JP2006331006A - Method for suppressing wiring congestion of lsi layout - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently suppress the wiring congestion of LSI layout in the stage of logic synthesis and the stage of layout design. <P>SOLUTION: A layout netlist is prepared by replacing the same logical function as that of a use inhibition cell with the internal connection logic synthesis cell of a logical synthesis cell library for performing logic synthesis by using a logic synthesis cell library, without using any registered use inhibition cell. The layout cells are automatically arranged in a layout netlist obtained by the logic synthesis by using the layout cell library. The possibility of the internal connection is determined in the layout obtained by automatic arrangement, and when there is any possibility of internal connection, the layout cells are replaced with the internal connection type layout cells registered in the layout cell library. The possibility of wiring congestion is determined in the layout obtained by automatic arrangement, and when there is any possibility of wiring congestion, the layout cells are replaced with the other layout cells with different pin arrangement registered in the layout cell library. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a wiring congestion suppression method for a layout that suppresses wiring congestion that may occur in multilayer wiring of an integrated circuit.

  With the realization of a semiconductor integrated circuit capable of operating on a large scale and at a high speed, it is necessary to reduce the chip area of the semiconductor integrated circuit and the layout design time. For this reason, manual design has become difficult, and automatic design by computers has been generally performed. In the computer, automatic placement and routing of cells is performed based on layout netlist information and information prepared for each cell. At this time, the cell-by-cell layout used is called an automatic placement and routing layout cell.

In the conventional case, a layout netlist is generated by logic synthesis, read into a layout placement and wiring program, automatically placed based on net connection information between layout cells, and automatic wiring is performed.
Japanese Patent Laid-Open No. 11-312185 (page 4-5, FIG. 1)

  However, in the case of the above-mentioned conventional technology, depending on the state of automatic placement, wiring congestion may occur when performing automatic wiring, and for the nets that could not be connected due to wiring congestion, bypass wiring is used for wiring connection Therefore, the wiring efficiency is lowered.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to efficiently suppress wiring congestion in an LSI layout at a logic synthesis stage and a layout design stage.

An LSI layout wiring congestion suppressing method according to the present invention includes:
Creating a layout netlist by performing logic synthesis from design data using a logic synthesis cell library;
Estimating wiring congestion in the layout netlist obtained by the logic synthesis;
Adding a mark to a cell instance of the layout netlist for a place where wiring congestion is estimated;
And using a layout cell library, automatically placing layout cells so that the marked layout cells are not placed close to each other.

  According to this, the wiring congestion of the layout net list obtained by logic synthesis is estimated and a cell instance is marked, and in the automatic placement of layout cells based on the layout net list, the mark indicating the wiring congestion is used as an index. The layout cells having the mark are not arranged close to each other, but are arranged in a distributed manner, whereby wiring congestion in the LSI layout can be efficiently suppressed.

  In the above, it is preferable that the wiring congestion estimation step estimates the wiring congestion on the basis of the number of nets connecting each layout cell from a single pin in the layout net list. . It is possible to estimate the wiring congestion in a portion where many nets are connected.

In addition, a wiring congestion suppression method for LSI layout according to the present invention is as follows.
Registering a logic synthesis cell that is expected to be congested in the logic synthesis cell library in advance as a prohibited cell;
Performing logic synthesis from design data using the logic synthesis cell library, and creating a layout netlist by performing logic synthesis under the condition not to use prohibited cells registered in the logic synthesis cell library;
And automatically arranging layout cells in the layout netlist obtained by the logic synthesis.

  According to this, a logic synthesis cell in which wiring congestion is expected is registered in the logic synthesis cell library in advance as a use-prohibited cell, and when the logic synthesis cell corresponds to a use-disabled cell, Since logic synthesis is performed without using a synthesis cell, it is possible to efficiently suppress wiring congestion in the LSI layout.

In addition, a wiring congestion suppression method for LSI layout according to the present invention is as follows.
Registering multiple patterns of layout cells with different pin arrangements in the layout cell library in advance,
Creating a layout netlist by performing logic synthesis from design data using a logic synthesis cell library;
Automatically arranging layout cells in the layout netlist obtained by the logic synthesis using the layout cell library;
Determining the possibility of wiring congestion in the layout obtained by the automatic placement, and replacing with another layout cell having a different pin arrangement registered in the layout cell library when there is a possibility of wiring congestion.

  According to this, a plurality of patterns of layout cells having different pin arrangements are registered in the layout cell library in advance, and when there is a possibility of wiring congestion in the automatic arrangement layout, it is replaced with another layout cell having different pin arrangements. Therefore, variations in pin connection during automatic wiring can be increased, and wiring congestion in the LSI layout can be efficiently suppressed.

In addition, a wiring congestion suppression method for LSI layout according to the present invention is as follows.
In the layout cell library, a step of registering a plurality of patterns as an internal connection type layout cell as a cell that is automatically wire-connected inside the cell if it is arranged adjacent to each logic synthesis cell;
Creating a layout netlist by performing logic synthesis from design data using a logic synthesis cell library;
Automatically arranging layout cells in the layout netlist obtained by the logic synthesis using the layout cell library;
Determining the possibility of internal connection in the layout obtained by the automatic arrangement, and replacing the internal connection type layout cell registered in the layout cell library when there is a possibility of internal connection.

  According to this, a plurality of patterns of internally connected layout cells (cells that are automatically connected to each other if they are arranged adjacent to each logic synthesis cell) are registered in the layout cell library in advance, When there is a possibility of internal connection in the layout obtained by automatic placement, it is replaced with the internal connection cell, so the variation of cell selection for optimal wiring according to the situation at the time of layout wiring can be increased, and the wiring area Can be reduced, and the wiring congestion of the LSI layout can be efficiently suppressed.

In addition, a wiring congestion suppression method for LSI layout according to the present invention is as follows.
Registering a logic synthesis cell that is expected to be congested in the logic synthesis cell library in advance as a prohibited cell;
Registering multiple patterns of layout cells with different pin arrangements in the layout cell library in advance,
Performing logic synthesis from design data using the logic synthesis cell library, and creating a layout netlist by performing logic synthesis under the condition not to use prohibited cells registered in the logic synthesis cell library;
Automatically arranging layout cells in the layout netlist obtained by the logic synthesis using the layout cell library;
Determining the possibility of wiring congestion in the layout obtained by the automatic placement, and replacing with another layout cell having a different pin arrangement registered in the layout cell library when there is a possibility of wiring congestion.

  Here, the step of registering prohibited cells in the logic synthesis cell library in advance and the step of registering multiple patterns of layout cells having different pin arrangements in the layout cell library in advance are arbitrary in the order.

  According to this, a logic synthesis cell in which wiring congestion is expected is registered in the logic synthesis cell library in advance as a use-prohibited cell, and when the logic synthesis cell corresponds to a use-disabled cell, Logic synthesis is performed without using a synthesis cell. In addition, if multiple patterns of layout cells with different pin assignments are registered in the layout cell library in advance and there is a possibility of wiring congestion in the automatic placement layout, it is replaced with another layout cell with different pin assignments. Variations for pin connection can be increased during wiring. As a result, the wiring congestion of the LSI layout can be suppressed sufficiently efficiently.

In addition, a wiring congestion suppression method for LSI layout according to the present invention is as follows.
Registering a logic synthesis cell that is expected to be congested in the logic synthesis cell library in advance as a prohibited cell;
In the layout cell library, a step of registering a plurality of patterns as an internally connected layout cell by automatically wiring-connecting cells inside the cell if arranged adjacent to each logic synthesis cell;
Performing logic synthesis from design data using the logic synthesis cell library, and creating a layout netlist by performing logic synthesis under the condition not to use prohibited cells registered in the logic synthesis cell library;
Automatically arranging layout cells in the layout netlist obtained by the logic synthesis using the layout cell library;
Determining the possibility of internal connection in the layout obtained by the automatic arrangement, and replacing the internal connection type layout cell registered in the layout cell library when there is a possibility of internal connection.

  Here, the step of registering prohibited cells in the logic synthesis cell library in advance and the step of registering a plurality of patterns of internally connected layout cells in the layout cell library in advance are arbitrary in the order.

  According to this, a logic synthesis cell in which wiring congestion is expected is registered in the logic synthesis cell library in advance as a use-prohibited cell, and when the logic synthesis cell corresponds to a use-disabled cell, Logic synthesis is performed without using a synthesis cell. In addition, multiple patterns of internally connected layout cells (cells that are automatically connected to each other if they are placed adjacent to each logic synthesis cell) are registered in the layout cell library in advance and automatically placed. When there is a possibility of internal connection in the layout obtained in (1), it is replaced with an internal connection cell, so the variation of cell selection for optimal wiring according to the situation at the time of layout wiring can be increased, and the wiring area can be reduced. Is possible. As a result, the wiring congestion of the LSI layout can be suppressed sufficiently efficiently.

In addition, a wiring congestion suppression method for LSI layout according to the present invention is as follows.
Registering multiple patterns of layout cells with different pin arrangements in the layout cell library in advance,
In the layout cell library, a step of registering a plurality of patterns as an internal connection type layout cell as a cell that is automatically wire-connected inside the cell if arranged adjacent to each logic synthesis cell;
Creating a layout netlist by performing logic synthesis from design data using a logic synthesis cell library;
Automatically arranging layout cells in the layout netlist obtained by the logic synthesis using the layout cell library;
Determining the possibility of internal connection in the layout obtained by the automatic placement, and replacing the internal connection type layout cell registered in the layout cell library when there is a possibility of internal connection;
Determining the possibility of wiring congestion in the layout obtained by the automatic placement, and replacing with another layout cell having a different pin arrangement registered in the layout cell library when there is a possibility of wiring congestion.

  Here, the step of registering multiple patterns of layout cells with different pin arrangements in the layout cell library in advance and the step of registering multiple patterns of internally connected layout cells in the layout cell library in advance are as follows. It is optional.

  According to this, a plurality of patterns of internally connected layout cells (cells that are automatically connected to each other if they are arranged adjacent to each logic synthesis cell) are registered in the layout cell library in advance, When there is a possibility of internal connection in the layout obtained by automatic placement, it is replaced with the internal connection cell, so the variation of cell selection for optimal wiring according to the situation at the time of layout wiring can be increased, and the wiring area Can be reduced. In addition, if multiple patterns of layout cells with different pin assignments are registered in the layout cell library in advance and there is a possibility of wiring congestion in the automatic placement layout, it is replaced with another layout cell with different pin assignments. Variations for pin connection can be increased during wiring. As a result, the wiring congestion of the LSI layout can be suppressed sufficiently efficiently.

In addition, a wiring congestion suppression method for LSI layout according to the present invention is as follows.
Registering a logic synthesis cell that is expected to be congested in the logic synthesis cell library in advance as a prohibited cell;
If the logic synthesis cell library has the same logic function as that of the prohibited cell in advance and is placed adjacent to each logic synthesis cell, a cell that is automatically wire-connected inside the cell is connected to an internally connected logic synthesis cell. As a step of registering the multiple patterns,
In the layout cell library, a step of registering a plurality of patterns as an internally connected layout cell by automatically wiring-connecting cells inside the cell if arranged adjacent to each logic synthesis cell;
The logic synthesis cell library is used to perform logic synthesis from the design data, and at this time, the use prohibited cell registered in the logic synthesis cell library is not used, and the logic function same as that of the use prohibited cell is used. A step of creating a layout netlist by synthesizing with a condition to be replaced with an internally connected logic synthesis cell of the library;
Automatically arranging layout cells in the layout netlist obtained by the logic synthesis;
Determining the possibility of internal connection in the layout obtained by the automatic arrangement, and replacing the internal connection type layout cell registered in the layout cell library when there is a possibility of internal connection.

  Here, a step of registering prohibited cells in the logic synthesis cell library in advance, a step of registering a plurality of patterns of internally connected logic synthesis cells in the logic synthesis cell library in advance, and an internal connection type in the layout cell library in advance The step of registering a plurality of layout cell patterns is arbitrary in the order.

  According to this, a logic synthesis cell in which wiring congestion is expected is registered in advance in the logic synthesis cell library as a prohibited cell, and an internally connected logic synthesis cell having the same logical function as that of the prohibited cell (in each logic synthesis cell). In the case of logic synthesis, if the logic synthesis cell falls under a use-disabled cell, the logic synthesis is performed. Since logic synthesis is performed by replacing the internal connection logic synthesis cell without using a synthesis cell, wiring congestion in the LSI layout can be efficiently suppressed. In addition, multiple patterns of internally connected layout cells (cells that are automatically connected to each other if they are placed adjacent to each logic synthesis cell) are registered in the layout cell library in advance and automatically placed. When there is a possibility of internal connection in the layout obtained in (1), it is replaced with an internal connection cell, so the variation of cell selection for optimal wiring according to the situation at the time of layout wiring can be increased, and the wiring area can be reduced. Is possible. As a result, it is possible to more efficiently suppress the wiring congestion of the LSI layout.

In addition, a wiring congestion suppression method for LSI layout according to the present invention is as follows.
Registering a logic synthesis cell that is expected to be congested in the logic synthesis cell library in advance as a prohibited cell;
In the layout cell library, a step of registering a plurality of patterns as an internally connected layout cell by automatically wiring-connecting cells inside the cell if arranged adjacent to each logic synthesis cell;
Registering in advance a plurality of patterns of layout cells having different pin arrangements in the layout cell library;
Performing logic synthesis from design data using the logic synthesis cell library, and creating a layout netlist by performing logic synthesis under the condition not to use prohibited cells registered in the logic synthesis cell library;
Automatically arranging layout cells in the layout netlist obtained by the logic synthesis using the layout cell library;
Determining the possibility of internal connection in the layout obtained by the automatic placement, and replacing the internal connection type layout cell registered in the layout cell library when there is a possibility of internal connection;
Determining the possibility of wiring congestion in the layout obtained by the automatic placement, and replacing with another layout cell having a different pin arrangement registered in the layout cell library when there is a possibility of wiring congestion.

  Here, the step of registering prohibited cells in the logic synthesis cell library in advance, the step of registering a plurality of patterns of internally connected layout cells in the layout cell library in advance, and the pin arrangement in the layout cell library in advance are different. The step of registering a plurality of layout cell patterns is arbitrary in the order.

  According to this, a logic synthesis cell in which wiring congestion is expected is registered in the logic synthesis cell library in advance as a use-prohibited cell, and when the logic synthesis cell corresponds to a use-disabled cell, Since logic synthesis is performed without using a synthesis cell, it is possible to efficiently suppress wiring congestion in the LSI layout. In addition, multiple patterns of internally connected layout cells (cells that are automatically connected to each other if they are placed adjacent to each logic synthesis cell) are registered in the layout cell library in advance and automatically placed. When there is a possibility of internal connection in the layout obtained in (1), it is replaced with an internal connection cell, so the variation of cell selection for optimal wiring according to the situation at the time of layout wiring can be increased, and the wiring area can be reduced. Is possible. In addition, if multiple patterns of layout cells with different pin arrangements are registered in the layout cell library in advance, and there is a possibility of wiring congestion in the automatic arrangement layout, it is replaced with another layout cell with different pin arrangements, and automatic wiring is performed. Sometimes variations on pin connections can be increased. As a result, it is possible to more efficiently suppress the wiring congestion of the LSI layout.

In addition, a wiring congestion suppression method for LSI layout according to the present invention is as follows.
Registering a logic synthesis cell that is expected to be congested in the logic synthesis cell library in advance as a prohibited cell;
If the logic synthesis cell library has the same logic function as that of the prohibited cell in advance and is placed adjacent to each logic synthesis cell, a cell that is automatically wire-connected inside the cell is connected to an internally connected logic synthesis cell. As a step of registering the multiple patterns,
In the layout cell library, a step of registering a plurality of patterns as an internal connection type layout cell as a cell that is automatically wire-connected inside the cell if it is arranged adjacent to each logic synthesis cell;
Registering in advance a plurality of patterns of layout cells having different pin arrangements in the layout cell library;
The logic synthesis cell library is used to perform logic synthesis from the design data, and at this time, the use prohibited cell registered in the logic synthesis cell library is not used, and the logic function same as that of the use prohibited cell is used. A step of creating a layout netlist by synthesizing with a condition to be replaced with an internally connected logic synthesis cell of the library;
Automatically arranging layout cells in the layout netlist obtained by the logic synthesis using the layout cell library;
Determining the possibility of internal connection in the layout obtained by the automatic placement, and replacing the internal connection type layout cell registered in the layout cell library when there is a possibility of internal connection;
Determining the possibility of wiring congestion in the layout obtained by the automatic placement, and replacing with another layout cell having a different pin arrangement registered in the layout cell library when there is a possibility of wiring congestion.

  Here, a step of registering prohibited cells in the logic synthesis cell library in advance, a step of registering a plurality of patterns of internally connected logic synthesis cells in the logic synthesis cell library in advance, and an internal connection type in the layout cell library in advance The step of registering a plurality of patterns of layout cells and the step of registering a plurality of patterns of layout cells having different pin arrangements in advance in the layout cell library are arbitrary in their order.

  According to this, similarly to the above, it is possible to extremely efficiently suppress the wiring congestion of the LSI layout over the logic synthesis stage and the layout stage.

In the above configuration, between the logic synthesis step and the layout cell automatic placement step,
Estimating wiring congestion in the layout netlist obtained by the logic synthesis;
Adding a mark to a cell instance of the layout netlist for a place where wiring congestion is estimated,
In the step of automatically arranging the layout cells, it is also preferable that the layout cells are automatically arranged using the layout cell library so that the layout cells with the marks are not arranged close to each other.

  Further, in the above, the use-prohibited cell is a logic synthesis cell having three or more input / output pins in one logic synthesis cell and having a narrow inter-pin width of 1 GRID (minimum width unit in layout) in the layout cell. It is preferable that there is.

  Further, in the above, it is preferable that the other layout cells having different pin arrangements have the same layout cell area and function and have different positions with respect to the wiring layers of the pins coming out of the layout cells. Different cells with different pin wiring layers can be selected in accordance with the degree of wiring congestion.

  Further, in the above, another layout cell having a different pin arrangement may have the same layout cell area and function, and different positions of pins extending from the layout cell in the horizontal and vertical directions.

  Also, in the above, the internal connection logic synthesis cell is preferably a logic synthesis cell having no more than three input / output pins and one-to-one connection between each input pin and output pin.

  According to the present invention, locations where wiring congestion is estimated can be dispersed, local wiring congestion can be avoided, and wiring congestion in the LSI layout can be efficiently suppressed while avoiding bypass wiring.

  In logic synthesis and layout, logic synthesis cells that are expected to be congested, such as narrow pin-to-pin widths, are disabled, replaced with other layout cells with different pin arrangements, or replaced with internally connected layout cells. Accordingly, it is possible to efficiently suppress the wiring congestion of the LSI layout while avoiding the bypass wiring.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of an LSI layout wiring congestion suppressing method according to the present invention will be described below in detail with reference to the drawings.

  First, a logic synthesis cell related to an LSI layout wiring congestion suppression method in an embodiment of the present invention will be described.

  The logic synthesis cell shown in FIGS. 1A and 1B has three or more input / output pins. In the case of FIG. 1A, the pin-to-pin width is 2GRID, but in the case of FIG. 1B, the pin-to-pin width is as narrow as 1GRID, and the wiring does not pass through, so a bypass wiring occurs. To do. By disabling this, detour wiring can be suppressed.

  2A, 2B, and 2C show logic synthesis cells having the same function, and the positions of the pins are different. In the case of FIG. 2A, as a result of automatic wiring, detour wiring occurs due to other wiring. On the other hand, in the case of FIGS. 2B and 2C, the alternate wiring is eliminated by replacing with another layout cell having a different pin arrangement. As described above, even when the same semiconductor integrated circuit is realized, the wiring area in FIG. 2A is wastefully consumed for the bypass wiring, whereas FIGS. 2B and 2C. Can be efficiently wired and does not use the wiring area in vain.

  3A and 3B show connection states of logic synthesis cells having the same function, and the connection states of the pins are different. In the case of FIG. 3A, wiring is performed for the pins coming out of the cell. On the other hand, in the case of FIG.3 (b), it connects with the cell which adjoins inside a cell. Thus, even when realizing the same semiconductor integrated circuit, the wiring region is used in FIG. 3A, and the wiring region is not used in FIG. 3B for connection inside the cell.

  Hereinafter, several aspects of the method for suppressing wiring congestion in an LSI layout according to an embodiment of the present invention will be described.

(1) Method for suppressing wiring congestion according to the flowchart of FIG. 4 In step S1, a logic net is generated from design data D1 using a logic synthesis cell library L1 to create a layout netlist.

  Next, in step S2, the wiring congestion in the layout netlist is estimated. As a condition for estimating the wiring congestion, for example, a cell to which five or more nets are connected from one output terminal on the layout net list is searched.

  Next, in step S3, a mark is added to the cell instance of the layout net list at a place where wiring congestion is estimated.

  Next, in step S4, the layout cell library L2 is used to avoid layout cells having marks in the cell instance in step S3 from the layout net list obtained in step S1, so that they are not placed close to each other. Automatically arrange cells.

  Next, in step S7, automatic rough wiring is performed.

  Next, in step S10, automatic detailed wiring is performed.

  This method estimates the wiring congestion of the layout netlist obtained by logic synthesis and marks the cell instance. In automatic layout cell placement based on the layout netlist, the mark indicating the wiring congestion is used as an index. Thus, by controlling the layout cells with the marks so as not to be arranged close to each other, it is possible to efficiently suppress the wiring congestion of the LSI layout. As a result, it is possible to suppress the loss of costs due to the backtracking process through shortening the layout design time.

(2) Wiring congestion suppression method according to the flowchart of FIG. 5 In step M1, in advance, input / output pins with 3 or more pins and pin-to-pin width of 1GRID are set as prohibited cells and registered in the logic synthesis cell library L1. deep.

  In step S1, a logic net is generated from the design data D1 using the logic synthesis cell library L1 to create a layout netlist. At the time of this logic synthesis, use-prohibited cells registered in advance in the logic synthesis cell library L1 are not adopted.

  Next, in step S4, cells are automatically arranged on the layout net list obtained in step S1, using the layout cell library L2.

  Next, in step S7, automatic rough wiring is performed.

  Next, in step S10, automatic detailed wiring is performed.

  According to this method, the use of prohibited cells registered in advance in the logic synthesis cell library L1 is suppressed in logic synthesis. Therefore, in the final wiring, there is no logic synthesis cell having a pin-to-pin width of 1 GRID, and wiring is performed. Space to pass through can be secured. And wiring congestion can be avoided and wiring efficiency can be improved. That is, the layout design time can be shortened and the cost loss caused by the backtracking process can be suppressed.

(3) Wiring congestion suppression method according to the flowchart of FIG. 6 This is different from FIG. 5 in the addition of step S2 and step S3.

  That is, step S2 and step S3 are added between step S1 and step S4.

  In step S2, wiring congestion in the layout netlist is estimated. That is, a cell to which five or more nets are connected from one output terminal on the layout net list is searched.

  Next, in step S3, a mark is added to the cell instance of the layout net list at a place where wiring congestion is estimated.

  Next, in step S4, using the layout cell library L2, cells are automatically arranged from the layout net list obtained in step S1 so as not to be close to the cell instance with the mark in step S3.

  Others are the same as FIG.

  According to this method, when a logic synthesis cell corresponds to a prohibited cell, logic synthesis is performed without using the logic synthesis cell, and close arrangement is avoided when there is a possibility of wiring congestion. Further, it is possible to more efficiently suppress the wiring congestion of the LSI layout. As a result, it is possible to suppress the loss of costs due to the backtracking process through shortening the layout design time.

(4) Method for suppressing wiring congestion according to the flowchart of FIG. 7 In step N1, a plurality of different layout cells having different pin arrangements are prepared for each logic synthesis cell and registered in the layout cell library L2.

  In step S1, a logic net is generated from the design data D1 using the logic synthesis cell library L1 to create a layout netlist.

  Next, in step S4, cells are automatically arranged on the layout net list obtained in step S1, using the layout cell library L2.

  Next, in step S7, automatic rough wiring is performed.

  Next, in step S8, it is determined whether or not there is a possibility that the wiring is congested in the layout obtained by the automatic schematic arrangement in step S7. When there is a possibility of wiring congestion, the process proceeds to step S9, and a plurality of patterns of cells with different pin arrangements registered in the layout cell library L2 in advance in step N1 are processed for a portion where wiring congestion is expected. An appropriate one is selected, and the wiring congestion cell is replaced with a cell at another selected pin position. When No in step S8 and after step S9, the process proceeds to step S10 to perform automatic detailed wiring.

  According to this method, multiple patterns of layout cells with different pin arrangements are registered in the layout cell library in advance, and when there is a possibility of wiring congestion in the automatic arrangement layout, it is possible to use different layout cells with different pin arrangements. Therefore, variations in pin connection during automatic wiring can be increased, and wiring congestion in the LSI layout can be efficiently suppressed.

(5) Wiring congestion suppression method according to the flowchart of FIG. 8 This is different from FIG. 7 in the addition of step S2 and step S3.

  That is, step S2 and step S3 are added between step S1 and step S4.

  In step S2, wiring congestion in the layout netlist is estimated. That is, a cell to which five or more nets are connected from one output terminal on the layout net list is searched.

  Next, in step S3, a mark is added to the cell instance of the layout net list at a place where wiring congestion is estimated.

  Next, in step S4, using the layout cell library L2, cells are automatically arranged from the layout net list obtained in step S1 so as not to be close to the cell instance with the mark in step S3.

  Others are the same as in FIG.

  According to this method, when there is a possibility of wiring congestion in the layout of automatic placement, it is replaced with another layout cell having a different pin arrangement, and when there is a possibility of wiring congestion, close placement is avoided. Layout congestion can be more efficiently suppressed. As a result, it is possible to suppress the loss of costs due to the backtracking process through shortening the layout design time.

(6) Wiring congestion suppression method according to the flowchart of FIG. 9 In step N2, an internal connection type layout cell (a cell in which wiring is automatically connected inside a cell if adjacent cells are arranged) in advance in step N2. ) Are prepared and registered in the layout cell library L2.

  In step S1, a logic net is generated from the design data D1 using the logic synthesis cell library L1 to create a layout netlist.

  Next, in step S4, cells are automatically arranged on the layout net list obtained in step S1, using the layout cell library L2.

  Next, in step S5, internal connection is possible by referring to whether there is a net connection between adjacent cells in close cells and the information of the internal connection cells registered in the layout cell library L2 in advance in step N2. It is determined whether or not. In the case of Yes, it progresses to step S6 and it replaces with the cell which can be connected internally. When No in step S5 and after step S6, the process proceeds to step S7 to perform automatic rough wiring.

  Next, in step S10, automatic detailed wiring is performed.

  According to this method, a plurality of patterns of internally connected layout cells (cells that are automatically connected to each other if they are arranged adjacent to each logic synthesis cell) are registered in the layout cell library in advance. When there is a possibility of internal connection in the layout obtained by automatic placement, it is replaced with the internal connection cell, so the variation of cell selection for optimal wiring according to the situation at the time of layout wiring can be increased, and wiring The area can be reduced, and wiring congestion in the LSI layout can be efficiently suppressed.

(7) Wiring congestion suppression method according to the flowchart of FIG. 10 This is different from FIG. 9 in the addition of step S2 and step S3.

  In step S2, wiring congestion in the layout netlist is estimated. That is, a cell to which five or more nets are connected from one output terminal on the layout net list is searched.

  Next, in step S3, a mark is added to the cell instance of the layout net list at a place where wiring congestion is estimated.

  Next, in step S4, using the layout cell library L2, cells are automatically arranged from the layout net list obtained in step S1 so as not to be close to the cell instance with the mark in step S3.

  Others are the same as FIG.

  According to this method, when there is a possibility of internal connection in a layout obtained by automatic placement, it is replaced with an internal connection cell, and when there is a possibility of wiring congestion, close placement is avoided. Wiring congestion can be suppressed more efficiently. As a result, it is possible to suppress the loss of costs due to the backtracking process through shortening the layout design time.

(8) Wiring congestion suppression method according to the flowchart of FIG. 11 In step M1, in advance, input / output pins with 3 or more pins and pin-to-pin width of 1GRID are set as prohibited cells and registered in the logic synthesis cell library L1. deep. In step N1, a plurality of different layout cells having different pin arrangements are prepared for each logic synthesis cell in advance and registered in the layout cell library L2. The order of step M1 and step N1 is arbitrary.

  In step S1, a logic net is generated from the design data D1 using the logic synthesis cell library L1 to create a layout netlist. At the time of this logic synthesis, use-prohibited cells registered in advance in the logic synthesis cell library L1 are not adopted.

  Next, in step S4, cells are automatically arranged on the layout net list obtained in step S1, using the layout cell library L2.

  Next, in step S7, automatic rough wiring is performed.

  Next, in step S8, it is determined whether or not there is a possibility that the wiring is congested in the layout obtained by the automatic schematic arrangement in step S7. When there is a possibility of wiring congestion, the process proceeds to step S9, and a plurality of patterns of cells with different pin arrangements registered in the layout cell library L2 in advance in step N1 are processed for a portion where wiring congestion is expected. An appropriate one is selected, and the wiring congestion cell is replaced with a cell at another selected pin position. When No in step S8 and after step S9, the process proceeds to step S10 to perform automatic detailed wiring.

  According to this method, a logic synthesis cell in which wiring congestion is expected is registered in the logic synthesis cell library in advance as a use-prohibited cell, and when the logic synthesis cell falls under a use-disabled cell, Logic synthesis is performed without using a logic synthesis cell. In addition, if multiple patterns of layout cells with different pin assignments are registered in the layout cell library in advance and there is a possibility of wiring congestion in the automatic placement layout, it is replaced with another layout cell with different pin assignments. Variations for pin connection can be increased during wiring. As a result, the wiring congestion of the LSI layout can be suppressed sufficiently efficiently.

(9) Wiring congestion suppression method according to the flowchart of FIG. 12 This is different from FIG. 11 in the addition of step S2 and step S3.

  In step S2, wiring congestion in the layout netlist is estimated. That is, a cell to which five or more nets are connected from one output terminal on the layout net list is searched.

  Next, in step S3, a mark is added to the cell instance of the layout net list at a place where wiring congestion is estimated.

  Next, in step S4, using the layout cell library L2, cells are automatically arranged from the layout net list obtained in step S1 so as not to be close to the cell instance with the mark in step S3.

  Others are the same as FIG.

  According to this method, in addition to the operation of FIG. 11, close arrangement is avoided when there is a possibility of wiring congestion, so that it is possible to more efficiently suppress wiring congestion in the LSI layout. As a result, it is possible to suppress the loss of costs due to the backtracking process through shortening the layout design time.

(10) Wiring congestion suppression method according to the flowchart of FIG. 13 In step M1, in advance, input / output pins with 3 or more pins and pin-to-pin width of 1GRID are set as prohibited cells and registered in the logic synthesis cell library L1. deep. In step N2, a plurality of patterns of internally connected layout cells are prepared for each logic synthesis cell and registered in the layout cell library L2. The order of step M1 and step N2 is arbitrary.

  In step S1, a logic net is generated from the design data D1 using the logic synthesis cell library L1 to create a layout netlist. At the time of this logic synthesis, use-prohibited cells registered in advance in the logic synthesis cell library L1 are not adopted.

  Next, in step S4, cells are automatically arranged on the layout net list obtained in step S1, using the layout cell library L2.

  Next, in step S5, internal connection is possible by referring to whether there is a net connection between adjacent cells in close cells and the information of the internal connection cells registered in the layout cell library L2 in advance in step N2. It is determined whether or not. In the case of Yes, it progresses to step S6 and it replaces with the cell which can be connected internally. When No in step S5 and after step S6, the process proceeds to step S7 to perform automatic rough wiring.

  Next, in step S10, automatic detailed wiring is performed.

  According to this method, a logic synthesis cell in which wiring congestion is expected is registered in the logic synthesis cell library in advance as a use-prohibited cell, and when the logic synthesis cell falls under a use-disabled cell, Logic synthesis is performed without using a logic synthesis cell. In addition, multiple patterns of internal connection type layout cells are registered in the layout cell library in advance, and if there is a possibility of internal connection in the layout obtained by automatic placement, it is replaced with internal connection cells. Variations in cell selection for optimal wiring according to the situation can be increased, and the wiring area can be reduced. As a result, the wiring congestion of the LSI layout can be suppressed sufficiently efficiently.

(11) Wiring congestion suppression method according to the flowchart of FIG. 14 This is different from FIG. 13 in the addition of step S2 and step S3.

  In step S2, wiring congestion in the layout netlist is estimated. That is, a cell to which five or more nets are connected from one output terminal on the layout net list is searched.

  Next, in step S3, a mark is added to the cell instance of the layout net list at a place where wiring congestion is estimated.

  Next, in step S4, using the layout cell library L2, cells are automatically arranged from the layout net list obtained in step S1 so as not to be close to the cell instance with the mark in step S3.

  Others are the same as FIG.

  According to this method, in addition to the operation of FIG. 13, close arrangement is avoided when there is a possibility of wiring congestion, so that it is possible to more efficiently suppress wiring congestion in the LSI layout. As a result, it is possible to suppress the loss of costs due to the backtracking process through shortening the layout design time.

(12) Wiring congestion suppression method according to the flowchart of FIG. 15 In step N1, a plurality of different layout cells having different pin arrangements are prepared for each logic synthesis cell in advance and registered in the layout cell library L2. In step N2, a plurality of patterns of internally connected layout cells are prepared for each logic synthesis cell and registered in the layout cell library L2. The order of step N1 and step N2 is arbitrary.

  In step S1, a logic net is generated from the design data D1 using the logic synthesis cell library L1 to create a layout netlist.

  Next, in step S4, cells are automatically arranged on the layout net list obtained in step S1, using the layout cell library L2.

  Next, in step S5, internal connection is possible by referring to whether there is a net connection between adjacent cells in close cells and the information of the internal connection cells registered in the layout cell library L2 in advance in step N2. It is determined whether or not. In the case of Yes, it progresses to step S6 and it replaces with the cell which can be connected internally. When No in step S5 and after step S6, the process proceeds to step S7 to perform automatic rough wiring.

  Next, in step S8, it is determined whether or not there is a possibility that the wiring is congested in the layout obtained by the automatic schematic arrangement in step S7. When there is a possibility of wiring congestion, the process proceeds to step S9, and a plurality of patterns of cells with different pin arrangements registered in the layout cell library L2 in advance in step N1 are processed for a portion where wiring congestion is expected. An appropriate one is selected, and the wiring congestion cell is replaced with a cell at another selected pin position. When No in step S8 and after step S9, the process proceeds to step S10 to perform automatic detailed wiring.

  According to this method, a plurality of patterns of internally connected layout cells are registered in advance in the layout cell library, and when there is a possibility of internal connection in a layout obtained by automatic placement, it is replaced with an internally connected cell. Variations in cell selection for optimal wiring according to the situation at the time of layout wiring can be increased, and the wiring area can be reduced. In addition, if multiple patterns of layout cells with different pin assignments are registered in the layout cell library in advance and there is a possibility of wiring congestion in the automatic placement layout, it is replaced with another layout cell with different pin assignments. Variations for pin connection can be increased during wiring. As a result, the wiring congestion of the LSI layout can be suppressed sufficiently efficiently.

(13) Wiring congestion suppression method according to the flowchart of FIG. 16 This is different from FIG. 15 in the addition of step S2 and step S3.

  In step S2, wiring congestion in the layout netlist is estimated. That is, a cell to which five or more nets are connected from one output terminal on the layout net list is searched.

  Next, in step S3, a mark is added to the cell instance of the layout net list at a place where wiring congestion is estimated.

  Next, in step S4, using the layout cell library L2, cells are automatically arranged from the layout net list obtained in step S1 so as not to be close to the cell instance with the mark in step S3.

  Others are the same as FIG.

  According to this method, in addition to the operation of FIG. 15, close arrangement is avoided when there is a possibility of wiring congestion, so that wiring congestion in the LSI layout can be more efficiently suppressed. As a result, it is possible to suppress the loss of costs due to the backtracking process through shortening the layout design time.

(14) Wiring congestion suppression method according to the flowchart of FIG. 17 In step M1, in advance, input / output pins with 3 or more pins and pin-to-pin width of 1GRID are set as prohibited cells and registered in the logic synthesis cell library L1. deep. In step M2, an internal connection logic synthesis cell capable of internal connection is registered in advance in the logic synthesis cell library L1. Further, in step N2, a plurality of patterns of internally connected layout cells are prepared for each logic synthesis cell in advance and registered in the layout cell library L2. The order of step M1, step M2, and step N1 is arbitrary.

  In step S1, a logic net is generated from the design data D1 using the logic synthesis cell library L1 to create a layout netlist. In this logic synthesis, use-prohibited cells registered in advance in the logic synthesis cell library L1 are not adopted, and logic synthesis is performed by replacing them with internally connected logic synthesis cells registered in advance in the logic synthesis cell library L1. .

  Next, in step S4, cells are automatically arranged on the layout net list obtained in step S1, using the layout cell library L2.

  Next, in step S5, internal connection is possible by referring to whether there is a net connection between adjacent cells in close cells and the information of the internal connection cells registered in the layout cell library L2 in advance in step N2. It is determined whether or not. In the case of Yes, it progresses to step S6 and it replaces with the cell which can be connected internally. When No in step S5 and after step S6, the process proceeds to step S7 to perform automatic rough wiring.

  Next, in step S10, automatic detailed wiring is performed.

  According to this method, logic synthesis cells that are expected to be congested are registered in advance in the logic synthesis cell library as prohibited cells, and multiple patterns of interconnected logic synthesis cells having the same logic function as the prohibited cells are registered. In the logic synthesis, if the logic synthesis cell corresponds to a use-inhibited cell, the logic synthesis is performed by replacing the internal cell synthesis cell without using the logic synthesis cell. Can be efficiently suppressed. In addition, multiple patterns of internal connection type layout cells are registered in the layout cell library in advance, and if there is a possibility of internal connection in the layout obtained by automatic placement, it is replaced with internal connection cells. Variations in cell selection for optimal wiring according to the situation can be increased, and the wiring area can be reduced. As a result, it is possible to more efficiently suppress the wiring congestion of the LSI layout.

(15) Wiring congestion suppression method according to the flowchart of FIG. 18 This is different from FIG. 17 in the addition of step S2 and step S3.

  In step S2, wiring congestion in the layout netlist is estimated. That is, a cell to which five or more nets are connected from one output terminal on the layout net list is searched.

  Next, in step S3, a mark is added to the cell instance of the layout net list at a place where wiring congestion is estimated.

  Next, in step S4, using the layout cell library L2, cells are automatically arranged from the layout net list obtained in step S1 so as not to be close to the cell instance with the mark in step S3.

  Others are the same as FIG.

  According to this method, in addition to the operation of FIG. 17, close arrangement is avoided when there is a possibility of wiring congestion, so that wiring congestion in the LSI layout can be more efficiently suppressed. As a result, it is possible to suppress the loss of costs due to the backtracking process through shortening the layout design time.

(16) Wiring congestion suppression method according to the flowchart of FIG. 19 In step M1, in advance, input / output pins with 3 or more pins and pin-to-pin width of 1GRID are set as prohibited cells and registered in the logic synthesis cell library L1. deep. In step N1, a plurality of different layout cells having different pin arrangements are prepared for each logic synthesis cell in advance and registered in the layout cell library L2. Further, in step N2, a plurality of patterns of internally connected layout cells are prepared for each logic synthesis cell in advance and registered in the layout cell library L2. The order of step M1, step N1, and step N2 is arbitrary.

  In step S1, a logic net is generated from the design data D1 using the logic synthesis cell library L1 to create a layout netlist. At the time of this logic synthesis, use-prohibited cells registered in advance in the logic synthesis cell library L1 are not adopted.

  Next, in step S4, cells are automatically arranged on the layout net list obtained in step S1, using the layout cell library L2.

  Next, in step S5, internal connection is possible by referring to whether there is a net connection between adjacent cells in close cells and the information of the internal connection cells registered in the layout cell library L2 in advance in step N2. It is determined whether or not. In the case of Yes, it progresses to step S6 and it replaces with the cell which can be connected internally. When No in step S5 and after step S6, the process proceeds to step S7 to perform automatic rough wiring.

  Next, in step S8, it is determined whether or not there is a possibility that the wiring is congested in the layout obtained by the automatic schematic arrangement in step S7. When there is a possibility of wiring congestion, the process proceeds to step S9, and a plurality of patterns of cells with different pin arrangements registered in the layout cell library L2 in advance in step N1 are processed for a portion where wiring congestion is expected. An appropriate one is selected, and the wiring congestion cell is replaced with a cell at another selected pin position. When No in step S8 and after step S9, the process proceeds to step S10 to perform automatic detailed wiring.

  According to this method, a logic synthesis cell in which wiring congestion is expected is registered in advance in the logic synthesis cell library as a prohibited cell, and when the logic synthesis cell corresponds to a prohibited cell, Since logic synthesis is performed without using a logic synthesis cell, wiring congestion in the LSI layout can be efficiently suppressed. In addition, multiple patterns of internal connection type layout cells are registered in the layout cell library in advance, and if there is a possibility of internal connection in the layout obtained by automatic placement, it is replaced with internal connection cells. Variations in cell selection for optimal wiring according to the situation can be increased, and the wiring area can be reduced. Furthermore, if multiple patterns of layout cells with different pin arrangements are registered in the layout cell library in advance, and there is a possibility of wiring congestion in the automatic arrangement layout, it is replaced with another layout cell with different pin arrangements, and automatic wiring is performed. Sometimes variations on pin connections can be increased. As a result, it is possible to more efficiently suppress the wiring congestion of the LSI layout.

(17) Wiring congestion suppression method according to the flowchart of FIG. 20 This is different from FIG. 19 in the addition of step S2 and step S3.

  In step S2, wiring congestion in the layout netlist is estimated. That is, a cell to which five or more nets are connected from one output terminal on the layout net list is searched.

  Next, in step S3, a mark is added to the cell instance of the layout net list at a place where wiring congestion is estimated.

  Next, in step S4, using the layout cell library L2, cells are automatically arranged from the layout net list obtained in step S1 so as not to be close to the cell instance with the mark in step S3.

  Others are the same as FIG.

  According to this method, in addition to the operation of FIG. 19, close arrangement is avoided when there is a possibility of wiring congestion, so that wiring congestion in the LSI layout can be more efficiently suppressed. As a result, it is possible to suppress the loss of costs due to the backtracking process through shortening the layout design time.

(18) Wiring congestion suppression method according to the flowchart of FIG. 21 In advance, in step M1, an input / output pin having three or more pins and a pin-to-pin width of 1GRID is set as a prohibited cell and registered in the logic synthesis cell library L1. deep. In step M2, an internal connection logic synthesis cell capable of internal connection is registered in advance in the logic synthesis cell library L1. In step N1, a plurality of different layout cells having different pin arrangements are prepared for each logic synthesis cell in advance and registered in the layout cell library L2. Further, in step N2, a plurality of patterns of internally connected layout cells are prepared for each logic synthesis cell in advance and registered in the layout cell library L2. The order of step M1, step M2, step N1, and step N2 is arbitrary.

  In step S1, a logic net is generated from the design data D1 using the logic synthesis cell library L1 to create a layout netlist. At the time of this logic synthesis, use-prohibited cells registered in advance in the logic synthesis cell library L1 are not adopted, and logic synthesis is performed by replacing them with internally connected logic synthesis cells registered in the logic synthesis cell library L1. .

  Next, in step S4, cells are automatically arranged on the layout net list obtained in step S1, using the layout cell library L2.

  Next, in step S5, internal connection is possible by referring to whether there is a net connection between adjacent cells in close cells and the information of the internal connection cells registered in the layout cell library L2 in advance in step N2. It is determined whether or not. In the case of Yes, it progresses to step S6 and it replaces with the cell which can be connected internally. When No in step S5 and after step S6, the process proceeds to step S7 to perform automatic rough wiring.

  Next, in step S8, it is determined whether or not there is a possibility that the wiring is congested in the layout obtained by the automatic schematic arrangement in step S7. When there is a possibility of wiring congestion, the process proceeds to step S9, and a plurality of patterns of cells with different pin arrangements registered in the layout cell library L2 in advance in step N1 are processed for a portion where wiring congestion is expected. An appropriate one is selected, and the wiring congestion cell is replaced with a cell at another selected pin position. When No in step S8 and after step S9, the process proceeds to step S10 to perform automatic detailed wiring.

  According to this method, similarly to the above, it is possible to extremely efficiently suppress the wiring congestion of the LSI layout over the logic synthesis stage and the layout stage.

(19) Method for suppressing wiring congestion in layout according to flowchart of FIG. 22 This is different from FIG. 21 in the addition of step S2 and step S3.

  In step S2, wiring congestion in the layout netlist is estimated. That is, a cell to which five or more nets are connected from one output terminal on the layout net list is searched.

  Next, in step S3, a mark is added to the cell instance of the layout net list at a place where wiring congestion is estimated.

  Next, in step S4, using the layout cell library L2, cells are automatically arranged from the layout net list obtained in step S1 so as not to be close to the cell instance with the mark in step S3.

  Others are the same as FIG.

  According to this method, in addition to the operation of FIG. 21, close arrangement is avoided when there is a possibility of wiring congestion, so that wiring congestion in the LSI layout can be more efficiently suppressed. As a result, it is possible to suppress the loss of costs due to the backtracking process through shortening the layout design time.

  The method for suppressing wiring congestion in an LSI layout according to the present invention enables suppression of wiring congestion at the time of logic synthesis and suppression of wiring congestion at the time of layout even if the miniaturization technology of the LSI manufacturing process advances. It is useful as a method for suppressing wiring congestion in a layout.

Explanatory drawing of the use prohibition cell of the wiring congestion suppression method of LSI layout in embodiment of this invention The figure which shows the several pattern of the layout cell from which pin arrangement differs by the wiring congestion suppression method of LSI layout in embodiment of this invention The figure which shows the cell which can be connected internally of the wiring congestion suppression method of LSI layout in embodiment of this invention Flowchart (1) of the LSI layout wiring congestion suppression method in the embodiment of the present invention Flowchart (2) of the method for suppressing wiring congestion of LSI layout in the embodiment of the present invention Flowchart (3) of the LSI layout wiring congestion suppression method in the embodiment of the present invention Flowchart (4) of the method for suppressing wiring congestion of LSI layout in the embodiment of the present invention Flowchart (5) of the LSI layout wiring congestion suppression method in the embodiment of the present invention Flowchart (6) of the LSI layout wiring congestion suppression method in the embodiment of the present invention Flowchart (7) of the LSI layout wiring congestion suppression method in the embodiment of the present invention Flowchart (8) of the LSI layout wiring congestion suppression method in the embodiment of the present invention Flowchart (9) of an LSI layout wiring congestion suppression method according to an embodiment of the present invention Flowchart (Part 10) of the method for suppressing wiring congestion in LSI layout in the embodiment of the present invention Flowchart (11) of the LSI layout wiring congestion suppression method in the embodiment of the present invention Flowchart (12) of the method for suppressing wiring congestion of LSI layout in the embodiment of the present invention Flowchart (13) of an LSI layout wiring congestion suppression method according to an embodiment of the present invention Flowchart (Part 14) of the method for suppressing wiring congestion in the LSI layout in the embodiment of the present invention Flowchart (15) of an LSI layout wiring congestion suppression method according to an embodiment of the present invention Flowchart (16) of the method for suppressing wiring congestion of LSI layout in the embodiment of the present invention Flowchart (17) of an LSI layout wiring congestion suppression method according to an embodiment of the present invention Flowchart (18) of an LSI layout wiring congestion suppression method according to an embodiment of the present invention Flowchart (19) of an LSI layout wiring congestion suppression method in an embodiment of the present invention

Explanation of symbols

D1 LSI design data L1 Logic synthesis cell library L2 Layout cell library M1 Designation of prohibited cells M2 Registration of internally connected logic synthesis cells N1 Registration of layout cells with different pin assignments N2 Registration of internally connected layout cells S1 Logic synthesis S2 Wiring congestion S3 Add a mark to a cell instance S4 Cell placement S5 Judgment of internal connection S6 Replacement of internal connection type layout cell S7 Automatic rough wiring S8 Congestion judgment S9 Replacement of another layout cell with different pin arrangement S10 Automatic detailed wiring

Claims (16)

Creating a layout netlist by performing logic synthesis from design data using a logic synthesis cell library;
Estimating wiring congestion in the layout netlist obtained by the logic synthesis;
Adding a mark to a cell instance of the layout netlist for a place where wiring congestion is estimated;
A method of suppressing wiring congestion in an LSI layout, comprising: using a layout cell library, and automatically placing layout cells so that the marked layout cells are not placed close to each other.   2. The wiring congestion estimation step according to claim 1, wherein in the layout net list, the wiring congestion is estimated based on the number of nets connected to each layout cell from a single pin. A method for suppressing wiring congestion in LSI layout. Registering a logic synthesis cell that is expected to be congested in the logic synthesis cell library in advance as a prohibited cell;
Performing logic synthesis from design data using the logic synthesis cell library, and creating a layout netlist by performing logic synthesis under the condition not to use prohibited cells registered in the logic synthesis cell library;
A method of suppressing wiring congestion of an LSI layout, including the step of automatically arranging layout cells in the layout netlist obtained by the logic synthesis. Registering multiple patterns of layout cells with different pin arrangements in the layout cell library in advance,
Creating a layout netlist by performing logic synthesis from design data using a logic synthesis cell library;
Automatically arranging layout cells in the layout netlist obtained by the logic synthesis using the layout cell library;
Determining the possibility of wiring congestion in the layout obtained by the automatic placement and replacing the layout cell with another layout cell having a different pin arrangement registered in the layout cell library when there is a possibility of wiring congestion. Wiring congestion control method. In the layout cell library, a step of registering a plurality of patterns as an internally connected layout cell by automatically wiring-connecting cells inside the cell if arranged adjacent to each logic synthesis cell;
Creating a layout netlist by performing logic synthesis from design data using a logic synthesis cell library;
Automatically arranging layout cells in the layout netlist obtained by the logic synthesis using the layout cell library;
Determining the possibility of internal connection in the layout obtained by the automatic placement, and replacing the internal connection type layout cell registered in the layout cell library when there is a possibility of internal connection with LSI layout wiring congestion Suppression method. Registering a logic synthesis cell that is expected to be congested in the logic synthesis cell library in advance as a prohibited cell;
Registering multiple patterns of layout cells with different pin arrangements in the layout cell library in advance,
Performing logic synthesis from design data using the logic synthesis cell library, and creating a layout netlist by performing logic synthesis under the condition not to use prohibited cells registered in the logic synthesis cell library;
Automatically arranging layout cells in the layout netlist obtained by the logic synthesis using the layout cell library;
Determining the possibility of wiring congestion in the layout obtained by the automatic placement and replacing the layout cell with another layout cell having a different pin arrangement registered in the layout cell library when there is a possibility of wiring congestion. Wiring congestion control method. Registering a logic synthesis cell that is expected to be congested in the logic synthesis cell library in advance as a prohibited cell;
In the layout cell library, a step of registering a plurality of patterns as an internal connection type layout cell as a cell that is automatically wire-connected inside the cell if it is arranged adjacent to each logic synthesis cell;
Performing logic synthesis from design data using the logic synthesis cell library, and creating a layout netlist by performing logic synthesis under the condition not to use prohibited cells registered in the logic synthesis cell library;
Automatically arranging layout cells in the layout netlist obtained by the logic synthesis using the layout cell library;
Determining the possibility of internal connection in the layout obtained by the automatic placement, and replacing the internal connection type layout cell registered in the layout cell library when there is a possibility of internal connection with LSI layout wiring congestion Suppression method. Registering multiple patterns of layout cells with different pin arrangements in the layout cell library in advance,
In the layout cell library, a step of registering a plurality of patterns as an internal connection type layout cell as a cell that is automatically wire-connected inside the cell if arranged adjacent to each logic synthesis cell;
Creating a layout netlist by performing logic synthesis from design data using a logic synthesis cell library;
Automatically arranging layout cells in the layout netlist obtained by the logic synthesis using the layout cell library;
Determining the possibility of internal connection in the layout obtained by the automatic placement, and replacing the internal connection type layout cell registered in the layout cell library when there is a possibility of internal connection;
Determining the possibility of wiring congestion in the layout obtained by the automatic placement and replacing the layout cell with another layout cell having a different pin arrangement registered in the layout cell library when there is a possibility of wiring congestion. Wiring congestion control method. Registering a logic synthesis cell that is expected to be congested in the logic synthesis cell library in advance as a prohibited cell;
If the logic synthesis cell library has the same logic function as that of the prohibited cell in advance and is placed adjacent to each logic synthesis cell, a cell that is automatically wire-connected inside the cell is connected to an internally connected logic synthesis cell. As a step of registering the multiple patterns,
In the layout cell library, a step of registering a plurality of patterns as an internally connected layout cell by automatically wiring-connecting cells inside the cell if arranged adjacent to each logic synthesis cell;
The logic synthesis cell library is used to perform logic synthesis from the design data, and at this time, the use prohibited cell registered in the logic synthesis cell library is not used, and the logic function same as that of the use prohibited cell is used. A step of creating a layout netlist by synthesizing with a condition to be replaced with an internally connected logic synthesis cell of the library;
Automatically arranging layout cells in the layout netlist obtained by the logic synthesis;
Determining the possibility of internal connection in the layout obtained by the automatic placement, and replacing the internal connection type layout cell registered in the layout cell library when there is a possibility of internal connection with LSI layout wiring congestion Suppression method. Registering a logic synthesis cell that is expected to be congested in the logic synthesis cell library in advance as a prohibited cell;
In the layout cell library, a step of registering a plurality of patterns as an internally connected layout cell by automatically wiring-connecting cells inside the cell if arranged adjacent to each logic synthesis cell;
Registering in advance a plurality of patterns of layout cells having different pin arrangements in the layout cell library;
Performing logic synthesis from design data using the logic synthesis cell library, and creating a layout netlist by performing logic synthesis under the condition not to use prohibited cells registered in the logic synthesis cell library;
Automatically arranging layout cells in the layout netlist obtained by the logic synthesis using the layout cell library;
Determining the possibility of internal connection in the layout obtained by the automatic placement, and replacing the internal connection type layout cell registered in the layout cell library when there is a possibility of internal connection;
Determining the possibility of wiring congestion in the layout obtained by the automatic placement and replacing the layout cell with another layout cell having a different pin arrangement registered in the layout cell library when there is a possibility of wiring congestion. Wiring congestion control method. Registering a logic synthesis cell that is expected to be congested in the logic synthesis cell library in advance as a prohibited cell;
If the logic synthesis cell library has the same logic function as that of the prohibited cell in advance and is placed adjacent to each logic synthesis cell, a cell that is automatically wire-connected inside the cell is connected to an internally connected logic synthesis cell. As a step of registering the multiple patterns,
In the layout cell library, a step of registering a plurality of patterns as an internally connected layout cell by automatically wiring-connecting cells inside the cell if arranged adjacent to each logic synthesis cell;
Registering in advance a plurality of patterns of layout cells having different pin arrangements in the layout cell library;
The logic synthesis cell library is used to perform logic synthesis from the design data, and at this time, the use prohibited cell registered in the logic synthesis cell library is not used, and the logic function same as that of the use prohibited cell is used. A step of creating a layout netlist by synthesizing with a condition to be replaced with an internally connected logic synthesis cell of the library;
Automatically arranging layout cells in the layout netlist obtained by the logic synthesis using the layout cell library;
Determining the possibility of internal connection in the layout obtained by the automatic placement, and replacing the internal connection type layout cell registered in the layout cell library when there is a possibility of internal connection;
Determining the possibility of wiring congestion in the layout obtained by the automatic placement and replacing the layout cell with another layout cell having a different pin arrangement registered in the layout cell library when there is a possibility of wiring congestion. Wiring congestion control method. Between the step of logic synthesis and the step of automatic placement of the layout cells,
Estimating wiring congestion in the layout netlist obtained by the logic synthesis;
Adding a mark to a cell instance of the layout netlist for a place where wiring congestion is estimated,
12. The layout cell is automatically arranged in the step of automatically arranging the layout cells by using the layout cell library so that the layout cells having the mark are not arranged close to each other. A method for suppressing wiring congestion in an LSI layout according to claim 1.   4. The use-prohibited cell is a logic synthesis cell having three or more input / output pins in one logic synthesis cell and having a narrow inter-pin width of 1 GRID (minimum width unit in layout) in the layout cell. An LSI layout wiring congestion suppression method according to claim 6, claim 7, claim 9, claim 10, or claim 11.   5. Another layout cell having a different pin arrangement has the same area and function as the layout cell, but is different in the position of the pin coming out of the layout cell with respect to the wiring layer. Item 12. The method for suppressing wiring congestion in an LSI layout according to Item 10 or Item 11.   The layout cells having different pin arrangements have the same layout cell area and function, and different positions of pins extending from the layout cells in the horizontal and vertical directions. 12. The method for suppressing wiring congestion in an LSI layout according to claim 10 or claim 11.   12. The LSI layout wiring congestion according to claim 9, wherein the internal connection logic synthesis cell is a logic synthesis cell having up to three input / output pins and each input pin and output pin being connected one-to-one. Suppression method.

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