JP2023084494A - Semiconductor device, photoelectric conversion device, photoelectric conversion system, and mobile body - Google Patents

Abstract

To provide a technique advantageous for suppressing a crosstalk noise.SOLUTION: A semiconductor device contains: a plurality of first power supply lines that is extended to a first direction, and is distributed to a second direction crossed to the first direction in a predetermined period on a main surface of a substrate; a plurality of second power supply lines that is arranged to a position separated from the main surface from the plurality of first power supply lines; a signal line that is extended to a first direction and a second direction between a first terminal and a second terminal, and electrically connects a first terminal and a second terminal; and a cell that to which a power is supplied from the two first power supply lines of the plurality of first power supply lines. The plurality of second power supply lines contains: a plurality of first wiring patterns extended to the first direction; and a plurality of second wiring patterns extended to the second direction. In an orthogonal projection to the main surface, the signal line is arranged so as to be housed in a region of the plurality of first wiring patterns and the plurality of second wiring patterns up to the second terminal from the first terminal. A signal line another than the signal line is not arranged between the signal line and the plurality of second power supply lines.SELECTED DRAWING: Figure 1

Description

The present invention relates to semiconductor devices, photoelectric conversion devices, photoelectric conversion systems, and moving bodies.

2. Description of the Related Art Crosstalk noise is known in which a voltage fluctuation in one signal line affects the quality of a signal flowing through another signal line in adjacent signal lines arranged in a semiconductor device. Japanese Patent Application Laid-Open No. 2002-201000 discloses that the influence of crosstalk is suppressed by repeatedly arranging power supply wiring and signal lines in one wiring layer.

Japanese Patent Application Laid-Open No. 2001-127162

In order to improve the quality of signals flowing through signal lines, it is necessary to further suppress the influence of crosstalk.

SUMMARY OF THE INVENTION An object of the present invention is to provide an advantageous technique for suppressing crosstalk noise.

In view of the above problems, a semiconductor device according to an embodiment of the present invention extends in a first direction on a main surface of a substrate and is arranged with a predetermined period in a second direction intersecting the first direction. a first power supply line, a plurality of second power supply lines arranged at a position further from the main surface than the plurality of first power supply lines, and a first terminal and a second terminal between the From a signal line extending in the first direction and the second direction and electrically connecting the first terminal and the second terminal, and two first power supply lines among the plurality of first power supply lines and a cell to which power is supplied, wherein the plurality of second power supply lines includes a plurality of first wiring patterns extending in the first direction and a plurality of second wiring patterns extending in the second direction. in an orthographic projection with respect to the main surface, the signal line extends from the first terminal to the second terminal within the region of the plurality of first wiring patterns and within the region of the plurality of second wiring patterns and a signal line other than the signal line is not disposed between the signal line and the plurality of second power supply lines.

According to the present invention, it is possible to provide an advantageous technique for suppressing crosstalk noise.

FIG. 2 is a plan view showing a configuration example of the semiconductor device of this embodiment; FIG. 2 is a cross-sectional view showing a configuration example of the semiconductor device in FIG. 1; FIG. 2 is a plan view showing a configuration example of a semiconductor device of a comparative example; FIG. 2 is a plan view showing a modification of the semiconductor device in FIG. 1; FIG. 5 is a cross-sectional view showing a configuration example of the semiconductor device of FIG. 4; FIG. 2 is a perspective view showing a configuration example of a photoelectric conversion device using the semiconductor device of FIG. 1; FIG. 7 is a plan view showing a configuration example of the photoelectric conversion device of FIG. 6; FIG. 7 is a diagram showing a configuration example of a photoelectric conversion system in which the photoelectric conversion device of FIG. 6 is incorporated; FIG. 7 is a diagram showing a configuration example of a moving body in which the photoelectric conversion device of FIG. 6 is incorporated;

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In addition, the following embodiments do not limit the invention according to the scope of claims. Although multiple features are described in the embodiments, not all of these multiple features are essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant description is omitted.

A semiconductor device according to an embodiment of the present disclosure will be described with reference to FIGS. 1 to 9. FIG. FIG. 1 is a plan view showing a configuration example of a semiconductor device 100 according to this embodiment. In the configuration shown in FIG. 1, the semiconductor device 100 has the wiring layer closest to the substrate as the first layer, and the wiring layers sequentially arranged from the first layer to the fifth layer in an upward direction away from the substrate. Prepare. Although five wiring layers are shown here, the number of wiring layers is not particularly limited.

The semiconductor device 100 includes a plurality of first power supply lines 121 , a plurality of second power supply lines 122 and 123 , signal lines 111 and 112 and cells 101 and 102 . The plurality of first power supply lines 121 extend in the X direction (horizontal direction in FIG. 1) on the main surface of the substrate and are arranged in a Y direction (vertical direction in FIG. 1) that intersects the X direction at predetermined intervals. It is Here, the X direction and the Y direction may be orthogonal. The plurality of first power supply lines 121 are arranged on the first layer. That is, another wiring layer (wiring pattern) is not arranged between the wiring layer in which the first power supply line is arranged and the main surface of the substrate. The plurality of first power supply lines 121 are arranged in one wiring layer (first layer).

The plurality of second power supply lines 122 and 123 are arranged at positions farther from the main surface of the substrate than the plurality of first power supply lines 121 . In the configuration shown in FIG. 1, the plurality of second power supply lines 122 are arranged on the third layer and the plurality of second power supply lines 123 are arranged on the fourth layer. First power supply line 121 and second power supply lines 122 and 123 include a power line and a ground line, and supply power to elements arranged in semiconductor device 100 .

Cells 101 and 102 include multiple transistors such as inverters and buffers. The cells 101 and 102 can be relatively small-scale circuits arranged between circuit blocks such as control circuits and memories, or between input/output terminals of the semiconductor device 100 and circuit blocks. The cells 101 and 102 are powered by two first power supply lines 121 out of the plurality of first power supply lines 121 .

Of the signal lines 111 and 112, the signal line 111 is a signal line that requires shielding. The signal line 111 extends in the X direction and the Y direction between two terminals (one terminal 131 is illustrated in FIG. 1) to electrically connect the two terminals. In the configuration shown in FIG. 1, the signal line 111 is arranged in the same wiring layer in both the portion extending in the X direction and the portion extending in the Y direction, but may be arranged over a plurality of wiring layers. In the configuration shown in FIG. 1, the signal line 111 is arranged in the second layer, but it may be arranged in a wiring layer above the third layer. As shown in FIG. 1, the terminal of signal line 111 may be connected to cell 101 . Also, the terminal of the signal line 111 may be connected to the circuit block described above. Further, in the configuration shown in FIG. 1, the signal line 111 is arranged between the first power supply line 121 and the second power supply lines 122 and 123 .

Of the signal lines 111 and 112, the signal line 112 is a signal line that does not require a shield. The signal line 112 extends in the X and Y directions between two terminals (one terminal 132 is shown in FIG. 1) to electrically connect the two terminals. In the configuration shown in FIG. 1, the signal line 112 is formed using a plurality of wiring layers, but the number of wiring layers to be used is not limited. A portion of the signal line 112 whose wiring layer changes is electrically connected by a via. Also, as shown in FIG. 1, the terminal of the signal line 112 may be connected to the cell 102 . Also, the terminal of the signal line 112 may be connected to the circuit block described above.

The plurality of second power supply lines 122 and 123 are composed of a plurality of second power supply lines 122 (first wiring pattern) extending in the X direction and a plurality of second power supply lines 123 (second wiring pattern) extending in the Y direction. including. The second power supply line 122 is electrically connected to the first power supply line 121 using vias. The second power supply line 122 is connected to the first power supply line 121 and the signal lines 111 and 112 in order to suppress the voltage drop from the power supply pad and supply power to the cells 101 and 102 arranged at arbitrary locations. Wiring width is thicker than In the configuration shown in FIG. 1, the second power supply line 122 shows an example arranged using the third layer.

The plurality of second power supply lines 122 (first wiring pattern) may be arranged in the Y direction at a predetermined cycle by making a pair of power supply lines and ground lines. In FIG. 1, a pair of second power supply lines 122 are shown. However, without being limited to this, the second power supply line 122 may be provided as appropriate.

The second power supply line 123 is electrically connected to the first power supply line 121 using vias. Also, the second power supply line 123 may be electrically connected to the second power supply line 122 using vias. The second power supply line 123 is connected to the first power supply line 121 and the signal lines 111 and 112 in order to suppress the voltage drop from the power supply pad and supply power to the cells 101 and 102 arranged at arbitrary locations. Wiring width is thicker than In the configuration shown in FIG. 1, the second power supply line 123 shows an example arranged using the fourth layer. That is, in the present embodiment, the plurality of second power supply lines 122 (first wiring pattern) and the plurality of second power supply lines 123 (second wiring pattern) are formed in different wiring layers.

The plurality of second power supply lines 123 (second wiring pattern) may be arranged in the X direction at predetermined intervals by making a pair of power supply lines and ground lines. In FIG. 1, two pairs of second power supply lines 122 are shown. However, without being limited to this, the second power supply line 123 may be provided as appropriate.

In the configuration shown in FIG. 1 , shield lines 124 and 125 are arranged adjacent to the signal line 111 in the same wiring layer as the signal line 111 . The shield lines 124 and 125 have the role of shielding the signal line 111 along the main surface of the substrate. Therefore, the shield lines 124 and 125 should be on the same wiring layer as the signal line 111 . Further, as shown in FIG. 1, when the wiring direction of the signal line 111 changes between the X direction and the Y direction, the shield lines 124 and 125 also need to change the wiring direction along the signal line 111. be. The shield lines 124 and 125 are connected to power supply lines such as the first power supply line 121 and the second power supply lines 122 and 123 or ground lines so that the shield lines 124 and 125 are maintained at a predetermined potential. good too.

When the shield lines 124 and 125 are arranged directly above the first power supply line 121 and below the second power supply lines 122 and 123, the first power supply line 121 and the second power supply lines 122 and 123 The electrical connection by vias may be made by avoiding the shield lines 124 and 125 . In addition, when wiring short-circuit does not occur, the electrical connection of the first power supply line 121 and the second power supply lines 122 and 123 by vias may pass through the shield lines 124 and 125 .

As shown in FIG. 1, in orthogonal projection onto the main surface of the substrate, the signal line 111 extends from one terminal (e.g., terminal 131) to the other terminal (not shown) through a plurality of second power supply lines. 122 (first wiring pattern) and the plurality of second power supply lines 123 (second wiring pattern), and the signal line 111 and the plurality of second power supply lines 122; 123, there is no signal line other than the signal line 111 (for example, the signal line 112). Thereby, the signal line 111 is also shielded in the direction perpendicular to the main surface of the substrate, and the influence of crosstalk noise can be suppressed.

Further, as shown in FIG. 1, shield lines 124 and 125 for shielding the signal line 111 in the direction along the main surface of the substrate in orthogonal projection to the main surface are connected to the second power supply line 122 (second power supply line 122). 1 wiring pattern) and the second power supply line 123 (second wiring pattern). As a result, the effect of shielding the signal line 111 is further increased, and the influence of crosstalk noise can be suppressed.

As shown in FIG. 1, internal wiring (not shown) of the cells 101 and 102 and a first power supply line 121 are arranged as the wiring pattern of the first layer. Also, the signal line 111 does not pass over the cells 101 and 102 . That is, a signal line different from the signal line (for example, the signal line 112) is arranged between the main surface of the substrate and the signal line 111 and so as to overlap the signal line 111 in orthogonal projection with respect to the main surface of the substrate. do not have. Therefore, there are few noise sources from the direction of the main surface of the substrate with respect to the signal line 111 . Therefore, the side of the signal line 111 closer to the main surface of the substrate may not have a pattern for shielding.

In the configuration shown in FIG. 1, the signal line 111 is arranged on the second layer, the second power supply line 122 is arranged on the third layer, and the second power supply line 123 is arranged on the fourth layer. , 123, there is no need to limit the wiring layer in which the signal line 111 and the second power supply lines 122 and 123 are arranged. Moreover, if there is no other signal line between the signal line 111 and the second power supply lines 122 and 123, it is not necessary to limit the wiring layer in which the signal line 111 and the second power supply lines 122 and 123 are arranged. .

When the wiring layer in which the signal line 111 is arranged and the wiring layer in which the second power supply lines 122 and 123 are arranged are separated by two or more layers, there is a gap between the signal line 111 and the second power supply lines 122 and 123. It is necessary to separately provide a wiring prohibited area or a shield pattern. That is, a wiring layer in which the second power supply lines 122 and 123 are not arranged is arranged between the wiring layer in which the signal line 111 is arranged and the wiring layer in which the second power supply lines 122 and 123 are arranged. In this case, the signal line 111 overlaps between the wiring layer in which the signal line 111 is arranged and the wiring layer in which the second power supply lines 122 and 123 are arranged in the orthogonal projection onto the main surface of the substrate. The region may include a region where no conductive pattern is arranged as a wiring prohibited region. By setting a wiring prohibited area and not arranging a wiring pattern (for example, the signal line 112) that becomes a noise source, it is possible to suppress the influence of crosstalk noise received from the signal line in the direction intersecting the main surface of the substrate. .

Further, for example, a wiring layer in which the second power supply lines 122 and 123 are not arranged between the wiring layer in which the signal line 111 is arranged and the wiring layer in which the second power supply lines 122 and 123 are arranged are arranged, in the orthogonal projection with respect to the main surface of the substrate, the signal line The region overlapping with may include a region in which a conductive pattern that is kept at a predetermined potential or in a floating state is arranged. The conductive pattern that does not function as a signal line can suppress the influence of crosstalk noise received from the signal line in the direction intersecting the main surface of the substrate.

The signal line 112 is a signal line that does not require a shield as described above. Therefore, as shown in FIG. 1, the signal line 112 may include portions that do not overlap the plurality of second power supply lines 122 and 123 in orthogonal projection onto the main surface of the substrate.

2(a) is a sectional view taken along line AA' in FIG. 1, and FIG. 2(b) is a sectional view taken along line BB' in FIG. 1, respectively. A substrate 200 and a wiring layer 201 are illustrated in FIGS. 2(a) and 2(b).

In the cross-sectional view shown in FIG. 2A, it can be seen that the signal line 111 is shielded from the signal line 112 by arranging the shield lines 124 and 125 on the left and right sides of the signal line 111 . The second power supply line 123 also shields the upward direction away from the main surface of the substrate 200 of the signal line 111 . Since no signal line is arranged below the signal line 111 near the main surface of the substrate 200, no shield pattern is arranged. However, a shield pattern (conductive pattern) for shielding the signal line 111 may be provided between the signal line 111 and the main surface of the substrate 200 .

Further, as shown in FIGS. 1 and 2(a), the signal line 111 is arranged on the second layer and the second power supply line 123 is arranged on the fourth layer, so that the signal line 111 and the second power supply line 123 Between them, it is necessary to provide a wiring prohibition area or a shield pattern on the third layer. In the configuration shown in FIGS. 1 and 2A, a wiring prohibited area is provided between the signal line 111 and the second power supply line 123 .

In the cross-sectional view shown in FIG. 2B, the signal line 111 is shielded from the main surface of the substrate 200 by arranging the second power supply lines 122 and 123 directly above the signal line 111 . there is Further, since the first power supply line 121 is arranged directly under the signal line 111 and no other signal line is arranged, there is no noise source. Therefore, no shield pattern is provided between the signal line 111 and the main surface of the substrate 200 .

By providing the semiconductor device 100 with such a structure, even when the signal line 111 extending in both the X direction and the Y direction is arranged, the signal line 111 can be can be shielded. In other words, by arranging the signal line 111 that needs to be shielded in accordance with the arrangement of the second power supply lines 122 and 123 that supply power to the cells 101 and 102 and circuit blocks, the signal line 111 can be efficiently shielded. can be shielded. In other words, the influence of crosstalk noise on the signal line 111 can be suppressed without complicating the design such as by adding a new shield pattern.

FIG. 3 shows a comparative semiconductor device 300 in which the signal line 111 does not overlap the second power supply lines 122 and 123 in orthogonal projection onto the main surface of the substrate. The arrangement of the second power supply lines 122 and 123 and the arrangement of the signal line 112 that does not require shielding are the same as in FIG. The signal line 111 and shield lines 124 and 125 are arranged on the second layer as in FIG.

Compared to the configuration shown in FIG. 1, the second power supply lines 122 and 123 are not arranged directly above the signal line 111 that requires shielding, so it is necessary to separately arrange a shield pattern 321. . Furthermore, the shield pattern 321 needs to use different wiring layers at the locations where it crosses the second power supply lines 122 and 123 in order to prevent short circuits with the second power supply lines 122 and 123 .

As a result, as is clear from a comparison between FIGS. 1 and 3, the semiconductor device 300 consumes more wiring resources than the semiconductor device 100. FIG. Further, it can be seen that the semiconductor device 100 of the present embodiment shown in FIG. 1 uses the second power supply lines 122 and 123 as shield patterns, thereby suppressing consumption of wiring resources. That is, the semiconductor device 100 of this embodiment can efficiently suppress crosstalk noise.

FIG. 4 is a plan view showing a configuration example of a semiconductor device 100' which is a modification of the semiconductor device 100 shown in FIG. In the semiconductor device 100 described above, the second power supply line 122 and the second power supply line 123 are arranged in different wiring layers. On the other hand, in the semiconductor device 100' shown in FIG. pattern) are arranged in one wiring layer. Other than this, it may be the same as the above-described semiconductor device 100, so the description will focus on the points of difference, and the description of the similar parts will be omitted as appropriate.

The second power supply line 122 is arranged to extend in the X direction using the third layer. Also, the second power supply line 123 is arranged to extend in the Y direction using the third layer. The second power supply line 122 is not arranged in the third layer but formed in another wiring layer in order to prevent wiring short-circuit at the intersection of the second power supply line 122 and the second power supply line 123. This is done by connecting to the power supply line 422 .

The power supply line 422 is electrically connected to the second power supply line 122 using vias. In the configuration shown in FIG. 4, power supply lines 422 are arranged in the X direction using the fourth layer. However, it is not limited to this, and other wiring layers may be used. In addition, in the configuration shown in FIG. 4 , the second power supply line 122 is connected to the power supply line 422 arranged in another layer at the intersection with the second power supply line 123 . The supply line 123 may be connected to a power supply line arranged on another layer. The second power supply line 122 or the second power supply line 123 may be connected to a power supply line arranged in another layer according to other wiring pattern configurations.
In the configuration shown in FIG. 4 also, in orthogonal projection onto the main surface of the substrate, the signal line 111 extends from one terminal (e.g., terminal 131) to the other terminal (not shown) through a plurality of second power supply terminals. The signal line 111 and the plurality of second power supply lines 122 are arranged so as to fit within the area of the line 122 (first wiring pattern) and within the area of the plurality of second power supply lines 123 (second wiring pattern). , 123, there is no signal line other than the signal line 111 (for example, the signal line 112). Thereby, the signal line 111 is also shielded in the direction perpendicular to the main surface of the substrate, and the influence of crosstalk noise can be suppressed.

Further, as shown in FIG. 4, shield lines 124 and 125 for shielding the signal line 111 in the direction along the main surface of the substrate in orthogonal projection with respect to the main surface are connected to the second power supply line 122 (second power supply line 122). 1 wiring pattern) and the second power supply line 123 (second wiring pattern). As a result, the effect of shielding the signal line 111 is further increased, and the influence of crosstalk noise can be suppressed.

As shown in FIG. 4, internal wiring (not shown) of the cells 101 and 102 and the first power supply line 121 are arranged as the wiring pattern of the first layer. Also, the signal line 111 does not pass over the cells 101 and 102 . That is, a signal line different from the signal line (for example, the signal line 112) is arranged between the main surface of the substrate and the signal line 111 and so as to overlap the signal line 111 in orthogonal projection with respect to the main surface of the substrate. do not have. Therefore, there are few noise sources from the direction of the main surface of the substrate with respect to the signal line 111 . Therefore, the side of the signal line 111 closer to the main surface of the substrate may not have a pattern for shielding.

In the configuration shown in FIG. 4, the signal line 111 is arranged on the second layer, the second power supply lines 122 and 123 are arranged on the third layer, and the power supply line 422 is arranged on the fourth layer. , 123 and the power supply line 422, the wiring layer in which the signal line 111 and the second power supply lines 122 and 123 are arranged need not be limited. Also, if there is no other signal line between the signal line 111 and the second power supply lines 122, 123 and the power supply line 422, the signal line 111, the second power supply lines 122 and 123 and the power supply line 422 are routed. It is not necessary to limit the wiring layer to be used.

When the wiring layer in which the signal line 111 is arranged and the wiring layer in which the second power supply lines 122 and 123 and the power supply line 422 are arranged are separated by two or more layers, the signal line 111 and the second power It is necessary to separately provide a wiring prohibited area or a shield pattern between the supply lines 122 and 123 . By not arranging a wiring pattern that becomes a noise source in the wiring prohibited area, it is possible to suppress the influence of crosstalk noise received from the signal lines in the direction intersecting the main surface of the substrate. In addition, the conductive pattern (shield pattern) that does not function as a signal line can suppress the influence of crosstalk noise received from the signal line in the direction intersecting the main surface of the substrate.

5(a) is a sectional view taken along line AA' in FIG. 4, and FIG. 5(b) is a sectional view taken along line BB' in FIG. 4, respectively. A substrate 200 and a wiring layer 201 are illustrated in FIGS. 5(a) and 5(b).

5A, it can be seen that the signal line 111 is shielded from the signal line 112 by arranging the shield lines 124 and 125 on the left and right sides of the signal line 111. As shown in FIG. The second power supply line 123 also shields the upward direction away from the main surface of the substrate 200 of the signal line 111 . Since no signal line is arranged below the signal line 111 near the main surface of the substrate 200, no shield pattern is arranged. However, a shield pattern (conductive pattern) for shielding the signal line 111 may be provided between the signal line 111 and the main surface of the substrate 200 .

Comparing the cross-sectional view of the semiconductor device 100 of FIG. 2A with the cross-sectional view of the semiconductor device 100' of FIG. A power supply line 123) is placed on the third layer instead of the fourth layer. Therefore, it is not necessary to provide a wiring prohibited area or a shield wiring between the signal line 111 and the shield pattern (the second power supply line 123) arranged on the second layer. That is, there is a possibility that the semiconductor device 100' can be designed more easily.

In the cross-sectional view shown in FIG. 5B, the signal line 111 is shielded from the main surface of the substrate 200 by arranging the second power supply line 123 directly above the signal line 111 . Further, since the first power supply line 121 is arranged directly under the signal line 111 and no other signal line is arranged, there is no noise source. Therefore, no shield pattern is provided between the signal line 111 and the main surface of the substrate 200 .

Comparing the cross-sectional view of the semiconductor device 100 in FIG. 2B with the cross-sectional view of the semiconductor device 100' in FIG. There is no need to provide a wiring prohibition area or shield wiring. That is, there is a possibility that the semiconductor device 100' can be designed more easily.

A photoelectric conversion device will be described as an application example of the semiconductor devices 100 and 100' of the present embodiment. FIG. 6 is a perspective view showing a configuration example of a photoelectric conversion device 600 including the semiconductor devices 100 and 100′ described above and a pixel array 603 having a plurality of photoelectric conversion elements 604. As shown in FIG.

A photoelectric conversion device 600 includes a substrate 601 and a substrate 602, and the substrate 601 and the substrate 602 are stacked. A pixel array 603 is arranged on the substrate 601 . Photoelectric conversion elements 604 (also called pixels) are regularly arranged in a two-dimensional array in the pixel array 603 .

The substrate 602 is the substrate of the semiconductor device 100, 100' described above. In the configuration shown in FIG. 6, the semiconductor devices 100, 100' are formed on one substrate 602, but may be formed on a plurality of substrates. In this case, three or more substrates may be laminated.

The semiconductor devices 100 and 100' have a configuration for operating the pixel array 603. FIG. The semiconductor device 100, 100' includes, for example, pad modules 605, 606. FIG. The semiconductor device 100, 100' also includes a plurality of analog or digital circuit blocks 607-624 as the circuit blocks described above.

The pad modules 605 and 606 may be circuits having one or more IO pads for transmitting and receiving signals to and from devices external to the photoelectric conversion device 600 . Examples of analog circuits forming the circuit blocks 607 to 624 include ADC (Analog-to-Digital Converter) circuits, column memory circuits, horizontal scanning circuits, vertical scanning circuits, and the like. Furthermore, examples of the digital circuits forming the circuit blocks 607 to 624 include a digital signal processing circuit, an analog circuit control circuit, and the like. The cells 101 and 102 described above can be arranged between these pad modules 605 and 606 and the circuit blocks 607-624 and between the circuit blocks 607-624.

FIG. 7 is an enlarged plan view of a portion 650 surrounded by dotted lines in FIG. In the configuration shown in FIG. 7, signal line 111 connects between pad module 605 and circuit blocks 609 , 618 , 619 . However, the present invention is not limited to this, and the signal line 111 may connect between other circuit blocks. 7, illustration of the cells 101 and 102 as shown in FIGS. 1 and 4 is omitted.

As shown in FIG. 7, in the orthogonal projection with respect to the main surface, the signal line 111 extends from the terminal 131a to the terminal 131b within the region of the plurality of second power supply lines 122 (first wiring pattern) and the plurality of first wiring patterns. 2 The power supply line 123 (second wiring pattern) is arranged so as to fit within the area, and between the signal line 111 and the plurality of second power supply lines 122 and 123, a signal different from the signal line 111 is provided. line is not laid. This makes it possible to suppress the influence of crosstalk noise as described above.

In the configuration shown in FIG. 7, the second power supply line 122 and the second power supply line 123 are arranged using the third layer, similarly to the configuration shown in FIG. The second power supply line 122 is arranged to extend in the X direction using the third layer. Also, the second power supply line 123 is arranged to extend in the Y direction using the third layer. At the intersection of the second power supply line 122 and the second power supply line 123, the second power supply line 122 is not arranged on the third layer, but the power supply line is formed on the fourth layer in order to prevent a wiring short circuit. This is done by connecting to line 422 .

By using the semiconductor devices 100 and 100' of the present embodiment described above, in a semiconductor integrated circuit such as the photoelectric conversion device 600 in which analog circuits and digital circuits coexist, the signal lines 111 extending in the X direction and the Y direction can be used. can be shielded. As a result, it is possible to suppress the influence of crosstalk noise on signal lines in a device including a semiconductor integrated circuit, such as the photoelectric conversion device 600 . As a result, it becomes possible to obtain a highly reliable device.

Here, an application example of the photoelectric conversion device 600 including the semiconductor devices 100 and 100' of this embodiment will be described. FIG. 8 is a block diagram showing a schematic configuration of a photoelectric conversion system 800 incorporating a photoelectric conversion device 600 including the semiconductor devices 100 and 100'.

The photoelectric conversion device 600 including the semiconductor devices 100 and 100' of the present embodiment described above can be applied to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, copiers, facsimiles, mobile phones, vehicle-mounted cameras, and observation satellites. A camera module including an optical system such as a lens and a photoelectric conversion device is also included in the photoelectric conversion system. FIG. 8 illustrates a block diagram of a digital still camera as an example of these.

A photoelectric conversion system 800 exemplified in FIG. and a barrier 801 for protecting the lens 802 . A lens 802 and a diaphragm 803 are an optical system that condenses light onto the photoelectric conversion device 600 . The photoelectric conversion device 600 converts the optical image formed by the lens 802 into an electrical signal.

The photoelectric conversion system 800 also includes a signal processing unit 807 that is an image generation unit that processes an output signal output from the photoelectric conversion device 600 to generate an image. A signal processing unit 807 performs various corrections and compressions as necessary and outputs image data. The signal processing unit 807 may be formed on the semiconductor substrate (for example, the substrate 602 ) on which the photoelectric conversion device 600 is provided, or may be formed on a semiconductor substrate different from the photoelectric conversion device 600 . Further, the photoelectric conversion device 600 and the signal processing section 807 may be formed on the same semiconductor substrate.

The photoelectric conversion system 800 further includes a memory unit 810 for temporarily storing image data, and an external interface unit (external I/F unit) 813 for communicating with an external computer or the like. Further, the photoelectric conversion system 800 includes a recording medium 812 such as a semiconductor memory for recording or reading image data, and a recording medium control interface section (recording medium control I/F section) for recording or reading the recording medium 812. 811. Note that the recording medium 812 may be built in the photoelectric conversion system 800 or may be detachable.

Further, the photoelectric conversion system 800 has an overall control/calculation unit 809 that controls various calculations and the entire digital still camera, and a timing generation unit 808 that outputs various timing signals to the photoelectric conversion device 600 and the signal processing unit 807 . Here, the timing signal and the like may be input from the outside, and the photoelectric conversion system 800 only needs to have at least the photoelectric conversion device 600 and the signal processing unit 807 that processes the output signal output from the photoelectric conversion device 600. .

The photoelectric conversion device 600 outputs the imaging signal to the signal processing section 807 . A signal processing unit 807 performs predetermined signal processing on the imaging signal output from the photoelectric conversion device 600 and outputs image data. A signal processing unit 807 generates an image using the imaging signal.

As described above, according to the present embodiment, a photoelectric conversion system to which the photoelectric conversion device 600 (for example, an imaging device) described above is applied can be realized.

Next, a photoelectric conversion system incorporating a photoelectric conversion device 600 including the semiconductor devices 100 and 100' of the present embodiment and a moving body will be described with reference to FIGS. 9(a) and 9(b). FIGS. 9A and 9B show a photoelectric conversion system 900 incorporating a photoelectric conversion device 600 including the semiconductor devices 100 and 100′ of the present embodiment, and a mobile body equipped with the photoelectric conversion system 900. 9 is a diagram showing the configuration of a device 901; FIG.

FIG. 9(a) shows an example of a photoelectric conversion system 900 for an onboard camera. The photoelectric conversion system 900 includes an image processing unit 912 that performs signal processing such as image processing on a plurality of image data acquired by the photoelectric conversion device 600 that includes the semiconductor devices 100 and 100′ of this embodiment, and an image processing unit. It has a parallax acquisition unit 914 that calculates parallax (phase difference of parallax images) from a plurality of image data subjected to signal processing by 912 . The photoelectric conversion system 900 also includes a distance acquisition unit 916 that calculates the distance to the object based on the calculated parallax, and a collision determination unit that determines whether there is a possibility of collision based on the calculated distance. 918 and . Here, the parallax acquisition unit 914 and the distance acquisition unit 916 are examples of distance information acquisition means for acquiring distance information to the object. That is, the distance information is information related to parallax, defocus amount, distance to the object, and the like. The collision determination unit 918 may use any of these distance information to determine the possibility of collision. The distance information acquisition means may be implemented by specially designed hardware, or may be implemented by a software module. Moreover, it may be implemented by FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or the like, or by a combination thereof.

The photoelectric conversion system 900 is connected to a vehicle information acquisition device 920 of a transportation device 901 (for example, a vehicle) equipped with a driving device, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 900 is also connected to a control ECU 930 that is a control device that outputs a control signal for generating a braking force to the vehicle based on the determination result of the collision determination section 918 . The photoelectric conversion system 900 is also connected to an alarm device 940 that issues an alarm to the driver based on the determination result of the collision determination section 918 . For example, if the collision determination unit 918 determines that there is a high possibility of a collision, the control ECU 930 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, or suppressing the engine output. The alarm device 940 warns the user by sounding an alarm such as sound, displaying alarm information on a screen of a car navigation system or the like, or vibrating a seat belt or a steering wheel.

In this embodiment, the photoelectric conversion system 900 captures an image of the surroundings of the transportation equipment 901, for example, the front or rear. FIG. 9(b) shows a photoelectric conversion system 900 for capturing an image in front of a transportation device 901 (imaging range 950). Vehicle information acquisition device 920 sends an instruction to photoelectric conversion system 900 or photoelectric conversion device 600 . With such a configuration, the accuracy of distance measurement can be further improved.

In the above, an example of controlling the driving device 960 such as the brake, accelerator, and engine of the transportation equipment 901 based on the information obtained by the photoelectric conversion device 600 so as not to collide with another vehicle has been described. However, the present invention is not limited to this, and can be applied to control for automatically driving following another vehicle, control for automatically driving so as not to stray from the lane, and the like. Further, although an example in which the photoelectric conversion system 900 incorporating the photoelectric conversion device 600 is incorporated in the transportation equipment 901 has been shown, the photoelectric conversion device 600 is incorporated in the vehicle information acquisition device 920, the control ECU 930, and the alarm device 940. may Furthermore, the photoelectric conversion system 900 in which the photoelectric conversion device 600 is incorporated is not limited to vehicles such as automobiles, and can be applied to transportation equipment equipped with a driving device such as ships, aircraft, railway vehicles, and industrial robots. can. In addition, the present invention can be applied not only to mobile objects but also to devices that widely use object recognition, such as intelligent transportation systems (ITS).

The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the claims are appended to make public the scope of the invention.

100: semiconductor device, 111: signal line, 121: first power supply line, 122, 123: second power supply line, 131: terminal

Claims (20)

a plurality of first power supply lines extending in a first direction and arranged at predetermined intervals in a second direction intersecting the first direction on the main surface of the substrate;
a plurality of second power supply lines arranged at positions further from the main surface than the plurality of first power supply lines;
a signal line extending in the first direction and the second direction between the first terminal and the second terminal and electrically connecting the first terminal and the second terminal;
a cell to which power is supplied from two first power supply lines among the plurality of first power supply lines,
the plurality of second power supply lines includes a plurality of first wiring patterns extending in the first direction and a plurality of second wiring patterns extending in the second direction;
In the orthogonal projection onto the main surface, the signal line is arranged so as to fit within the region of the plurality of first wiring patterns and within the region of the plurality of second wiring patterns from the first terminal to the second terminal. and a signal line other than the signal line is not disposed between the signal line and the plurality of second power supply lines. the plurality of first wiring patterns are arranged in the second direction with a predetermined period in pairs of power supply lines and ground lines;
2. The semiconductor device according to claim 1, wherein said plurality of second wiring patterns are arranged in said first direction at predetermined intervals in pairs of power supply lines and ground lines. 3. The semiconductor device according to claim 1, wherein a width of each of said plurality of second power supply lines is thicker than a width of each of said plurality of first signal lines. 4. The semiconductor device according to claim 1, wherein the plurality of first wiring patterns and the plurality of second wiring patterns are formed in wiring layers different from each other. 1 to 3, wherein the plurality of second power supply lines are arranged in one wiring layer except for intersections between the plurality of first wiring patterns and the plurality of second wiring patterns. 4. The semiconductor device according to any one of 3. 6. The semiconductor device according to claim 1, wherein said signal line is arranged in one wiring layer. 6. The semiconductor device according to claim 1, wherein said signal line is arranged over a plurality of wiring layers. 8. The semiconductor device according to claim 1, wherein a shield line is arranged in the same wiring layer as the signal line so as to be adjacent to the signal line. 9. The semiconductor device according to claim 8, wherein said shield line is arranged so as to overlap said first wiring pattern and said second wiring pattern in orthogonal projection onto said main surface. 10. The semiconductor device according to claim 8, wherein said shield line is kept at a predetermined potential. 11. The semiconductor device according to claim 1, wherein the signal line is arranged between the plurality of first power supply lines and the plurality of second power supply lines. . 12. The method according to claim 11, wherein no signal line different from the signal line is arranged between the main surface and the signal line and so as to overlap the signal line in the orthogonal projection with respect to the main surface. The semiconductor device described. 13. The semiconductor device according to claim 1, wherein said plurality of first power supply lines are arranged in one wiring layer. 14. The semiconductor device according to claim 13, wherein no other wiring layer is arranged between the wiring layer in which the plurality of first power supply lines are arranged and the main surface. A third wiring layer in which the plurality of second power supply lines are not arranged between a first wiring layer in which the signal lines are arranged and a second wiring layer in which the plurality of second power supply lines are arranged A wiring layer is arranged,
15. The method according to any one of claims 1 to 14, wherein a region of the third wiring layer that overlaps with the signal line in an orthogonal projection onto the main surface includes a region in which no conductive pattern is arranged. semiconductor equipment. A third wiring layer in which the plurality of second power supply lines are not arranged between a first wiring layer in which the signal lines are arranged and a second wiring layer in which the plurality of second power supply lines are arranged A wiring layer is arranged,
In an orthographic projection with respect to the main surface, a region of the third wiring layer that overlaps with the signal line includes a region in which a conductive pattern is arranged,
16. The semiconductor device according to claim 1, wherein said conductive pattern is kept at a predetermined potential or is in a floating state. Using the signal line as a first signal line, a second signal line is further arranged,
17. The semiconductor device according to claim 1, wherein said second signal line includes a portion that does not overlap with said plurality of second power supply lines when orthogonally projected onto said main surface. A semiconductor device according to any one of claims 1 to 17;
A photoelectric conversion device including a pixel array comprising a plurality of photoelectric conversion elements,
The substrate is used as a first substrate, and a second substrate is provided,
The pixel array is arranged on the second substrate,
The semiconductor device has a configuration for operating the pixel array,
A photoelectric conversion device, wherein the first substrate and the second substrate are laminated. a photoelectric conversion device according to claim 18;
a signal processing unit that processes a signal output from the photoelectric conversion device;
A photoelectric conversion system comprising: A moving body comprising a driving device, comprising the photoelectric conversion device according to claim 18, and a control device for controlling the driving device based on information obtained by the photoelectric conversion device. mobile body.

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