JP4353369B2 - SiC semiconductor and manufacturing method thereof - Google Patents
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Description
本発明は、Ｓｉ（シリコン、ケイ素）単結晶基板上にβ−ＳｉＣ（立方晶炭化ケイ素）単結晶薄膜を形成してなり、次世代電子素子、高速高温動作可能電子素子、太陽光発電素子等としての応用が期待されているＳｉＣ半導体及びその製造方法に関する。 The present invention comprises a β-SiC (cubic silicon carbide) single crystal thin film formed on a Si (silicon, silicon) single crystal substrate, a next-generation electronic device, an electronic device capable of high-speed and high-temperature operation, a photovoltaic power generation device, etc. The present invention relates to a SiC semiconductor that is expected to be applied as a semiconductor device and a manufacturing method thereof.
ＳｉＣ（炭化ケイ素）は、広いバンドギャップ、高い電子移動度、及び高い耐熱性を有し、構成元素の資源量が豊富でかつ環境汚染への懸念が小さい等の特徴を持つ化合物半導体である。 SiC (silicon carbide) is a compound semiconductor having characteristics such as a wide band gap, high electron mobility, high heat resistance, abundant amounts of constituent elements, and low concern about environmental pollution.
従来、ＳｉＣ半導体及びその製造方法としては、電子素子の基板（Ｓｉ単結晶基板）上にＣＶＤ（Chemical Vapor Deposition ：化学的気相成長）法によりβ−ＳｉＣ単結晶薄膜を１２００℃以下の温度領域で２段の成長温度に分けて成長させてなるものが知られている（特許文献１参照）。
このＳｉＣ半導体によれば、結晶性に優れた高品質のものが得られる、というものである。
Conventionally, as a SiC semiconductor and a manufacturing method thereof, a β-SiC single crystal thin film is formed on a substrate of an electronic element (Si single crystal substrate) by a CVD (Chemical Vapor Deposition) method at a temperature range of 1200 ° C. or lower. In this case, it is known that the growth is performed by dividing the growth temperature into two stages (see Patent Document 1).
According to this SiC semiconductor, a high-quality one having excellent crystallinity can be obtained.
しかし、従来のＳｉＣ半導体及びその製造方法では、Ｓｉ単結晶基板表面の凹凸が欠陥要因となり、β−ＳｉＣ単結晶薄膜の結晶品質が低下する不具合がある。
又、ＳｉＣ／Ｓｉ界面へ空隙を残したり、多数の欠陥を発生させることにより、ＳｉＣ ｏｎ Ｓｉデバイスとしての使用を困難にしている。
Ｓｉ単結晶基板の表面に凹凸が生じるのは、１２００℃までのＳｉ単結晶基板の加熱過程において、Ｓｉ単結晶基板の表面がＨ2Ｏ（水蒸気）やＯ2（酸素ガス）等の不純物ガスにより８００℃付近からエッチングされ、エッチピットが生成されることによるものである。
However, the conventional SiC semiconductor and the manufacturing method thereof have a defect that the unevenness of the surface of the Si single crystal substrate becomes a defect factor and the crystal quality of the β-SiC single crystal thin film is deteriorated.
In addition, leaving voids at the SiC / Si interface or generating a large number of defects makes it difficult to use as a SiC on Si device.
Irregularities occur on the surface of the Si single crystal substrate because the surface of the Si single crystal substrate is heated to 1200 ° C., while the surface of the Si single crystal substrate is an impurity gas such as H 2 O (water vapor) or O 2 (oxygen gas). This is because etching is performed from around 800 ° C. to generate etch pits.
上述したＳｉ単結晶基板表面のエッチングの抑制には、β−ＳｉＣ単結晶薄膜の成膜の前にＳｉ単結晶基板表面を炭化して形成したＳｉＣ単結晶層が有効であるが、表面炭化のみで形成される１０ｎｍ程度の極薄の層では、エッチングを完全に防止することができない。
本発明は、β−ＳｉＣ単結晶薄膜を結晶性に優れた高品質なものとし得るＳｉＣ半導体及びその製造方法の提供を課題とする。 An object of the present invention is to provide a SiC semiconductor capable of making a β-SiC single crystal thin film of high quality with excellent crystallinity and a method for producing the same.
本発明のＳｉＣ半導体は、Ｓｉ単結晶基板上にアモルファスを含む厚さ３〜２０ｎｍの第１ＳｉＣ層及び多数のβ−ＳｉＣ成長核からなる厚さ１０〜５０ｎｍの第２ＳｉＣ層を順に介在して厚さ１μｍ以上のβ−ＳｉＣ単結晶薄膜が形成されていることを特徴とする。 The SiC semiconductor of the present invention is formed by sequentially interposing a first SiC layer having a thickness of 3 to 20 nm containing amorphous and a second SiC layer having a thickness of 10 to 50 nm composed of a number of β-SiC growth nuclei on an Si single crystal substrate. A β-SiC single crystal thin film having a thickness of 1 μm or more is formed.
一方、ＳｉＣ半導体の製造方法は、Ｓｉ単結晶基板上にＣＶＤ法により第１ＳｉＣ層を成長温度５００〜７００℃で３〜２０ｎｍの厚さに成長させた後、第１ＳｉＣ層上にＣＶＤ法により第２ＳｉＣ層を成長温度７８０〜９５０℃で１０〜５０ｎｍの厚さに成長させ、しかる後に、第２ＳｉＣ層上にＣＶＤ法によりβ−ＳｉＣ単結晶薄膜を成長温度１１００℃以上で１μｍ以上の厚さに成長させることを特徴とする。 On the other hand, the SiC semiconductor manufacturing method is such that after a first SiC layer is grown on a Si single crystal substrate by a CVD method to a thickness of 3 to 20 nm at a growth temperature of 500 to 700 ° C., the first SiC layer is grown on the first SiC layer by a CVD method. The 2SiC layer is grown to a thickness of 10 to 50 nm at a growth temperature of 780 to 950 ° C., and then a β-SiC single crystal thin film is grown on the second SiC layer by a CVD method to a thickness of 1 μm or more at a growth temperature of 1100 ° C. or more. It is characterized by growing.
本発明のＳｉＣ半導体及びその製造方法によれば、不純物ガスによるＳｉ単結晶基板表面のエッチング開始温度以下で成長させられてアモルファスを含む第１ＳｉＣ層が、エッチング開始温度付近でのＳｉ単結晶基板表面のエッチングを防止するエッチング防止層として機能すると共に、その結晶配列の乱れがＳｉとβ−ＳｉＣとの格子不整合を緩和するバッファ層として機能する一方、不純物ガスによるＳｉ単結晶基板表面のエッチング開始温度又はそれよりも高い温度で成長させられて多数のβ−ＳｉＣ成長核からなる第２ＳｉＣ層が、１１００℃以上の高温域までＳｉ単結晶基板のエッチングを防止するエッチング防止層として機能すると共に、β−ＳｉＣ成長核がβ−ＳｉＣ単結晶薄膜の成長を良好とし、かつ、二次元成長化を促進するので、β−ＳｉＣ単結晶薄膜を結晶性に優れた極めて高品質なものとすることができ、しかも表面性に優れたものとすることができる。 According to the SiC semiconductor and the manufacturing method thereof of the present invention, the first SiC layer grown at a temperature lower than or equal to the etching start temperature of the Si single crystal substrate surface by the impurity gas and containing the amorphous is the surface of the Si single crystal substrate near the etching start temperature. In addition to functioning as an anti-etching layer that prevents the etching of silicon, the disorder of the crystal arrangement functions as a buffer layer that alleviates lattice mismatch between Si and β-SiC, while etching of the Si single crystal substrate surface by impurity gas begins. The second SiC layer made of a large number of β-SiC growth nuclei grown at a temperature or higher than the temperature functions as an etching prevention layer for preventing the etching of the Si single crystal substrate to a high temperature region of 1100 ° C. or higher, β-SiC growth nuclei improve the growth of β-SiC single crystal thin films and promote two-dimensional growth Since, beta-SiC single crystal thin film can be excellent and very high quality ones in crystallinity, moreover can be provided with excellent surface properties.
Ｓｉ単結晶基板は、Ｓｉ（１００）又はＳｉ（１１１）が好ましい。 The Si single crystal substrate is preferably Si (100) or Si (111).
第１ＳｉＣ層の厚さが、３ｎｍ未満であると、Ｓｉエッチング開始温度（８００℃）付近でのエッチング防止効果が得られない。一方、２０ｎｍを超えると、エッチング防止効果は向上するが、その後の結晶成長を阻害し結晶性を低下させる要因となる。
第１ＳｉＣ層の厚さは、５〜１５μｍがより好ましい。
When the thickness of the first SiC layer is less than 3 nm, the effect of preventing etching near the Si etching start temperature (800 ° C.) cannot be obtained. On the other hand, if the thickness exceeds 20 nm, the etching prevention effect is improved, but it hinders subsequent crystal growth and causes a decrease in crystallinity.
As for the thickness of a 1st SiC layer, 5-15 micrometers is more preferable.
第２ＳｉＣ層の厚さが、１０ｎｍ未満であると、１１００℃以上の高温まで昇温する際のエッチング防止効果が得られない。一方、５０ｎｍを超えると、結晶性低下の要因となる。
第２ＳｉＣ層の厚さは、１５〜３０ｎｍがより好ましい。
When the thickness of the second SiC layer is less than 10 nm, the effect of preventing etching when the temperature is raised to a high temperature of 1100 ° C. or higher cannot be obtained. On the other hand, when it exceeds 50 nm, it becomes a factor of crystallinity fall.
The thickness of the second SiC layer is more preferably 15 to 30 nm.
β−ＳｉＣ単結晶薄膜の厚さが、１μｍ未満であると、Ｓｉ単結晶基板の影響を受け易く格子不整合による応力や欠陥が多い領域となる。
β−ＳｉＣ単結晶薄膜の厚さは、５μｍ以上がより好ましい。
β−ＳｉＣ単結晶薄膜の厚さは、いくら厚くてもよいが、３００μｍを超えると実用的でない。
When the thickness of the β-SiC single crystal thin film is less than 1 μm, it is easily affected by the Si single crystal substrate and becomes a region having many stresses and defects due to lattice mismatch.
The thickness of the β-SiC single crystal thin film is more preferably 5 μm or more.
The β-SiC single crystal thin film may be as thick as possible, but it is not practical when it exceeds 300 μm.
Ｓｉ単結晶基板は、ケミカルエッチング等により表面を平坦にしたものを用いることが好ましい。
又、Ｓｉ単結晶基板には、第１ＳｉＣ層の成長前に、水素アニーリングにより表面クリーニングを施すことが望ましい。
It is preferable to use a Si single crystal substrate whose surface is flattened by chemical etching or the like.
Further, it is desirable to perform surface cleaning of the Si single crystal substrate by hydrogen annealing before the growth of the first SiC layer.
ＣＶＤ法としては、ＭＯＣＶＤ（Metal Organic Chemical Vapor Deposition ：有機金属化学的気相成長）法、その他が挙げられる。 Examples of the CVD method include MOCVD (Metal Organic Chemical Vapor Deposition) method and others.
第１ＳｉＣ層の成長温度が、５００℃未満であると、成長速度が極端に遅くなる又は成長しない。一方、７００℃を超えると、Ｓｉエッチング温度に近づくことからエッチング抑制のための成膜制御困難となる。
第１ＳｉＣ層の成長温度は、６００〜６８０℃がより好ましい。
第１ＳｉＣ層の成長原料としては、ＳｉＨ3ＣＨ3（ＭＭＳ：モノメチルシラン）、その他が用いられる。
If the growth temperature of the first SiC layer is less than 500 ° C., the growth rate becomes extremely slow or does not grow. On the other hand, when the temperature exceeds 700 ° C., film formation control for suppressing etching becomes difficult because the temperature approaches the Si etching temperature.
The growth temperature of the first SiC layer is more preferably 600 to 680 ° C.
As a growth raw material for the first SiC layer, SiH 3 CH 3 (MMS: monomethylsilane) and others are used.
第２ＳｉＣ層の成長温度が、７８０℃未満であると、アモルファス成分が多くなることによりその後の結晶成長における結晶性劣化の原因となる。一方、９５０℃を超えると、第１ＳｉＣ層だけではエッチング防止できない。
第２ＳｉＣ層の成長温度は、８００〜９００℃がより好ましい。
第２ＳｉＣ層の成長原料としては、ＳｉＨ3ＣＨ3、その他が用いられる。
When the growth temperature of the second SiC layer is lower than 780 ° C., the amorphous component increases, which causes crystallinity deterioration in the subsequent crystal growth. On the other hand, if the temperature exceeds 950 ° C., the first SiC layer alone cannot prevent etching.
The growth temperature of the second SiC layer is more preferably 800 to 900 ° C.
SiH 3 CH 3 and others are used as the growth raw material for the second SiC layer.
β−ＳｉＣ単結晶薄膜の成長温度が、１１００℃未満であると、アモルファス成分が残留する。
β−ＳｉＣ単結晶薄膜の成長温度は、成長表面マイグレーション（移動）を考慮しなるべく高温であることが好ましいが、１４００℃を超えると、Ｓｉ単結晶基板が軟化する。
β−ＳｉＣ単結晶薄膜の成長用原料としては、ＳｉＨ4（モノシラン）及びＣ3Ｈ8（プロパン）、その他が用いられる。
If the growth temperature of the β-SiC single crystal thin film is less than 1100 ° C., the amorphous component remains.
The growth temperature of the β-SiC single crystal thin film is preferably as high as possible in consideration of growth surface migration (movement), but when it exceeds 1400 ° C., the Si single crystal substrate is softened.
As a raw material for growing the β-SiC single crystal thin film, SiH 4 (monosilane), C 3 H 8 (propane), and others are used.
図１は、本発明に係るＳｉＣ半導体の実施例１を示す概念的な断面図である。 FIG. 1 is a conceptual cross-sectional view showing a first embodiment of an SiC semiconductor according to the present invention.
このＳｉＣ半導体１は、（１００）Ｓｉ単結晶基板からなる厚さ６３０μｍのＳｉ単結晶基板２上に、アモルファス（非晶質）を含む厚さ５ｎｍの第１ＳｉＣ層３、及び多数のβ−ＳｉＣ成長核からなる厚さ１８ｎｍの第２ＳｉＣ層４を順に介在して厚さ１０μｍのβ−ＳｉＣ単結晶薄膜５が形成されているものである。
The
上述したＳｉＣ半導体１を製造するには、（１００）Ｓｉ基板からなり、表面をケミカルエッチングしたＳｉ単結晶基板２を準備し、先ず、Ｓｉ単結晶基板２を基板ホルダーに載せ、反応管（共に図示せず）内の成長領域にセットする。
In order to manufacture the
次に、ガス導入管からキャリアガスとしてＨ2（水素ガス）を供給しながら、Ｓｉ単結晶基板２を１１００℃に昇温して基板表面のクリーニングを行う。
Next, while supplying H 2 (hydrogen gas) as a carrier gas from the gas introduction tube, the Si
次いで、基板温度を６５０℃まで降温し、安定したところで原料ガスとしてＳｉＨ3ＣＨ3を１５分間供給して（図２（ａ）参照）、第１ＳｉＣ層３（図２（ｂ）参照）を５ｎｍの厚さに成長させる。 Next, the substrate temperature is lowered to 650 ° C., and when stable, SiH 3 CH 3 is supplied as a raw material gas for 15 minutes (see FIG. 2A), and the first SiC layer 3 (see FIG. 2B) is 5 nm. Grow to a thickness of.
次に、基板温度を８３０℃まで昇温し、安定したところで原料ガスとしてＳｉＨ3ＣＨ3を１０分間供給して（図２（ｂ）参照）、第２ＳｉＣ層４（図２（ｃ）参照）を１８ｎｍの厚さに成長させる。
なお、第１、第２ＳｉＣ層３，４の成長は、ガス供給量を、Ｈ2：１２ｓｌｍ、ＳｉＨ3ＣＨ3：２ｓｃｃｍとして２５Ｔｏｒｒの圧力雰囲気下で行った。
Next, the substrate temperature is raised to 830 ° C., and when stable, SiH 3 CH 3 is supplied as a source gas for 10 minutes (see FIG. 2B), and the second SiC layer 4 (see FIG. 2C). Is grown to a thickness of 18 nm.
The first and
最後に、基板温度を１２００℃まで昇温し、原料ガスとしてＳｉＨ4及びＣ3Ｈ8をそれぞれ４．８ｓｃｃｍ供給して（図２（ｃ）参照）、８時間かけてβ−ＳｉＣ単結晶薄膜５（図１参照）を１０μｍの厚さに成長させる。 Finally, the substrate temperature is raised to 1200 ° C., and 4.8 sccm of SiH 4 and C 3 H 8 are supplied as source gases (see FIG. 2C), and the β-SiC single crystal thin film is taken over 8 hours. 5 (see FIG. 1) is grown to a thickness of 10 μm.
得られたＳｉＣ半導体１は、Ｓｉ単結晶基板２とβ−ＳｉＣ単結晶薄膜５の界面にエッチピットが存在せず、表面も非常に平坦であった。
又、低温からＳｉＣ形成したことにより、界面からの不純物の混入も少なく、成長させたβ−ＳｉＣ単結晶薄膜５の結晶性も良好であった。
なお、ＳｉＣ（２００）ピークに対するＦＷＨＭ（Full Width at Half Maximum：半値全幅）は、０．１°であった。
The obtained
Further, since SiC was formed from a low temperature, impurities were not mixed from the interface, and the crystallinity of the grown β-SiC single crystal
The FWHM (Full Width at Half Maximum) for the SiC (200) peak was 0.1 °.
実施例１における第１、第２ＳｉＣ層３，４を形成せずに、その他は実施例１と同様に製造してＳｉＣ半導体を得た。 The first and second SiC layers 3 and 4 in Example 1 were not formed, and the others were manufactured in the same manner as in Example 1 to obtain a SiC semiconductor.
得られたＳｉＣ半導体は、界面に多数のエッチピットが存在し、ＳｉＣ（１００）ピークが存在する多結晶であった。 The obtained SiC semiconductor was polycrystalline with a large number of etch pits at the interface and a SiC (100) peak.
基板表面のクリーニングまでは実施例１と同様とし、その後、基板温度６５０℃まで下げたところでＣ３ Ｈ８ を５０ｓｃｃｍ供給しながら、昇温速度を２００℃／ｍｉｎとして基板温度を１２００℃まで昇温し、この温度を５分間保持して炭化層を形成した後、実施例１と同様の条件によりβ−ＳｉＣ単結晶薄膜を成長させてＳｉＣ半導体を得た。 The substrate surface was cleaned in the same manner as in Example 1, and then the substrate temperature was raised to 1200 ° C. at a rate of temperature rise of 200 ° C./min while supplying 50 sccm of C3 H8 when the substrate temperature was lowered to 650 ° C. After maintaining this temperature for 5 minutes to form a carbonized layer, a β-SiC single crystal thin film was grown under the same conditions as in Example 1 to obtain a SiC semiconductor.
得られたＳｉＣ半導体は、実施例１と同程度のＦＷＨＭとなり、結晶性は良好であったが、界面に数１００個／ｃｍ２ のエッチピットが存在した。
The obtained SiC semiconductor had a FWHM comparable to that of Example 1 and had good crystallinity, but had several hundreds /
基板表面のクリーニングまでは実施例１と同様とし、その後、基板温度を８００℃まで下げ、安定したところで原料ガスとしてＳｉＨ3ＣＨ3を１０分間供給して、中間ＳｉＣ単結晶層を１０ｎｍの厚さに成長させる。
この際の成長は、ガス供給量を、Ｈ2：１２ｓｌｍ、ＳｉＨ3ＣＨ3：２ｓｃｃｍとして２５Ｔｏｒｒの圧力雰囲気下で行った。
The substrate surface is cleaned in the same manner as in Example 1. Thereafter, the substrate temperature is lowered to 800 ° C., and when stable, SiH 3 CH 3 is supplied as a source gas for 10 minutes, and the intermediate SiC single crystal layer has a thickness of 10 nm. To grow.
The growth at this time was performed in a pressure atmosphere of 25 Torr with gas supply amounts of H 2 : 12 slm and SiH 3 CH 3 : 2 sccm.
次に、基板温度を１２００℃まで昇温し、実施例１と同様の条件によりβ−ＳｉＣ単結晶薄膜を成長させてＳｉＣ半導体を得た。 Next, the substrate temperature was raised to 1200 ° C., and a β-SiC single crystal thin film was grown under the same conditions as in Example 1 to obtain a SiC semiconductor.
得られたＳｉＣ半導体は、実施例１と同程度のＦＷＨＭとなり、結晶性は良好であったが、界面に数１０個／ｃｍ2のエッチピットが存在した。
なお、中間ＳｉＣ単結晶層の成長時間を延長してその厚さを１５ｎｍとした場合、ＳｉＣ（２００）ピークに対するＦＷＨＭが０．８°となり結晶性が低下した。逆に成長時間を短縮して厚さを５ｎｍとした場合には、エッチピットが増加した。
The obtained SiC semiconductor had a FWHM similar to that of Example 1 and had good crystallinity, but there were several tens / cm 2 of etch pits at the interface.
When the growth time of the intermediate SiC single crystal layer was extended to a thickness of 15 nm, the FWHM with respect to the SiC (200) peak was 0.8 ° and the crystallinity was lowered. Conversely, when the growth time was shortened to a thickness of 5 nm, etch pits increased.
基板表面のクリーニングまでは実施例１と同様とし、その後、基板温度を２００℃まで降温してから、原料ガスとしてＳｉＨ3ＣＨ3の供給を開始、ガス供給しながら昇温速度２００℃／ｍｉｎで８００℃まで昇温して中間ＳｉＣ単結晶層を２０ｎｍの厚さに成長させる。
この際の成長は、ガス供給量を、Ｈ2：１２ｓｌｍ、ＳｉＨ3ＣＨ3：２ｓｃｃｍとして２５Ｔｏｒｒの圧力雰囲気下で行った。
The substrate surface is cleaned in the same manner as in Example 1. Thereafter, after the substrate temperature is lowered to 200 ° C., supply of SiH 3 CH 3 as a raw material gas is started, and the temperature rise rate is 200 ° C./min while supplying the gas. The temperature is raised to 800 ° C., and an intermediate SiC single crystal layer is grown to a thickness of 20 nm.
The growth at this time was performed in a pressure atmosphere of 25 Torr with gas supply amounts of H 2 : 12 slm and SiH 3 CH 3 : 2 sccm.
次に、基板温度を１２００℃まで昇温し、実施例１と同様の条件でβ−ＳｉＣ単結晶薄膜を成長させてＳｉＣ半導体を得た。 Next, the substrate temperature was raised to 1200 ° C., and a β-SiC single crystal thin film was grown under the same conditions as in Example 1 to obtain a SiC semiconductor.
得られたＳｉＣ半導体は、界面にエッチピットが数１０個／ｃｍ2存在し、ＳｉＣ（２００）ピークに対するＦＷＨＭが０．３°であった。
なお、中間ＳｉＣ単結晶層の厚さを１０ｎｍとした場合、ＦＷＨＭが低下し、結晶性は向上したが、エッチピット数が増加した。
又、昇温速度を８０℃／ｍｉｎと遅くした場合、エッチピット数は減少したが、ＦＷＨＭが１．１°となり、結晶性が低下した。
The obtained SiC semiconductor had several tens of etch pits / cm 2 at the interface, and the FWHM with respect to the SiC (200) peak was 0.3 °.
When the thickness of the intermediate SiC single crystal layer was 10 nm, FWHM decreased and crystallinity improved, but the number of etch pits increased.
Further, when the rate of temperature increase was slowed down to 80 ° C./min, the number of etch pits was reduced, but the FWHM was 1.1 ° and the crystallinity was lowered.
１ ＳｉＣ半導体
２ ＳｉＣ単結晶基板
３ 第１ＳｉＣ層
４ 第２ＳｉＣ層
５ β−ＳｉＣ単結晶薄膜
DESCRIPTION OF
Claims (2)
A first SiC layer is grown on a Si single crystal substrate by a CVD method at a growth temperature of 500 to 700 ° C. to a thickness of 3 to 20 nm, and then a second SiC layer is grown on the first SiC layer by a CVD method at a growth temperature of 780 to 950 ° C. And then growing a β-SiC single crystal thin film on the second SiC layer by a CVD method to a thickness of 1 μm or more at a growth temperature of 1100 ° C. or more. Manufacturing method.
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