JP4351178B2 - 半導体記憶装置 - Google Patents
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- JP4351178B2 JP4351178B2 JP2005050632A JP2005050632A JP4351178B2 JP 4351178 B2 JP4351178 B2 JP 4351178B2 JP 2005050632 A JP2005050632 A JP 2005050632A JP 2005050632 A JP2005050632 A JP 2005050632A JP 4351178 B2 JP4351178 B2 JP 4351178B2
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- 239000004065 semiconductor Substances 0.000 title claims description 16
- 230000007704 transition Effects 0.000 claims description 29
- 239000003990 capacitor Substances 0.000 claims description 24
- 230000005684 electric field Effects 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 description 20
- 230000003071 parasitic effect Effects 0.000 description 13
- 230000005540 biological transmission Effects 0.000 description 10
- 239000000758 substrate Substances 0.000 description 7
- 230000007423 decrease Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000013500 data storage Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000007562 laser obscuration time method Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229920006395 saturated elastomer Polymers 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 229910021193 La 2 O 3 Inorganic materials 0.000 description 1
- -1 Pr 2 O 3 Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 230000005283 ground state Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
Description
図1は、第1の実施の形態に係るDRAMの回路構成を示している。図中、WL、/WLは差動ワード線であり、BL、/BLは差動ビット線である。差動ワード線WL、/WLと差動ビット線BL、/BLの各交点にはメモリセルMCがそれぞれ配置されている。各メモリセルMCは対応する差動ワード線WL,/WL及び差動ビット線BL,/BLに接続されている。
ここで、センスアンプ16の動作開始電圧をΔV、各ビット線の容量をCb=150fF、電源電圧Vdd=2.5Vとすると、ΔV=(Vdd/2)(Cs/Cs+Cb)=41mVとなる。
次に本発明をSRAMに実施した場合を説明する。
Claims (8)
- それぞれ差動信号ペア線路で構成されたワード線及びビット線と、
前記ワード線及びビット線に接続されたメモリセルと、
前記ビット線に接続されたセンスアンプとを具備し、
前記メモリセルは、同じウエル領域内に隣り合うように形成され、前記ワード線の差動信号により差動的に動作するペアトランジスタを有し、かつ前記センスアンプは、同じウエル領域内に隣り合うように形成され、前記ビット線の差動信号により差動的に動作するペアトランジスタを有し、
前記各ペアトランジスタは、前記各ペアトランジスタに供給される差動信号の遷移時に、各ペアトランジスタ相互間で電荷の授受が行われて高速状態遷移が促進される平面距離を隔てて形成されていることを特徴とする半導体記憶装置。 - 前記メモリセル及びセンスアンプの動作を制御する制御回路をさらに具備し、
前記制御回路は、同じウエル領域内に隣り合うように形成され、差動的に動作するペアトランジスタを有することを特徴とする請求項1記載の半導体記憶装置。 - 前記差動信号ペア線路の特性インピーダンスが50Ω〜200Ωの範囲の値であることを特徴とする請求項1記載の半導体記憶装置。
- 前記メモリセルは、
ドレインが前記差動信号ペア線路で構成されたビット線に接続され、ゲート電極が前記差動信号ペア線路で構成されたワード線の一方のワード線に接続されたトランスファゲート用の第1のトランジスタと、
前記第1のトランジスタのソースとグランドとの間に接続されたキャパシタと、
ドレイン及びソースがグランドに接続され、ゲート電極が前記差動信号ペア線路で構成されたワード線の他方のワード線に接続され、前記第1のトランジスタとペアトランジスタを構成するトランスファゲート用の第2のトランジスタとを含むことを特徴とする請求項1ないし3のいずれか1項記載の半導体記憶装置。 - 前記キャパシタは、ハイk材料からなる絶縁物を一対の金属電極で挟んだ構造を有することを特徴とする請求項4記載の半導体記憶装置。
- 前記メモリセルは、
ソース、ドレインの一方が前記差動信号ペア線路で構成されたビット線の一方のビット線に接続され、ゲート電極が前記差動信号ペア線路で構成されたワード線の一方のワード線に接続されたトランスファゲート用の第1のトランジスタと、
ソース、ドレインがグランドに接続され、ゲート電極が前記差動信号ペア線路で構成されたワード線の他方のワード線に接続され、前記第1のトランジスタとペアトランジスタを構成する第2のトランジスタと、
ソース、ドレインの一方が前記差動信号ペア線路で構成されたビット線の他方のビット線に接続され、ゲート電極が前記差動信号ペア線路で構成されたワード線の一方のワード線に接続されたトランスファゲート用の第3のトランジスタと、
ソース、ドレインがグランドに接続され、ゲート電極が前記差動信号ペア線路で構成されたワード線の他方のワード線に接続され、前記第3のトランジスタとペアトランジスタを構成する第4のトランジスタと、
前記第1のトランジスタのソース、ドレインの他方と前記第3のトランジスタのソース、ドレインの他方とに接続されてデータを記憶するフリップフロップ回路とを含むことを特徴とする請求項1ないし3のいずれか1項記載の半導体記憶装置。 - 前記ウエル領域内における電荷のモビリティをμ(cm2/Sv)、前記各ペアトランジスタのチャネル領域間の電界強度をE(V/cm)、前記差動信号の遷移時間をtr(s)、前記差動信号の周波数をf(1/s)としたときに、前記平面距離の最大値dmaxが、
dmax=trμE=0.35fμE
で与えられることを特徴とする請求項1記載の半導体記憶装置。 - 前記センスアンプ内のトランジスタを含む全てのトランジスタのオン抵抗を並列にしたインピーダンスと等しいか、もしくはそれ以下の特性インピーダンスを持ち、前記センスアンプに高電位側及び低電位側の電源電圧を供給するペア線路をさらに具備したことを特徴とする請求項1記載の半導体記憶装置。
Priority Applications (5)
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JP2005050632A JP4351178B2 (ja) | 2005-02-25 | 2005-02-25 | 半導体記憶装置 |
CN2006100582101A CN1825476B (zh) | 2005-02-25 | 2006-02-24 | 半导体存储器装置 |
TW095106538A TWI305916B (en) | 2005-02-25 | 2006-02-24 | Semiconductor memory device |
US11/360,681 US7280385B2 (en) | 2005-02-25 | 2006-02-24 | Semiconductor memory device |
KR1020060018207A KR100720624B1 (ko) | 2005-02-25 | 2006-02-24 | 반도체 메모리 장치 |
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JP4351178B2 true JP4351178B2 (ja) | 2009-10-28 |
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JP (1) | JP4351178B2 (ja) |
KR (1) | KR100720624B1 (ja) |
CN (1) | CN1825476B (ja) |
TW (1) | TWI305916B (ja) |
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US8247874B2 (en) * | 2010-08-26 | 2012-08-21 | Infineon Technologies Austria Ag | Depletion MOS transistor and charging arrangement |
US8422294B2 (en) * | 2010-10-08 | 2013-04-16 | Infineon Technologies Ag | Symmetric, differential nonvolatile memory cell |
CN102446545B (zh) * | 2011-12-31 | 2014-04-16 | 上海交通大学 | 适用于低功耗芯片的静态随机访问存储器的设计方法 |
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NL8901376A (nl) * | 1989-05-31 | 1990-12-17 | Philips Nv | Geintegreerde geheugenschakeling met een leesversterker. |
JP3028913B2 (ja) * | 1994-11-10 | 2000-04-04 | 株式会社東芝 | 半導体記憶装置 |
JP3549479B2 (ja) | 2000-10-16 | 2004-08-04 | 寛治 大塚 | バラクタデバイスを備えた半導体集積回路 |
JP2002298588A (ja) * | 2001-03-30 | 2002-10-11 | Fujitsu Ltd | 半導体装置及びその検査方法 |
US6711044B2 (en) * | 2001-07-02 | 2004-03-23 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory device with a countermeasure to a signal delay |
JP3723477B2 (ja) * | 2001-09-06 | 2005-12-07 | 松下電器産業株式会社 | 半導体記憶装置 |
US6678189B2 (en) | 2002-02-25 | 2004-01-13 | Hewlett-Packard Development Company, L.P. | Method and system for performing equipotential sensing across a memory array to eliminate leakage currents |
JP2003308693A (ja) * | 2002-04-11 | 2003-10-31 | Mitsubishi Electric Corp | 半導体記憶装置 |
US6845033B2 (en) * | 2003-03-05 | 2005-01-18 | International Business Machines Corporation | Structure and system-on-chip integration of a two-transistor and two-capacitor memory cell for trench technology |
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- 2006-02-24 US US11/360,681 patent/US7280385B2/en active Active
- 2006-02-24 KR KR1020060018207A patent/KR100720624B1/ko active IP Right Grant
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US20060203586A1 (en) | 2006-09-14 |
CN1825476A (zh) | 2006-08-30 |
KR20060094916A (ko) | 2006-08-30 |
TWI305916B (en) | 2009-02-01 |
CN1825476B (zh) | 2010-10-13 |
KR100720624B1 (ko) | 2007-05-23 |
TW200643951A (en) | 2006-12-16 |
JP2006237330A (ja) | 2006-09-07 |
US7280385B2 (en) | 2007-10-09 |
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