JP4350023B2 - 通信装置 - Google Patents
通信装置 Download PDFInfo
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- JP4350023B2 JP4350023B2 JP2004312618A JP2004312618A JP4350023B2 JP 4350023 B2 JP4350023 B2 JP 4350023B2 JP 2004312618 A JP2004312618 A JP 2004312618A JP 2004312618 A JP2004312618 A JP 2004312618A JP 4350023 B2 JP4350023 B2 JP 4350023B2
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Description
36 制御回路(制御手段)
40 RAM(記憶手段)
44 入力部
Claims (2)
- 所定の情報と当該情報を送信する相手先を記憶する記憶手段と、当該記憶手段に記憶されている前記情報を送信する送信手段と、入力手段と、
当該入力手段による特定の入力操作を禁止するキーロック状態が所定時間以上継続すると、前記送信手段が、前記記憶手段に記憶されている前記情報を送信することを特徴とする通信装置。 - 前記送信手段が、前記記憶手段に記憶されている前記情報を送信した後に、送
信した前記情報を前記記憶手段から削除することを特徴とする請求項1に記載の通信装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004312618A JP4350023B2 (ja) | 2004-10-27 | 2004-10-27 | 通信装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004312618A JP4350023B2 (ja) | 2004-10-27 | 2004-10-27 | 通信装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006128921A JP2006128921A (ja) | 2006-05-18 |
JP4350023B2 true JP4350023B2 (ja) | 2009-10-21 |
Family
ID=36723153
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004312618A Active JP4350023B2 (ja) | 2004-10-27 | 2004-10-27 | 通信装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4350023B2 (ja) |
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2004
- 2004-10-27 JP JP2004312618A patent/JP4350023B2/ja active Active
Also Published As
Publication number | Publication date |
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JP2006128921A (ja) | 2006-05-18 |
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