JP4345392B2 - Automatic clock delay detection circuit - Google Patents

Description

  The present invention relates to a clock delay amount automatic detection circuit, for example, a clock delay amount automatic detection circuit that automatically detects and controls a delay difference between a clock inside the circuit and an external clock.

The delay difference between the clock inside the circuit and the clock coming from the outside is adjusted by actual signal observation or delay measurement value.
However, in the conventional clock generator, a clock based on the clock generated by the clock generator is regressed, and the signal that has entered again has a delay compared to the internal clock, and this delay The amount generally varies from application device to device or with elapsed time. For this reason, there is a problem that it is necessary to constantly adjust the clock between the input and output clock signals. For example, a conventional clock generator outputs a generated clock to an external LSI. Therefore, a signal that has been forwarded based on the clock and re-entered has a greater or lesser delay than the internal clock.

  In a conventional clock generator applied to this type of clock delay amount automatic detection circuit, the generated clock is output to an external LSI. The signal relationship is shown in FIG. In FIG. 6, the clock generator of this conventional example is configured to include a target LSI 20 and an external LSI 21, an operation clock is output from the target LSI 20 to the external LSI 21, and a delay clock is forwarded from the external LSI 21 to the target LSI 20. The

In the conventional clock generator, the delay difference between the output clock and the input clock is directly adjusted by actual signal observation or delay measurement value (see Patent Documents 1, 2, and 3). More specifically, in Patent Document 2, for example, one of the same types of data transfer paths is used to adjust the delay amount of the data latch, and the latch clock with the adjusted delay amount is used for all the same types of data transfer paths. Used as a data latch clock.
Japanese Patent Laid-Open No. 2-123412 Japanese Patent Laid-Open No. 11-3135 Japanese Patent Laid-Open No. 11-46182

  The problem to be solved is that it is necessary to constantly adjust the clock between the input and output clock signals.

The present invention is a clock delay amount automatic detection circuit in which n flip-flops (n is a positive integer greater than or equal to 2) are connected in series and n XORs are connected in series. In the flip-flop, an operation clock generated inside the circuit and output to the outside of the circuit for synchronization between the inside and outside of the circuit, and an adjustment clock obtained by multiplying the operation clock by n times are input. After the clock output from the first flip-flop and the regression clock from which the operation clock is forwarded from outside the circuit are input, a signal having a predetermined waveform is output, and the x-th (1 <x ≦ n is satisfied. The positive integer) flip-flop receives the clock output from the (x-1) th flip-flop and the adjustment clock, and the xth XOR outputs from the xth flip-flop. When the generated clock and the regression clock are input, a signal having a predetermined waveform is output, and when the waveform of the signal output from the first XOR is 0, the delay amount between the operation clock and the regression clock Is detected as being 1 / n minutes of the operation clock, and when the waveform of the signal output from the xth XOR is 0, the delay amount between the operation clock and the regression clock is x / n of the operation clock. It is detected that it is minutes .

  The present invention categorizes and corrects the clock delay amount of the operation clock generated inside the circuit and outputted to synchronize between the inside and outside of the circuit and the regression clock from which the operation clock is outputted and forwarded. This is an automatic quantity detection circuit, and compares the operation timing between the adjustment clock and the regression clock with the adjustment clock generator that creates the adjustment clock with the operation clock multiplied by N (N is a positive integer greater than or equal to 2). And a delay amount detection unit for detecting the delay amount of the regression clock. As a result, the magnitude of the delay amount between the operation clock and the regression clock can be classified and detected.

  1 to 5, there is shown an embodiment of a clock delay amount automatic detection circuit according to the present invention. 1 to 3 show the first embodiment, and FIGS. 4 and 5 show the second embodiment. The clock delay amount automatic detection circuit of these embodiments is a clock delay amount automatic detection circuit that automatically controls the adjustment between a clock signal inside the circuit and a clock signal having a delay difference that has entered from the outside. Composed.

  FIG. 1 shows a circuit configuration example of the clock delay amount automatic detection circuit according to the first embodiment. The clock delay amount automatic detection circuit according to this embodiment includes four flip-flops (circuits) 1 to 4, three signal lines 5 to 7, and six logic gates (circuits) 8 to 13. The six logic gates (circuits) 8 to 13 are classified into four XORs (circuits) 8 to 11 and two selectors (circuits) 12 and 13.

The configuration contents of the clock delay amount automatic detection circuit of this embodiment shown in FIG. 1 will be described below.
In the circuit component shown in FIG. 1, the relationship between the serial part number, the part name, and the part number is as follows: (1) flip-flop 1, (2) flip-flop 2, (3) flip-flop 3, (4) Flip-flop 4, (5) SIG1, (6) SIG2, (7) SIG3, (8) XOR1, (9) XOR2, (10) XOR3, (11) XOR4, (12) Selector 1, (13) Selector 2 , Have a relationship. Among these, (5) SIG1 is an operation clock, and (6) SIG2 is an adjustment clock for automatic adjustment.

In the clock delay amount automatic detection circuit shown in FIG. 1, (5) SIG1 of the clock signal generated in the internal circuit is converted into four flip-flops, (1) flip-flop 1, (2) flip-flop 2, and (3). flip-flop 3, (4) flip-flop 4, in which cascaded. Further, (6) SIG2, which is an adjustment clock for automatic adjustment (four times speed clock) , is input as the gate signals of these four flip-flops 1 to 4.
The output signals from the four flip-flops 1 to 4 are set as one input signal of the four XORs 1 to 4. In addition, (7) SIG3 which is the other input signal of these four XOR1-4 is a signal (feedback signal) which (5) SIG1 delayed by (DELTA ) t . These input signals are shown in FIG.

The clock delay amount automatic detection circuit according to the present embodiment is configured as a circuit in which the following input signals are input to each of the four flip-flops 1 to 4.
1) The flip-flop 1 uses (5) SIG1 and (6) SIG2 as input signals.
2) The flip-flop 2 uses (1) the output signal of the flip-flop 1 and (6) SIG2 as input signals.
3) The flip-flop 3 uses (2) the output signal of the flip-flop 2 and (6) SIG2 as input signals.
4) The flip-flop 4 uses (3) the output signal of the flip-flop 3 and (6) SIG2 as input signals.

  The four flip-flops 1 to 4 configured as described above have their input / output signals connected in series. Based on this configuration, (5) SIG1 is input to the first (1) flip-flop 1, and the output signal of the first (1) flip-flop 1 is input to the second (2) flip-flop 2. Further, the second (2) flip-flop 2 is sequentially cascaded to the third (3) flip-flop 3. The same (5) SIG2 is input to each trigger input terminal.

  (8) XOR1 has (1) the output signal of flip-flop 1 and (7) SIG3 as an input signal, (9) XOR2 has (2) the output signal of flip-flop 2 and (7) SIG3 as an input signal, (10) XOR3 has (3) output signal of flip-flop 3 and (7) SIG3 as input signal, and (11) XOR4 has (4) output signal of flip-flop 4 and (7) SIG3 as input signal It has become.

  The (12) selector 1 uses (8) XOR1, (9) XOR2, (10) XOR3, and (11) XOR4 as input signals. Further, (13) selector 2 has a circuit configuration in which the output signal of (1) flip-flop 1, (2) flip-flop 2, (3) flip-flop 3, and (4) flip-flop 4 is used as an input signal. .

  As an embodiment, FIG. 2 shows a time chart when a quadruple clock is input as an adjustment clock signal to the clock delay amount automatic detection circuit having the circuit configuration as shown in FIG. In FIG. 2, SIG1 is an original clock, SIG2 is a quadruple clock, and SIG3 is a delayed clock. In addition, in the relationship between SIG1 and SIG2, it is necessary to allocate a clock faster than SIG1 as SIG2.

FIG. 3 shows examples of four types of output signals for classifying delay amounts.
In the above circuit connection configuration, the signal amount between SIG1 and SIG3 has a delay amount Δt. Depending on the magnitude of the delay amount Δt, four types of signal waveforms such as (1) output 1 to (4) output 4 shown in FIG. 3 are output as output signals of the four flip-flops in FIG. Therefore, the timing can be automatically adjusted by selecting a timing that results in the waveform of (4) output 4 in FIG. That is, the delay amount of the feedback signal (7) SIG3 can be classified into four stages based on the four times the adjustment clock.

  According to the above embodiment, it is not necessary to adjust the timing between signals between input and output, and it is not necessary to perform delay adjustment by external setting based on external test or measurement value, and delay adjustment is automatically performed. There is an effect that can be done. The adjustment clock can be classified into an arbitrary number of stages by adjusting the multiplication factor of the quadruple clock.

3 shows a circuit configuration example of an embodiment of an automatic clock delay amount detection circuit. Example 1 A time chart when a quadruple clock is input as an adjustment clock signal is shown. 4 shows examples of four types of output signals for classifying delay amounts. The circuit structural example of the clock delay amount automatic detection circuit is shown. (Example 2) 10 is a timing chart of signals corresponding to Example 2. It is a block block diagram for demonstrating a prior art example.

Explanation of symbols

1-4 Flip-flop (circuit)
8-11 XOR (circuit)
12, 13 Selector (circuit)
Δt clock delay (time)

Claims (2)

A clock delay amount automatic detection circuit in which n (n is a positive integer of 2 or more) flip-flops are connected in series, and n XORs are connected in series,
In the first flip-flop, an operation clock generated inside the circuit and outputted to the outside of the circuit for synchronization between the inside and outside of the circuit, and an adjustment clock obtained by multiplying the operation clock by n times are input.
The first XOR receives the clock output from the first flip-flop and the regression clock from which the operation clock is routed from outside the circuit, and then outputs a signal having a predetermined waveform. ,
In the x-th (a positive integer satisfying 1 <x ≦ n) flip-flop, the clock output from the (x−1) -th flip-flop and the adjustment clock are input,
A signal having a predetermined waveform is output to the xth XOR after the clock output from the xth flip-flop and the regression clock are input.
When the waveform of the signal output from the first XOR is 0, the delay amount between the operation clock and the regression clock is detected to be 1 / n minutes of the operation clock,
When the waveform of the signal output from the x-th XOR is 0, the delay amount between the operation clock and the regression clock is detected to be x / n minutes of the operation clock. Automatic clock delay detection circuit. 2. The clock delay amount automatic detection circuit according to claim 1 , wherein the number of the flip-flops and the XOR is an even number of 2 or more.

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