JP4339563B2 - Manufacturing method of semiconductor substrate and manufacturing method of semiconductor device using this method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor substrate in which a SiGe film is stacked on a Si substrate or an SOI substrate, a method for manufacturing a semiconductor device manufactured using the substrate, and a semiconductor device.
[0002]
[Prior art]
A strained SiGe film having a lattice constant different from that of Si is formed on the Si substrate for the purpose of improving the mobility of electrons and holes passing through the channel region, and is generated in the SiGe film due to mismatch of the lattice constant with Si. There is known a method of forming an upper Si film as a cap layer on a SiGe film after alleviating such strain by introducing misfit dislocations. For example, as shown in FIG. 6, edge dislocations 16 are generated at the interface between the Si substrate 1 and the SiGe film 2 (14 in the figure is Si atoms and 15 is Ge atoms), and the lattice is relaxed. The upper Si film formed on the SiGe film is pulled by the SiGe film having a lattice constant larger than that of the Si film, thereby generating strain in the upper Si film, thereby changing the band structure and improving the carrier mobility. To do.
[0003]
As a method for relaxing the strain of the SiGe film, a method of increasing the strain elastic energy of the SiGe film by increasing the thickness of the SiGe film to relax the lattice is known.
For example, it has been announced that the SiGe film is gradually increased to form a concentration-gradient SiGe film having a concentration gradient of about 1 μm, thereby reducing the strain of the SiGe film (for example, see Non-Patent Document 1 by YJ Mii et al.). ).
[Non-Patent Document 1]
Appl. Phys. Lett. 59 (13), 1611 (1991)
[0004]
In addition, as a method of relieving the strain of the thin film SiGe film formed on the Si substrate, the thin film SiGe film is subjected to an ion implantation process such as hydrogen and then subjected to an annealing process at a high temperature, thereby forming a defect layer in the Si substrate. It is known that the stacking faults generated cause slipping and misfit dislocations are generated at the SiGe / Si interface, and that strain relaxation is achieved by hydrogen ion implantation using this method (for example, non-patent by H. Trinkaus et al. Reference 2).
[Non-Patent Document 2]
Appl. Phys. Lett. 76 (24), 3552 (2000)
[0005]
[Problems to be solved by the invention]
However, in the method of forming a thick SiGe film and increasing the strain elastic energy of the SiGe film to achieve lattice relaxation, the critical film thickness for obtaining a complete crystal of the SiGe film is exceeded. A great number of defects will occur.
[0006]
In the case of a thick film, since it grows while self-relaxing the strain, streaky roughness (unevenness) at intervals of several tens of μm, called a cross hatch, is generated on the surface of the SiGe film and cannot be used as it is as a semiconductor substrate. Therefore, a planarization process such as a CMP process is essential, and a SiGe film must be further grown on the SiGe film surface on the substrate subjected to the planarization process.
[0007]
On the other hand, by performing ion implantation treatment of hydrogen or the like and high-temperature annealing treatment, a stacking fault formed in a defective layer in the underlying Si substrate causes slip, and misfit dislocations are generated at the SiGe / Si interface, thereby causing a SiGe film. In the method of relieving the lattice strain, defects are less likely to occur as compared with the thick SiGe film described above. However, as shown in FIG. 3, threading dislocations 9 are generated from misfit dislocations 8 that are not terminated. The threading dislocations 9 reach the surface of the SiGe film through the (111) plane 10 of the SiGe film, and further reach the upper Si layer formed thereon, and the threading dislocations 9 terminate in energy. Stabilize.
[0008]
In the semiconductor substrate in which the SiGe film is laminated on the underlying Si substrate (or on the underlying SOI substrate) by using this phenomenon in reverse, the strain of the SiGe film is sufficiently relaxed and the element is formed. An object of the present invention is to provide a method of manufacturing a semiconductor substrate in which threading dislocations generated in the semiconductor substrate are suppressed. It is another object of the present invention to provide a method for manufacturing a semiconductor device using the semiconductor substrate and a semiconductor device.
[0009]
[Means for Solving the Problems]
The method for manufacturing a semiconductor substrate of the present invention made to solve the above-mentioned problems is as follows: (a) a semiconductor substrate in which a SiGe film is laminated on a base Si substrate or a base SOI substrate, and (b) a SiGe film is formed on the SiGe film. Patterning an ion implantation preventive film in a region where an element is to be formed; (c) implanting ions into a semiconductor substrate on which the ion implantation preventive film is formed;
(D) The present invention is characterized in that threading dislocations caused by implanted ions are generated in regions other than regions where elements are formed by removing the ion implantation preventing film and performing an annealing treatment.
[0010]
According to this method, since the implantation preventing film is formed in advance on the region where the element of the semiconductor substrate is formed before ion implantation, and the ion implantation processing is performed using this as a mask, the implantation preventing film is formed. Ions are partially implanted in the unexposed region.
When this substrate is annealed, minute holes are formed in the partial region where the ion-implanted element is implanted, and stacking faults are generated. The generated stacking fault slides on the (111) plane of the Si substrate and causes misfit dislocation at the SiGe / Si interface, thereby causing lattice relaxation.
Here, since ion implantation is performed using the patterned ion implantation prevention film as a mask, misfit dislocations are formed in regions other than the element formation region, and from the misfit dislocations, the SiGe film penetrates the substrate surface. Reaching threading dislocation occurs. This threading dislocation is reduced when forming STI (Shallow Trench Isolation) and LOCOS (Local Oxidation of Silicon) in a subsequent element isolation process of a device manufacturing process such as a diode, transistor, or LSI.
Therefore, since misfit dislocations hardly occur in the element formation region, a semiconductor element can be formed in a region without threading dislocations.
[0011]
Further, in the above method, after the step (a), an implantation protective film is formed on the SiGe film, and in the step (b), an ion implantation prevention film is formed on the implantation protective film corresponding to the element formation region, and (d) The implantation protective film may be removed together with the ion implantation prevention film in the process.
This prevents contamination materials from entering the SiGe film during ion implantation, and requires low acceleration energy below the device specification limit of the ion implantation apparatus when the SiGe film is thin. Even under such conditions, the lattice distortion of the thin SiGe film can be relaxed by adjusting the film thickness of the implantation protective film instead of adjusting the acceleration energy.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
As described above, the present invention forms (a) a semiconductor substrate in which a SiGe film is laminated on a base Si substrate or a base SOI substrate, and (b) an ion implantation prevention film in a region where an element is formed on the SiGe film. (C) ions are implanted into the semiconductor substrate on which the ion implantation prevention film is formed, and (d) the ion implantation prevention film is removed and an annealing process is performed.
[0013]
When a Si substrate is used as the underlying substrate, a Si single crystal substrate is preferable, but other Si substrates such as a polycrystalline Si substrate may be used as long as the SiGe film can be heteroepitaxially grown on the substrate. The same applies to an SOI substrate as long as the SiGe film can be epitaxially grown on the Si layer of the SOI substrate.
[0014]
The SiGe film may be formed by any apparatus as long as it is an epitaxial growth film formed on Si. For example, silane gas (SiH ₄ ) or germane gas (GeH ₄ ) is used as a source gas. The SiGe film having a desired Ge concentration and a desired film thickness can be formed by the low pressure vapor phase growth apparatus (LPCVD).
[0015]
The semiconductor element formed in the element formation region may be any element using a semiconductor material such as a diode, a transistor, or an LSI in which the element is integrated. In particular, the element can improve carrier mobility and prevent leakage current. It is preferable to form an element that affects the performance of the device.
[0016]
For the ion implantation prevention film, a material and a film thickness that can prevent irradiation of ions irradiated into the semiconductor substrate by blocking the irradiated ions in accordance with the implantation conditions of the ion implantation apparatus are selected. It is preferable to use a resist, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like.
This ion implantation preventing film can be formed in a desired region on the semiconductor substrate by a known patterning technique using a mask or the like.
[0017]
The ion implantation process is performed using a known ion implantation apparatus. As an ion species for ion implantation, hydrogen is preferable, but not limited thereto, an inert gas such as helium, neon, and argon, an ionized group IV element such as Si, or a mixed gas thereof may be used.
[0018]
In the ion implantation apparatus, the ion implantation amount (dose amount) and ion implantation energy can be appropriately changed as setting parameters, and by optimizing the material and film thickness of the ion implantation prevention film together with these, The peak position (depth) should be on the substrate side of the SiGe film / underlying Si substrate interface in the region without the ion implantation preventive film, and remain in the ion implantation preventive film in the region where the ion implantation preventive film is formed. To.
[0019]
When the ion implantation process is completed, the ion implantation preventing film is removed. The removal method may be a known removal technique depending on the material used as the ion implantation prevention film. For example, when a photoresist is used as the ion implantation prevention film, it can be removed by dissolution with an organic solvent, or silicon oxide film or the like by dry etching or wet etching.
[0020]
After removing the ion implantation preventing film, the semiconductor substrate is annealed. The annealing process is performed using a furnace apparatus (heat treatment furnace) capable of introducing an atmospheric gas such as nitrogen, hydrogen, or argon. The annealing temperature is preferably 700 ° C. to 900 ° C., for example, it is preferable to perform annealing at 800 ° C. By this annealing treatment, minute holes are formed near the peak position (depth) of the implanted ions.
[0021]
In the present invention, a process of forming an implantation protective film on the SiGe film after forming the SiGe film may be added. In this case, it is preferable to stack any one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or these as an implantation protective film.
[0022]
In the present invention, one or more semiconductor films may be formed on the annealed SiGe film.
For example, a second SiGe film having a Ge concentration different from that of the first SiGe film subjected to strain relaxation can be formed as a semiconductor film. As a result, a film with less roughness can be formed even if it becomes a thick SiGe film as a whole, and a semiconductor device using a semiconductor substrate using the thick SiGe film can be formed. For example, even in a CMOS device with a high power supply voltage, the depletion layer region can reach the interface between the first SIGe film where the misfit dislocation exists and the Si substrate, thereby preventing junction leakage current. Can do.
[0023]
In the present invention, an upper Si thin film having lattice strain may be formed on the SiGe film after annealing or on the semiconductor film further formed thereon.
The strained Si thin film thus prepared has an energy band structure that is changed, and an upper Si layer having a carrier mobility higher than usual can be obtained.
[0024]
In the present invention, a semiconductor substrate can be manufactured by any of the methods described above, and a semiconductor element can be formed in an element formation region on the semiconductor substrate. Since the semiconductor element thus produced is not affected by threading dislocations, it can be made into a semiconductor element having excellent performance such as a small junction leak.
[0025]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Embodiment 1
FIG. 1 shows a process diagram of a semiconductor substrate manufacturing method according to an embodiment of the present invention.
First, as a pretreatment of the Si substrate 1 having an n-type (100) surface, boiling sulfuric acid and RCA cleaning are performed, and the natural oxide film on the substrate surface is removed with 5% dilute hydrofluoric acid. Next, a SiGe film 2 having a Ge concentration of 28.5% and a thickness of 157 nm is formed on the Si substrate 1 using germane (GeH ₄ ) and silane (SiH ₄ ) as raw materials using a low-pressure vapor deposition (LP-CVD) apparatus. Epitaxial growth is performed at 500 ° C. until it becomes (FIG. 1A).
[0026]
Here, before performing ion implantation, an alignment mark mask is prepared and an alignment mark is formed on the Si substrate 1 in advance. This is a pattern of an ion implantation protective film that covers the element formation region and is formed for ion implantation into a region other than the element formation region (region that becomes an element separation portion) (this resist pattern is an element separation mask). And alignment with a photoresist pattern at the time of element formation using the same element isolation mask (STI, LOCOS, etc.) is performed using this alignment mark as a reference.
[0027]
After the alignment mark is formed, a photoresist is spin-coated on the entire surface of the wafer to a thickness of 500 to 1500 nm, and a photomask for forming an i-line stepper and the above-described element isolation portions (STI, LOCOS, etc.) used during LSI manufacturing A patterned photoresist 3 that functions as an ion implantation preventive film on a region to be an element formation region on the wafer (on the SiGe film 2) by aligning with the reference alignment mark, exposing, and developing with an alkali developer. Is formed (FIG. 1B).
[0028]
Hydrogen ions 4 are implanted into the substrate under the conditions of an implantation energy of 18 KeV, a hydrogen ion amount (dose amount) of 3 × 10 ¹⁶ H ⁺ / cm ² , and a tilt angle of 7 ° (FIG. 1C). According to this implantation condition, the implantation peak position (depth) at which the implantation amount of hydrogen ions reaches a peak is a region where the photoresist is not formed (a region serving as an interelement separation portion) at the SiGe film / Si substrate interface. The position is 70 nm on the substrate side. On the other hand, the peak position (depth) in the region covered with the photoresist 3 is set to be near the center of the film thickness of the photoresist 3. Thereby, in the region covered with the photoresist 3, the implanted hydrogen ions do not reach the SiGe film or the Si substrate.
[0029]
The photoresist 3 on the substrate into which hydrogen ions have been implanted is removed, and after boiling sulfate and RCA, annealing is performed at 800 ° C. for 10 minutes in a furnace 5 in a nitrogen atmosphere.
As a result, minute vacancies called microcavities 17 are generated in the vicinity of the implantation peak of hydrogen ions implanted in the region where the photoresist 3 is not formed (region serving as the element isolation portion). FIG. 4 is a cross-sectional TEM photograph of the Si substrate 1 including the microcavity 17, and it can be seen that the size of the holes is about 10 μm.
As the stacking fault layer 6 generated by the microcavity 17 slips, misfit dislocations occur at the SiGe / Si interface, and lattice relaxation occurs (FIG. 1 (d)).
[0030]
If a thicker SiGe film is required, an (second) SiGe film 11 having a Ge concentration of 28.5% is epitaxially grown as an intermediate layer semiconductor film on the strain-relaxed SiGe / Si substrate to a film thickness of 300 nm. . As a result, the total thickness of the SiGe film becomes 457 nm. For example, even in a CMOS device with a high power supply voltage, the first SiGe film (annealed SiGe film) in which the depletion layer region spreads has misfit dislocations. ) And the Si substrate can be prevented from generating a junction leakage current.
[0031]
A Si film or SiGe thin film may be further formed as an intermediate semiconductor film between the first and second SiGe films. Thus, there is no restriction | limiting in the number of layers of the semiconductor film formed in the middle.
Thereafter, the upper Si layer 12 functioning as a channel region through which carriers pass is epitaxially grown to a thickness of 20 nm.
The upper Si layer 12 created through such a process is lattice-matched with the underlying strain-relaxed SiGe film having a larger lattice constant or the intermediate layer semiconductor film affected by the SiGe film, and has a tensile strain, thereby providing a carrier. Increases mobility.
[0032]
At this stage, misfit dislocations generated at the SiGe / Si substrate interface are not terminated in a region other than the element formation region (region serving as an element separation portion), and penetrates to the substrate surface layer (upper Si layer 12 in the above example). Dislocation 9 has been reached (FIG. 1 (e)).
[0033]
Thereafter, a device manufacturing process is started using this substrate. Mask used (inter-element isolation step in STI (S hallow T rench I solation ) by element separating step in device fabrication process is the same as the patterning mask for ion implantation prevention film previously used, alignment of the mask The first alignment mark is used as a reference), a photoresist (not shown) is patterned using a mask for the element isolation process, the substrate is etched by 500 nm, and the element is isolated by embedding an oxide film and CMP processing. By forming the portion 13, a substrate free from defects such as threading dislocations 9, stacking fault layers 6, and microcavities 17 (see FIG. 4) can be formed (FIG. 1 (f)).
Then, a semiconductor element such as a MOS transistor is formed in the element formation region by a normal semiconductor manufacturing process using the substrate after the separation process between elements.
[0034]
FIG. 5 is a diagram showing a cross-sectional configuration of the MOS transistor formed in the element formation region by the above process. In this figure, the same components as those in FIG. In the figure, 1 is a Si substrate, 2 is a SiGe film, 11 is a second SiGe film formed as an intermediate semiconductor film, and 12 is an upper Si film. 18 is a polysilicon gate (gate electrode), 19 is a gate insulating film, 20 is a source region, 21 is a drain region, and 22 is a sidewall.
In this MOS transistor, since the upper Si layer 12 having improved carrier mobility is formed by being pulled by the SiGe film 11, it can function as a channel layer.
Further, since no threading dislocation is generated in the vicinity of the MOS including the source region 20 and the drain region 21, leakage current due to threading dislocation can be prevented.
[0035]
In this embodiment, a photoresist is used as the ion implantation preventing film. However, for example, a silicon oxide film can be used instead. In this case, a silicon oxide film is formed on the SiGe film 2 to a thickness of about 100 to 10,000 nm, a photoresist is spin-coated thereon, and a photoresist pattern is formed on the element formation region by exposure and development. A silicon oxide film is patterned on the element formation region by RIE (Reactive Ion Etching) or the like using the mask as a mask.
[0036]
This is because, for example, if the ion implantation energy is high and it is necessary to apply a thick photoresist, or if a fine trench with a narrow pattern pitch is required, the photoresist aspect ratio becomes too high and the resist pattern collapses. This is an effective means when the resist film cannot be formed to a required thickness.
Further, the ion implantation is not limited to hydrogen, and the same effect can be obtained with, for example, an inert gas such as helium or a group IV element such as Si.
[0037]
Embodiment 2
Next, a second embodiment of the present invention will be described with reference to FIG. As in the first embodiment, low pressure vapor phase growth is performed on an n-type (100) silicon substrate 1 that has been subjected to RCA washing with sulfuric acid boil as a pretreatment and the natural oxide film on the substrate surface is removed with 5% dilute hydrofluoric acid. Using an (LP-CVD) apparatus, a germanium (GeH ₄ ) and silane (SiH ₄ ) raw material is used to epitaxially grow a SiGe film having a Ge concentration of 40.7% at 500 ° C. until a film thickness of 25 nm is obtained. A low-temperature silicon oxide film 7 functioning as an implantation protective film is formed on the film 2 until the film thickness reaches 50 nm (FIG. 2A).
Here, before ion implantation is performed in the same manner as in the first embodiment, an alignment mark mask is prepared and a photoresist pattern formed at the time of ion implantation and a photoresist pattern at the time of forming an element isolation portion (STI, LOCOS, etc.) An alignment mark for adapting the above is attached on the Si substrate 1.
[0038]
Next, a photoresist is spin-coated on the entire surface of the wafer so as to have a film thickness of 500 to 1500 nm, exposed using an i-line stepper and a photomask for forming an element isolation part used in LSI manufacturing, and developed with an alkali developer. As a result, a patterned photoresist 3 functioning as an ion implantation preventing film is formed on the element formation region on the wafer (FIG. 2B).
[0039]
Hydrogen ions are implanted into the substrate under the conditions of an implantation energy of 6 KeV, a hydrogen ion implantation amount (dose amount) of 3 × 10 ¹⁶ H ⁺ / cm ² , and a tilt angle of 7 ° (FIG. 2C).
Under this implantation condition, a hydrogen ion implantation peak is a region covered with the photoresist 3 at a position 30 nm on the substrate side of the SiGe film / Si substrate interface in a region where the photoresist 3 is not present (a region serving as an element isolation portion). In the (region to be an element formation region), it is set to be near the upper layer of the film thickness of the photoresist 3. As a result, hydrogen ions do not reach the SiGe film or the Si substrate in the region covered with the photoresist 3. Next, after removing the photoresist 3 and the silicon oxide film 7 and performing boil sulfate boiling and RCA cleaning, annealing is performed at 800 ° C. for 10 minutes using a furnace 5 in a nitrogen atmosphere. As a result, minute vacancies called microcavities 17 are generated in the vicinity of the implantation peak of hydrogen ions implanted in a region where there is no photoresist (a region serving as an element isolation portion) (see FIG. 4), and the resulting laminated layer When the defect 6 slips, misfit dislocation occurs at the SiGe / Si interface and lattice relaxation occurs (FIG. 2 (d)).
[0040]
In this embodiment, the formation of the implantation protective film 7 can prevent contamination by contaminants during ion implantation. Furthermore, when hydrogen ions are to be implanted, the acceleration voltage of the device specifications of the ion implantation apparatus is the lower limit (for example, about 5 KeV), and the film thickness is as thin as 25 nm without forming the implantation protective film 7 with the acceleration voltage. Even when annealing is performed by implanting hydrogen ions into the SiGe film, even if there is a problem that the peak position of the implanted ions becomes too deep and cannot be sufficiently relaxed, the implantation protective film 7 can be implanted by increasing the film thickness. The peak position can be controlled, and even a very thin SiGe film can be strain-relieved with the current ion implantation apparatus.
[0041]
Further, the implantation protective film 7 is not limited to the silicon oxide film, and the same effect can be obtained by, for example, a silicon nitride film or a silicon oxynitride film.
[0042]
Similar to the first embodiment, the second SiGe film 11 having a Ge concentration of 28.5% may be epitaxially grown on the strain-relaxed SiGe / Si substrate to a thickness of 300 nm as an intermediate semiconductor film.
[0043]
Then, the upper Si layer 12 is epitaxially grown to a thickness of 20 nm as a channel region through which carriers pass. At this stage, the misfit dislocations generated at the SiGe / Si interface are not terminated in the region other than the element formation region (the region serving as the element separation portion), and the threading dislocation 9 reaches the substrate surface ( FIG. 2 (e)).
After that, in the element isolation process by STI, a photoresist (not shown) is formed using a mask for the element isolation process in the same manner as in the first embodiment, the substrate is etched by 500 nm, the oxide film is embedded and CMP is performed between the elements. By forming the separation portion, a substrate free from defects such as the minute holes 6, the threading dislocations 9, and the microcavities 17 can be formed (FIG. 2F). Then, using this substrate, a semiconductor element such as a MOS transistor is formed in the element formation region (FIG. 5).
[0044]
Embodiment 3
Although the Si substrate is used in the first and second embodiments, a semiconductor substrate having the same properties as those in the first and second embodiments is created by using an SOI substrate whose surface layer is a single crystal Si film instead. can do.
When an SOI substrate is used, the surface layer Si film thickness of the SOI substrate needs to be thicker than the distance between the peak position of ion implantation and the SiGe / Si interface, specifically about twice as thick. It is desirable to be.
[0045]
【The invention's effect】
As described above, according to the present invention, in the element formation region of the Si or SOI substrate, it is a semiconductor substrate having good crystallinity that does not have threading dislocations causing leakage current, and has a sufficient relaxation rate. A semiconductor substrate having a strain relaxation SiGe film layer can be manufactured.
[0046]
In addition, by forming an upper strained Si thin film on the strain-relaxed SiGe film, it is possible to manufacture a semiconductor substrate with improved carrier mobility compared to a conventional Si substrate.
By manufacturing a semiconductor device using this semiconductor substrate, a semiconductor device having excellent performance can be created.
[Brief description of the drawings]
FIG. 1 is a process diagram illustrating a method for manufacturing a semiconductor substrate according to an embodiment of the present invention.
FIG. 2 is a process diagram illustrating a method for manufacturing a semiconductor substrate according to another embodiment of the present invention.
FIG. 3 is a schematic diagram for explaining how threading dislocations are generated from misfit dislocations that are not terminated.
FIG. 4 is a cross-sectional TEM photograph showing a microcavity generated in a Si substrate.
FIG. 5 is a diagram showing a configuration of a MOS transistor as a semiconductor device according to an embodiment of the present invention.
FIG. 6 is a schematic diagram for explaining an atomic arrangement state at the interface between a SiGe film in a lattice-relaxed state and a Si substrate.
[Explanation of symbols]
1: Si substrate (SOI substrate)
2: SiGe film 3: Photoresist (ion implantation preventing film)
4: Implanted ions 5: Furnace apparatus 6: Stacking fault layer 7: Low-temperature silicon oxide film (implantation protective film)
8: Misfit dislocation 9: Threading dislocation 10: SiGe film (111) surface 11: Second SiGe film (intermediate layer semiconductor film)
12: Upper layer Si film 13: Inter-element separation part 14: Si atom 15: Ge atom 16: Edge dislocation 17: Microcavity 18: Polysilicon gate (gate electrode)
19: Gate oxide film 20: Source region 21: Drain region 22: Side wall

Claims (8)

(A) forming a semiconductor substrate in which a SiGe film is laminated on an underlying Si substrate or an underlying SOI substrate;
(B) patterning a region on the SiGe film where an element is to be formed using an ion implantation prevention film as a mask ;
(C) An ion implantation process is performed so that the peak position of the implanted ions is on the substrate side of the interface between the SiGe film and the underlying Si substrate or the underlying SOI substrate for the semiconductor substrate on which the ion implantation preventing film is formed ,
(D) By removing the ion implantation preventive film and applying an annealing treatment, microvoids are generated near the peak position of the implanted ions, and threading dislocations caused by the microvoids other than the region where the element is formed A method of manufacturing a semiconductor substrate, characterized by comprising:   (A) After the step, an implantation protective film is formed on the SiGe film, an ion implantation prevention film is formed on the implantation protective film corresponding to the element formation region in the step (b), and ion implantation prevention is performed in the step (d). The method of manufacturing a semiconductor substrate according to claim 1, wherein the implantation protective film is removed together with the film.   2. The method of manufacturing a semiconductor substrate according to claim 1, wherein the ion species for ion implantation is at least one element selected from the group consisting of hydrogen, an inert gas, and a group IV element. 2. The method of manufacturing a semiconductor substrate according to claim 1, wherein the ion implantation preventing film is made of at least one of a photoresist, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.   3. The method of manufacturing a semiconductor substrate according to claim 2, wherein the implantation protective film is composed of at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.   2. The method of manufacturing a semiconductor substrate according to claim 1, further comprising forming one or more semiconductor films after the step (d).   7. The method of manufacturing a semiconductor substrate according to claim 1, wherein a Si thin film having lattice strain is formed on the SiGe film or the semiconductor film after the step (d).   8. A method of manufacturing a semiconductor device, comprising: forming a semiconductor element in an element forming region of a semiconductor substrate manufactured by the method according to claim 1.

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