JP2005072464A - Method of manufacturing semiconductor substrate, and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To balance the mobility of nMOS and that of pMOS in CMOS where distortion Si is made to be a channel. <P>SOLUTION: In a method for manufacturing an Si substrate for forming a MOS transistor, an SiGe film is formed as lattice-matching it to an Si substrate surface, an Si film is formed as lattice-matching it on the SiGe film, Ge ions and hydrogen ions are injected to an area where an NMOS transistor is formed, and heat treatment is performed to reduce distortion of only the SiGe film in the area. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor substrate and a method for manufacturing a semiconductor device. Further, the present invention relates to a method for manufacturing a semiconductor substrate in which a strained Si film and a strained SiGe film are simultaneously realized on one substrate, and a high-speed CMOS transistor using the substrate. It relates to a manufacturing method.

In recent years, in order to increase the speed of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), instead of conventional technology using the Si-SiO ₂ MOS interface as a channel, a material having a lattice constant different from that of Si has been used. By forming a heterostructure, that is, by epitaxially growing a material film having a lattice constant different from that of the Si substrate on the Si substrate, the film is subjected to horizontal compression or tensile strain, and the strain is utilized. Techniques for manufacturing high mobility transistors are known.

  For example, as a MOSFET manufacturing technique using strain, a SiGe film having a thickness of about 300 nm and a Ge concentration of 20 atom% (hereinafter simply referred to as “%”) is epitaxially grown on a Si substrate, and a thickness of about 20 nm is formed thereon. Si film is epitaxially grown continuously. Next, hydrogen ions are implanted into the surface of the obtained Si substrate, and then heat treatment at about 800 ° C. is performed. By this heat treatment, stacking faults extending from the hydrogen microvoids generated in the vicinity of the hydrogen injection peak reach the interface between the SiGe film and the Si substrate, and further, misfit dislocations are generated in a direction parallel to the interface. By generating this misfit dislocation, the distortion of the SiGe film is alleviated. At this time, tensile strain is generated in the Si film on the SiGe film whose strain has been relaxed, and the mobility is increased. When this substrate is used, the mobility of nMOS is remarkably improved, but the mobility improvement rate of pMOS is only about half that of nMOS.

  Therefore, a method using a thin strained SiGe film has been proposed as a method for improving the mobility of pMOS. A SiGe film having a compressive strain is formed by epitaxially growing a SiGe film having a Ge concentration of 20 to 40% and a film thickness of 10 to 50 nm on a Si substrate, and further continuously growing a Si film having a thickness of about 20 nm on the SiGe film. It has been experimentally confirmed that when a pMOS transistor is formed on this substrate, a channel is formed in the strained SiGe film, and the mobility is about twice that of the case where the Si substrate is used. ing.

  However, when a normal CMOS is formed using a conventional strained Si substrate, it is difficult to make the improvement rate of the mobility of the pMOS equal to that of the nMOS with the same substrate (for example, see Non-Patent Document 1). Regarding the improvement rate of the mobility of the transistor relative to the Si film, for example, when a channel is formed in a strained Si film on a SiGe film with a Ge concentration of 30%, the mobility in a vertical electric field of 0.6 MV / cm is low. As can be seen, the nMOS transistor shows a 120% improvement in mobility, but the pMOS shows only a 30% improvement. When a CMOS is fabricated using this substrate, the mobility improvement rate is large. Balance will occur. This imbalance requires that when designing an inverter circuit using CMOS, the channel width of the pMOS must be larger than that of the conventional nMOS, and a significant change is required when utilizing conventional design assets. Therefore, it is not preferable.

In order to solve this, it is necessary to improve the mobility of the pMOS to be equal to that of the nMOS. As a method for improving the mobility of pMOS, there is a method of forming a channel in a SiGe film having compressive strain. For example, Non-Patent Document 2 describes that mobility improvement of about 50% was obtained with strained SiGe of Ge 33%. Non-Patent Document 3 describes that mobility is about 70% in an nMOS in which a channel is formed in a Si film having tensile strain on a SiGe film whose strain is relaxed by 20%.
VLSI Symposium 2002 10-4 PMCarone, V. Venkataraman and JCSturn, International Electron devices and Materials, p. 29 (1991) J. Welser, JLHoyt, S. Takagi and JFGibbon International Electron Devices and Materials, p.373 (1994)

  However, it has not been achieved so far to form different substrate structures for nMOS and pMOS with a single substrate to obtain the same degree of mobility improvement.

  The present invention has been made in view of such circumstances, and a semiconductor substrate manufacturing method suitable for high-speed CMOS manufacturing by simultaneously realizing a strained Si film and a strained SiGe film on one substrate, and the substrate. A semiconductor device using the above is provided.

In this invention, (a) a SiGe film is formed on a substrate whose surface is made of silicon, (b) a Si film is formed on the SiGe film, (c) Ge ions and H ₂ ions are implanted into the nMOS formation region, (D) Provided is a manufacturing method of a method for manufacturing a semiconductor substrate comprising steps of relaxing strain of the SiGe film in the region by heat treatment.

According to the present invention, when the high-speed MOSFET is formed, the imbalance of the mobility improvement rate with respect to the CMOS can be eliminated. In other words, even if an nMOS-pMOS transistor is formed on one Si substrate, the mobility can be matched with each other.
In addition, when this semiconductor substrate manufacturing method is used, the conventional design assets can be effectively utilized when designing using a strained Si film.

In the method of manufacturing a semiconductor substrate according to the present invention, (a) a SiGe film is formed on a substrate whose surface is made of silicon, (b) a Si film is formed on the SiGe film, and (c) Ge ions and H are formed in an nMOS formation region. ₂ ions are implanted, and (d) distortion of the SiGe film in the region is relaxed by heat treatment.
Here, the substrate whose surface is made of silicon is a so-called SOI, SOS substrate or the like having a single crystal silicon substrate or a single crystal silicon layer on the surface.
In this invention, you may make it perform a process (b) continuously after a process (a).
Here, “continuously performed” means that the source gas source is switched in the same apparatus.
Further, the step (b) may be performed after the steps (a), (c) and (d) are sequentially performed.
In this invention, the SiGe film in the step (a) is formed so that the Ge concentration is 10 to 50% and the film thickness is 10 to 50 nm, and the Si film in the step (b) is 5 to It is preferable to be formed to be 50 nm.

  In the present invention, the heat treatment in the step (d) is preferably performed at a temperature of 600 ° C. or higher and 1000 ° C. or lower.

In the manufacturing method, the Ge ion implantation in the step (c) may be performed at least twice.
In the above manufacturing method, the hydrogen ion implantation in the step (c) is preferably set such that the implantation peak is deeper than the maximum implantation peak of Ge.

  Further, in the above manufacturing method, the step (c) further includes a separation step of separating the pMOS transistor formation region and the nMOS transistor formation region, and the separation step may be performed after the completion of the steps (a) and (b). Good.

  Furthermore, the method of manufacturing a semiconductor device according to the present invention uses the semiconductor substrate manufactured by the above method, forms a gate oxide film and a gate electrode on the Si film, which is the uppermost semiconductor film, and masks the gate electrode A MOS transistor is formed by forming a source and a drain, a pMOS transistor is formed in a region having a strained SiGe film, and an nMOS transistor is formed in a region having a strained SiGe film. To do.

  Also, in the method of manufacturing a semiconductor device according to the present invention, a SiGe film is formed on a Si substrate having first and second regions for forming pMOS and nMOS transistors, respectively, and the Si film is continuously formed on the SiGe film. Forming and separating the first and second regions, implanting n-type ions into the first region, implanting Ge ions, hydrogen ions, and P-type ions into the second region; The strain is relaxed only in the SiGe film in the second region, the n well and the P well are formed in the first and second regions, respectively, the pMOS transistor is formed in the first region, and the nMOS transistor is formed in the second region. It is characterized by doing.

Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings. This does not limit the invention. In the following,% representing concentration is atom%.
First Embodiment An embodiment of a semiconductor substrate manufacturing method according to the present invention will be described below with reference to FIG.
[A] Formation of SiGe Film and Si Film As shown in FIG. 1A, the oxide film on the normal Si substrate 1 having a (100) surface is removed using a known diluted HF solution. Thereafter, using a known CVD method, the SiH ₄ / GeH ₄ / H ₂ gas atmosphere, 400 to 800 ° C., and the flow rate ratio of GeH ₄ are adjusted. Thereby, a thin SiGe film 2 having a Ge concentration of 10 to 50% and a film thickness of 5 to 50 nm is epitaxially grown.
Thereafter, a thin Si film (hereinafter referred to as a cap Si film) 3 having a thickness of 5 to 50 nm is grown in a SiH ₄ / H ₂ gas atmosphere at 400 to 900 ° C. in the same apparatus. That is, the SiGe film 2 is formed while being lattice-matched to the surface of the Si substrate 1, and the cap Si film 3 is formed while being lattice-matched on the SiGe film 2.

In this case, it is necessary to pay attention to the following points.
(1) Since the growth of the SiGe film 2 is greatly influenced by the surface state of the Si substrate 1, first, heat treatment (annealing) is performed at 800 to 1000 ° C. with only H ₂ gas to reduce the natural SiO ₂ film on the surface. After removal and hydrogen termination of Si dangling bonds, using the well-known CVD (Chemical Vapor Deposition) method, the Si film is formed at 800-1000 ° C in a SiH ₄ / H ₂ gas atmosphere. It is desirable to epitaxially grow the surface of the Si substrate 1 as a buffer layer.

(2) Thereafter, the SiGe film 2 is epitaxially grown by flowing SiH ₄ / GeH ₄ / H ₂ gas continuously in the same reaction chamber without opening to the atmosphere. At this time, since the Si film grown as the buffer layer is not released to the atmosphere, the surface is basically free of oxygen and other contamination, so that the SiGe film 2 with few defects can be grown.

  (3) The crystal structure of the SiGe film 2 grown on the Si film as the buffer layer is the same diamond structure as Si, but the lattice constant increases as the Ge concentration increases because the ionic radius of Ge is approximately 30% larger than that of Si. The horizontal growth is aligned with the lattice spacing of the Si film, and the epitaxial growth proceeds with a shrinkage strain in the horizontal direction.

(4) As the growth film thickness increases, the strain energy of the SiGe film 2 increases, and when it exceeds the energy at which dislocations are generated for strain relaxation, dislocations are formed at the SiGe / Si interface and strain relaxation of the SiGe film 2 occurs. . Since the energy for generating the dislocation is smaller as the temperature is higher, it is necessary to grow at the lowest possible temperature in order to prevent the occurrence of defects.
However, if the temperature is lowered to 400 ° C. or lower, the growth rate rapidly decreases and it becomes difficult to grow in a realistic time. Therefore, the temperature is set in consideration of the growth rate. In a hot-wall type CVD system, the growth of 20% SiGe is about several nm / min at 550 ° C, and it takes about several hours to grow a 300 nm film. Absent. For example, if the deposit temperature is 450 ° C., it takes about one digit longer to deposit a thickness of 300 nm.
If the growth temperature is lowered, the critical film thickness can be increased, but with 20% SiGe, when the growth temperature is 550 ° C., the film thickness is 300 nm, and a device having a thickness of 300 nm necessary for the device can be formed.
Further, in order to prevent dislocation from occurring in the strained SiGe film 2 by a heat treatment at about 950 ° C. in a normal CMOS process, the film thickness needs to be about 10 nm or less for 30% SiGe.

  As described above, in this embodiment, as shown in FIG. 1A, first, for example, a SiGe film 2 having a Ge concentration of 30% and a thickness of 10 nm is formed on the entire surface of the Si substrate 1 necessary for forming the pMOS. For example, a cap Si film 3 having a thickness of 10 nm is formed, for example.

[B] Ion Implantation Next, a method of forming the strain relaxation SiGe layer 5 which becomes the virtual substrate portion of the nMOS will be described with reference to FIG. First, using the resist 4 formed on the right half using a known photolithography technique as a mask, using a known ion implantation technique, Ge ions and hydrogen ions are applied to the nMOS region on the left half as shown in FIG. Then, a SiGe layer 5 is formed under the SiGe film 2.

  The implantation of Ge ions is to form a SiGe virtual substrate for nMOS. In order to improve the mobility of nMOS by 50% or more compared to that manufactured with a normal Si substrate, the effective concentration of Ge needs to be 15% or more.

In the ion implantation profile, two or more implantations are performed in order to make the strained Ge concentration almost a rectangular distribution. FIG. 2 shows Ge concentration distributions C1 to C4 when Ge ion implantation is carried out 1 to 4 times. Implantation energy / injection volume used at this time, since the 1st to 4th, respectively ^{50KeV / 1.1E16cm -2, 100KeV / 2E16cm} -2, 170KeV / 3.4E16cm -2, is set to 280KeV / 9.8E16cm ^-2. The implantation energy condition is desirably calculated using the relationship of the following expression in order to approximate a flat distribution.

2nd injection depth = 1st injection depth + standard deviation of 1st injection x 0.8
+ Standard deviation of the second injection x 0.8
Further, the injection amount is set in inverse proportion to the standard deviation of the injection distribution, whereby a total injection distribution Ct that is almost flat can be realized.

  As shown in FIG. 1 (b), in order to perform ion implantation through a cap Si film 3 with a thickness of 10 nm and a SiGe film 2 with a thickness of 10 nm, implantation is performed so that Ge does not enter a depth of 40 nm or less from the surface as much as possible. Although the energy is set, a substantially flat 15% SiGe layer 5 is formed under the SiGe film 2 to a depth of 40 to 200 nm. Thereafter, the Ge concentration gradually decreases, and the SiGe layer 5 is formed to a depth of about 300 nm.

In the hydrogen ion implantation, the peak depth of implantation is set deeper than 200 nm. This depth is the depth at which the total concentration distribution Ct of Ge shown in FIG. 2 begins to decrease. If it is shallower than this, stacking faults generated by hydrogen microvoids reach the surface, and the junction of the MOS transistor as a threading dislocation This is not preferable because it causes problems such as leakage current. The injection amount must be set to 1 x 10 ¹⁶ cm ^-2 or more for microvoid formation, and the hydrogen concentration of the injection peak must be 5 x 10 ²⁰ cm ^-3 or more (atomic concentration is about 1% or more). There is. 3 × 10 ¹⁶ cm ^-2 or more (atomic concentration above about 3%) microvoids grows larger as you, since such peeling of surface abnormalities or SiGe layer is a problem, the injection volume 1 to 3 × 10 ¹⁶ Must be set to cm ^-2 .

[C] Heat treatment After removing the resist 4 in FIG. 1 (b), heat treatment (annealing) at a temperature of about 600 to 1000 ° C., as shown in FIG. 1 (c), near the hydrogen injection peak. The stacking faults, that is, the transition loops 7 extending from the microvoids 6 of hydrogen generated in the metal, reach the interface between the strained SiGe layer 5 formed by the Ge ion implantation and the Si substrate 1, and further miss in the direction parallel to the interface. Generate a fit dislocation. By generating this misfit dislocation, the distortion of the SiGe film 2 and the SiGe layer 5 is alleviated. At this time, tensile strain occurs in the cap Si film 3 on the SiGe film 2 whose strain has been relaxed, and the mobility increases. In this embodiment, the hydrogen ion implantation peak is set deeper than the SiGe / Si substrate interface, but there is no particular problem as long as it is deeper than the depth at which the Ge concentration distribution Ct shown in FIG. 2 starts to decrease.

In this state, the SiGe film 2 in the nMOS region is strain-reduced, and tensile strain is generated in the cap Si film 3 thereon. Therefore, it is necessary to set the SiGe film 2 below the critical film thickness for strain relaxation.
In this example, when the Ge concentration is 20%, the upper limit of the film thickness is 15 nm. Thereafter, a MOS transistor is formed on this substrate by using a known CMOS manufacturing technique.

Second Embodiment Another embodiment of the semiconductor substrate manufacturing method of the present invention will be described below with reference to FIG.
[A] Formation of SiGe film As shown in FIG. 3A, a thin SiGe film 2 having a Ge concentration of 10 to 50% and a film thickness of 5 to 50 nm is formed on a normal Si substrate 1 having a (100) surface. Epitaxially grow. That is, the SiGe film 2 is formed while being lattice-matched to the surface of the Si substrate 1. The detailed method is the same as that of the first embodiment.

[B] Ion Implantation Next, as shown in FIG. 3B, using the resist 4 as a mask, Ge ions and hydrogen ions are implanted into the Si substrate 1 to form a SiGe layer 5.
The method of implanting Ge ions and hydrogen ions is the same as in the first embodiment.

[C] Heat treatment and formation of cap Si film After the resist 4 in FIG. 3 (b) is peeled off, it is annealed at a temperature of about 600 to 1000 ° C., and then continuously SiH ₄ / H in the same apparatus. _The cap Si film 3 is grown at 400 to 900 ° C. in a gas atmosphere. That is, the Si film 3 is formed on the SiGe film 2 while being lattice-matched. Then, by this annealing, as shown in FIG. 3 (c), the stacking fault 7 extending from the hydrogen microvoid 6 generated in the vicinity of the hydrogen implantation peak is formed by the strained SiGe layer 5 and the Si substrate formed by ion implantation. A misfit dislocation is generated in a direction parallel to the interface. By generating this misfit dislocation, the distortion of the SiGe film 2 and the SiGe layer 5 is alleviated. At this time, tensile strain occurs in the Si film 3 on the SiGe film 2 whose strain has been relaxed, and the mobility increases.

  In this embodiment, the hydrogen ion implantation peak is set deeper than the SiGe / Si substrate interface, but there is no particular problem as long as it is deeper than the depth at which the Ge concentration distribution Ct shown in FIG. 2 starts to decrease.

In this state, the SiGe film 2 in the nMOS region relaxes the strain, and the Si film 3 on the SiGe film 2 has a tensile strain. When the Ge concentration is 20%, the upper limit of the film thickness is 15 nm. Thereafter, a MOS transistor is formed on this substrate by using a known CMOS manufacturing technique.
Compared to the first embodiment, since the cap Si film 3 serving as an nMOS channel is formed after the Ge ion implantation, the cap Si film 3 is not damaged by the implantation.

Third Embodiment Next, an embodiment of a semiconductor device manufacturing method according to the present invention will be described with reference to FIG.
First, as shown in FIG. 4 (a), the SiGe film 2 having a Ge concentration of 10 to 50% and a film thickness of 5 to 50 nm and a film thickness of 5 to 50 nm are formed on the Si substrate 1 by the same method as in the first embodiment. The cap Si film 3 is continuously formed.

After that, without exposing to the atmosphere, SiH ₄ / GeH ₄ / H ₂ gas is allowed to flow continuously in the same reaction chamber to epitaxially grow the SiGe film 2, and further continuously in the same reaction chamber, the SiH ₄ / H ₂ gas atmosphere The cap Si film 3 is epitaxially grown on the SiGe film 2 at 800 to 1000 ° C. Thereafter, a trench 10 embedded with SiO ₂ for trench element isolation is formed using a known element isolation technique.

Next, as shown in FIG. 4 (b), using the photoresist 11 having an opening in the pMOS transistor formation region as a mask, phosphorous ion implantation is performed with a known ion implantation technique, with respect to implantation energy / injection amount, 600 KeV / 1 × 10 ¹³ cm ^-2 , 320 KeV / 7 x 10 ¹² cm ^-2 , 150 KeV / 5 x 10 ¹² cm ^-2 and 60 KeV / 2 x 10 ¹² cm ^-2 for a total of 4 times, concentration in Si substrate 1b An N-type region (N well) 12 of 3 × 10 ¹⁷ cm ⁻³ is formed.

Thereafter, as shown in FIG. 4 (c), Ge ion implantation is performed with a known ion implantation technique using a photoresist 13 having an nMOS transistor formation region opened as a mask, with an implantation energy / injection amount of 50 KeV / 1.1. ^{E16cm -2, 100KeV / 2E16cm -2 170KeV} / 3.4E16cm -2, 280KeV / 9.8E16cm the SiGe layer 15 is formed under performs the SiGe film 2 four times in the ^condition-2, further 20 KeV / 2E16 cm hydrogen ions ^{- Once at 2} conditions, boron ions are 300KeV / 1 × 10 ¹³ cm ^-2 , 150 KeV / 7 × 10 ¹² cm ^-2 , 60 KeV / 5 × 10 ¹² cm ^-2 and 20/2 × 10 ¹² cm ^-2 Under conditions, a total of four times is implanted in the SiGe / Si substrate to form a P-type high concentration region (P well) 14.

  Thereafter, annealing is performed at 600 to 1000 ° C. to form a minute hydrogen precipitate 16 in the P well 14 as shown in FIG. 4 (d), and a dislocation loop 17 is generated therefrom. This forms misfit dislocations in the tilted Ge distribution region, and the distortion of the SiGe film 2 and the SiGe layer 15 is alleviated. At this time, the dislocation loop 17 forms misfit dislocations in the inclined distribution region and can easily stop, so in order to completely relieve the distortion of the SiGe layer 15 in the rectangular distribution region, the dislocation loop 17 has a rectangular distribution as much as possible. It is desirable to set the implantation energy so as to have a peak at a close portion.

Thereafter, a MOS transistor is formed using a known CMOS process. First, after forming a gate oxide film 19 having a thickness of 2 to 20 nm, a poly Si film having a thickness of about 200 nm is grown, and the gate electrode 20 of the MOS transistor is processed by an anisotropic reactive etching method. Thereafter, BF2 + ions are implanted with a resist mask having an opening in the pMOS region under conditions of an implantation energy of 40 KeV and an implantation amount of 3 × 10 ¹⁵ cm ⁻² . In addition, arsenic ions are implanted under the conditions of an implantation energy of 40 KeV and an implantation amount of 3 × 10 ¹⁵ cm ⁻² using a resist mask having an nMOS region opened. After removing the resist, annealing is performed at about 900 ° C., and the source / drain P + diffusion layer 21 and N + diffusion layer 20 are formed, thereby forming the strained Si film 3 as a channel as shown in FIG. A surface channel nMOS transistor 31 and a buried channel pMOS transistor 32 having the strained SiGe film 2 as a channel are formed.

Fourth Embodiment Another embodiment of the semiconductor device manufacturing method according to the present invention will be described below with reference to FIG.
First, as shown in FIG. 5 (a), the substrate shown in FIG. 1 (c) or FIG. 3 (c) is manufactured according to the first or second embodiment, and trench element isolation is performed using a known element isolation technique. A groove 10 embedded with SiO ₂ as a member is formed.

Next, as shown in FIG. 5 (b), using the photoresist 11 having an opening in the pMOS region as a mask, phosphorus ions are implanted with a known ion implantation technique at an implantation energy / implantation amount of 600 KeV / 1 × 10 ^13. cm- ² , 320 KeV / 7 × 10 ¹² cm ^-2 , 150 KeV / 5 × 10 ¹² cm-2 and 60 KeV / 2 × 10 ¹² cm-2, 4 times in total, concentration in Si substrate 1 about 3 × 10 ¹⁷ An N-type region (N well) 12 of cm ⁻³ is formed.

Thereafter, as shown in FIG. 5 (c), with the photoresist 13 in which the nMOS region is opened as a mask, boron ions are implanted at 300 KeV / 1 × 10 with respect to implantation energy / injection amount by a known ion implantation technique. ^{13 cm -2, 150KeV / 7 ×} 10 12 cm -2, 60KeV / 5 × 10 12 cm -2 and 20/2 × 10 ¹² cm under conditions of ^-2 four times SiGe / Si substrate implanted P-type in the A high concentration region (P well) 14 is formed.
Thereafter, a MOS transistor is formed using a known CMOS process. As shown in FIG. 5 (d), first, a gate oxide film 19 having a thickness of 2 to 20 nm is formed, and then a poly-Si 20 film having a thickness of about 200 nm is grown, and the gate of the MOS transistor is subjected to anisotropic reactive etching. The electrode 20 is processed. Thereafter, BF2 + ions are implanted with an implantation energy of 40 KeV and an implantation amount of 3 × 10 ¹⁵ cm ⁻² through a resist mask having an opening in the pMOS region. Also, arsenic ions are implanted with a resist mask with an nMOS region opened at an implantation energy of 40 KeV and an implantation amount of 3 × 10 ¹⁵ cm ⁻² , and after removing the resist, annealing is performed at about 900 ° C. to form a source / drain P + diffusion layer By forming 21 and the N + diffusion layer 22, a surface channel type nMOS transistor 31 having the strained Si film 3 as a channel and a buried channel type pMOS transistor 32 having the strained SiGe film 2 as a channel are formed.

It is process drawing explaining an example of the manufacturing method of the semiconductor substrate of this invention. It is explanatory drawing for demonstrating distribution of the depth direction of Ge ion implantation in this invention. It is process drawing explaining the other example of the manufacturing method of the semiconductor substrate of implementation of this invention. It is process drawing which shows an example of the manufacturing method of the semiconductor device of this invention. It is process drawing which shows the other example of the manufacturing method of the semiconductor device of this invention.

Explanation of symbols

1 Si substrate
2 Strained SiGe film
3 Cap Si film
4 Photoresist
SiGe layer formed by 5 Ge ion implantation
6 Fine hydrogen precipitate
7 Dislocation loop
10 Embedded SiO ₂ for device isolation
11 Resist mask for n-well formation
12 n well
Resist mask for p-well formation
14 p well
Strained SiGe layer formed by 15 Ge ion implantation
16 Fine hydrogen precipitate
17 Dislocation loop
19 Gate SiO ₂
20 Gate poly-Si electrode
21 P + source / drain diffusion layer
22 N + source / drain diffusion layer

Claims (11)

(A) forming a SiGe film on a substrate whose surface is made of silicon;
(B) A Si film is formed on the SiGe film,
(C) Implanting Ge ions and H ₂ ions into the nMOS formation region,
(D) Relieve distortion of the SiGe film in the region by heat treatment,
A method of manufacturing a semiconductor substrate comprising steps.   The method of manufacturing a semiconductor substrate according to claim 1, wherein the step (b) is continuously performed following the step (a), and then the steps (c) and (d) are sequentially performed.   The method of manufacturing a semiconductor substrate according to claim 1, wherein the step (b) is performed after the steps (a), (c), and (d) are sequentially performed.   The method for manufacturing a semiconductor substrate according to claim 1, wherein the SiGe film in the step (a) has a Ge concentration of 10 to 50 atom% and a film thickness of 10 to 50 nm.   The method of manufacturing a semiconductor substrate according to claim 1, wherein the Si film in the step (b) has a thickness of 5 to 50 nm.   The manufacturing method of the semiconductor substrate as described in any one of Claims 1-3 with which the heat processing of a process (d) is performed at the temperature of 600-1000 degreeC.   The method of manufacturing a semiconductor substrate according to claim 1, wherein in the step (c), Ge ions are implanted twice or more.   4. The method of manufacturing a semiconductor substrate according to claim 1, wherein in the step (c), the hydrogen ion implantation peak is set deeper than the Ge maximum implantation peak.   3. The method of manufacturing a semiconductor substrate according to claim 2, further comprising a separation step of separating the substrate into a pMOS transistor formation region and an nMOS transistor formation region, wherein the separation step is performed after steps (a) and (b).   Using the semiconductor substrate manufactured by the method according to any one of claims 1 to 3, a gate oxide film and a gate electrode are formed on a Si film that is the uppermost semiconductor film, and the gate electrode is used as a mask. Forming a MOS transistor by forming a source and a drain, forming a pMOS transistor in a region having a strained SiGe film, and forming an nMOS transistor in a region having a strained SiGe film. A method for manufacturing a semiconductor device. A SiGe film is formed on a Si substrate having first and second regions for forming pMOS and nMOS transistors, respectively, a Si film is continuously formed on the SiGe film, and the first and second regions are separated. Element isolation is performed, n-type ions are implanted into the first region, Ge ions, hydrogen ions, and P-type ions are implanted into the second region, heat treatment is performed, and only the SiGe film in the second region is strain-relaxed. In addition, a method of manufacturing a semiconductor device is characterized in that an n well and a P well are formed in the first and second regions, respectively, a pMOS transistor is formed in the first region, and an nMOS transistor is formed in the second region.

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