JP2008004910A - Manufacturing method of strain multi-gate transistor and device obtained therefrom - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the mobility in a multi-gate device by introducing strain to the multi-gate device, thereby controlling and alleviating this strain for NMOS or PMOS. <P>SOLUTION: There is provided a method of alleviating strain in a multi-gate device, including the steps of: providing a substrate including a strain material; patterning a plurality of fins in the strain material; defining a first area including at least one fin; defining a second area including at least one fin; forming a diffusion barrier layer on a first area; and performing hydrogen annealing so as to alleviate the strain material of at least one fin of the second area. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention generally relates to improving the performance of semiconductor devices such as multi-gate devices.

  In particular, the present invention relates to a method for improving mobility in these multi-gate devices.

  Miniaturization of silicon MOS semiconductor devices is a major challenge in the semiconductor industry. In the early days, device geometric reductions have provided many improvements in integrated circuit (IC) manufacturing, while today's new technologies, methods, and materials are introduced beyond the 90 nm technology node. There is a need.

  One major problem in miniaturizing conventional planar devices is the short channel effect that begins to dominate device performance. The solution to this problem comes from multi-gate field effect transistors (MUGFETs). Due to its three-dimensional structure with the gate covered around thin silicon fins, improved gate control over the channel (and thus less short channel effect) could be achieved by using multi-gates.

  However, the introduction of this new device structure has created new problems. One problem is carrier mobility in the device. Due to the different crystal orientations on the top and side surfaces of the fin, there is a difference in mobility for electrons and holes. When using a standard (100) wafer surface with <110> notches, the mobility of electrons in the nMOS MUGFET is sufficiently disturbed by the undesirable sidewall surface crystallographic orientation. The greatest contribution comes from those sidewall surfaces that have an orientation / orientation of (100) / <110>, which is the worst for electron mobility. The orientation / azimuth of (100) / <110> on the top surface of an nMOS MUGFET, however, is very useful for electron mobility. However, the opposite phenomenon occurs for pMOS MUGFETs. If the (100) / <110> orientation / azimuth on the sidewall is very useful for hole mobility, the (100) / <110> orientation / azimuth on the top surface is not preferred.

  Different possibilities have been proposed to improve mobility in both nMOS and pMOS MUGFETs, following the same principle. That is, in order to improve the mobility of both electrons and holes, strain is introduced. In order to solve these problems, it is necessary to bear in mind that the semiconductor material of the fin has a crystal orientation-dependent sensitivity of charge mobility to stress. For nMOS devices on a standard (100) / <110> substrate, parallel tensile stress along the channel and compressive stress perpendicular to the wafer surface are useful. Contrary to pMOS devices, parallel compressive stress along the channel and tensile stress perpendicular to the wafer surface are useful.

  Distortion can be introduced into the channel in two ways. Biaxial global strain or uniaxial local strain.

  The former is 31.7 of J. Wesler et al., “NMOS and PMOS Transistors Fabricated in Strained Silicon / Relaxed Silicon-Germanium Structures”, Electron Devices Meeting, 1992 Technical Digest (December 13, 1992), also called substrate-induced strain. As explained on pages .1 to 31.7.3, the conventionally known biaxial total strain is the introduction of a tilted silicon germanium (SiGe) substrate having a strained silicon (Si) surface layer. Since the lattice constant of relaxed SiGe is higher than that of relaxed Si, the Si lattice becomes aligned with the SiGe lattice, and as a result, a biaxial tensile strain is applied to the Si surface layer, which is formed in this strained Si layer. This also applies to the channel region. Due to biaxial strain, this technology is useful in both pMOS and nMOS devices. However, the disadvantage is the performance degradation due to the shorter gate length.

  Another possibility for biaxial overall strain is the use of strained silicon (SSOI) on an insulating substrate. This is the result of E. Augendre et al. "On the scalability of source / drain current enhancement in thin film sSOI", Proceedings of 35th European Solid-State Device Research Conference 2005 (ESSDERC 2005, September 12-16, 2005), 301. From page to page 304. By using a strained silicon-on-insulator (SSOI) substrate, the advantages of using an SOI substrate (improved insulation, reduced parasitic capacitance) and the advantages of using strained silicon (increased mobility) Combined. However, in this case, only the nMOS device shows better performance.

  Another possibility is the use of silicon germanium (SGOI) on an insulating substrate. This is because T. Irisawa et al., “High current drive uniaxially-strained SGOI for pMOSFETs fabricated by lateral strain relaxation technique”, Symposium of VLSI Technology Digest of Technical Papers 2005 (June 14-16, 2006), 178-179. It is shown on the page. SGOI substrates combine the advantages of using SOI substrates (improved insulation, reduced parasitic capacitance) and the advantages of using SiGe technology (increased mobility). However, in this case, only the pMOS device shows better performance.

  Different approaches are explored when uniaxial local strain is introduced.

  One approach is to introduce a stress liner on top of the MUGFET. This is described in Collaert et al., "Performance improvement of tall triple gate devices with strained SiN layers", Electron Devices Letters IEEE (November 2005), Volume 26, Issue 11, pages 820-82.

  By forming a contact etch stop silicon nitride layer (CESL) over the transistor, strain can be introduced into the channel region. In the case of pMOS, the tension layer and the compression layer exhibit improved device characteristics. On the other hand, in the case of nMOS, only the tensile layer provides high performance. In the dual CESL approach, both types of stress are introduced into the CMOS device. The main disadvantage of this technique lies in the additional process steps required to deposit both compressive and tensile CESL.

The second approach is to introduce recessed strained SiGe into the source and drain regions of the MUGFET device. This is the result of P. Verheyen et al. "25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si _0.8 Ge _0.2 in the source and drain regions", Symposium of VLSI Technology Digest of Technical Papers. 2005 (June 14-16, 2006), pages 194-195. A recess is formed by etching the silicon substrate, and selectively grown SiGe is formed in the recess. The larger lattice constant of SiGe compared to Si places the channel region between the source / drain regions under uniaxial compressive stress, which is only useful for pMOS devices.

  The main drawback of all the proposed methods found in the prior art is that in many cases only the mobility of majority carriers (eg electrons in n-type MUGFET transistors when the stress source is SSOI) is high. On the other hand, the mobility of other minority carriers (eg, holes in an n-type MUGFET transistor when the stress source is SSOI) remains equal or lower. Therefore, there is still a need for a method that can simultaneously increase the mobility for both NMOS and PMOS.

A second drawback of all proposed methods found in the prior art is a solution to increase the strain in NMOS or PMOS by introducing strain (further strain) by means of a stress source A measure is required. For this reason, there is a need for a method that selectively reduces strain in a distorted material in a controlled manner.
J. Wesler et al. "NMOS and PMOS Transistors Fabricated in Strained Silicon / Relaxed Silicon-Germanium Structures", Electron Devices Meeting, 1992 Technical Digest (Dec. 13, 1992) pp. 31.7.1-31.7.3

  One object of embodiments of the present invention is a method of increasing mobility in a multi-gate device by introducing strain into the multi-gate device and mitigating this strain in a controlled manner for NMOS or PMOS. Is to introduce.

  In one form, a method for mitigating strain in a multi-gate device is described. Such a method includes providing a substrate having a strained material, patterning a plurality of fins in the strained material, defining a first region including at least one fin, and a first including at least one fin. A step of defining two regions, a step of forming a diffusion barrier layer on the first region, and a step of performing hydrogen annealing so that the strain material of at least one fin in the second region is relaxed.

  The diffusion barrier layer of the present invention may contain a nitride. Alternatively, the diffusion barrier layer may be a contact etch stop layer (CESL). This contact etch stop layer may be tensile strain or compressive strain.

  The thickness of the diffusion barrier layer generally depends on the annealing parameters of hydrogen annealing. The annealing parameters for hydrogen annealing are preferably selected from, for example, temperature, pressure, concentration, and time. The thickness of the diffusion barrier layer is preferably in the range of 5 nm to 50 nm.

  In a specific example, the thickness of the diffusion barrier layer is selected so that hydrogen does not pass through the diffusion barrier layer. The strained material is not affected by hydrogen annealing. The strain material of the at least one fin in the first region remains unchanged after the hydrogen annealing step.

  In other embodiments, the thickness of the diffusion barrier layer is selected so that the strained material is partially relaxed by hydrogen annealing. After the hydrogen annealing step, the strained material in the at least one fin of the first region is partially relaxed.

  A method for relieving strain in a multi-gate device is based on a hydrogen annealing process. The hydrogen annealing step is preferably performed at 900 ° C. or lower. In one embodiment, the most preferred temperature for hydrogen annealing also depends on the thickness of the diffusion barrier layer.

  The hydrogen annealing step is preferably performed in a time within a range of 1 minute to 5 minutes. In one embodiment, the most preferred time for hydrogen annealing also depends on the thickness of the diffusion barrier layer.

  In other embodiments, the substrate of the present invention includes a strained material, which includes strained silicon. The strained material may also be SiGe.

  In one specific example, the substrate is an SSOI substrate. In other embodiments, the substrate is an SGOI substrate.

  In one specific example, the first region is an NMOS region and the second region is a PMOS region. In this specific example, the strain in the PMOS region is relaxed by the hydrogen annealing process.

  In another specific example, the first region is a PMOS region and the second region is an NMOS region. In this specific example, the distortion of the NMOS region is alleviated by the hydrogen annealing step.

  One or more embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited thereto. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements are expanded for illustrative purposes and are not described in actual sizes. Those skilled in the art will be aware of many variations and modifications of this invention that are encompassed by its scope. Thus, the following description of certain inventive embodiments should not be considered as limiting the scope of the invention.

  Furthermore, the terms first, second, etc. in the specification and claims are used to distinguish between similar elements and need not represent a continuous or time sequence. This term is used interchangeably under appropriate circumstances, and the embodiments of the invention described herein can be used in an order different from that described and represented herein. Should be understood.

  The term “comprising”, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. . Thus, the range of the expression “a device including the A means and the B means” should not be limited to a device including only the A component and the B component. In the context of the present invention, the meaningful components of the device mean A and B.

  The term “diffusion barrier layer” referred to in this application is used to define a layer that completely or partially blocks hydrogen during the hydrogen annealing step. If the diffusion barrier layer completely blocks hydrogen, hydrogen cannot diffuse through this diffusion barrier layer. This means that the underlying material (disposed below the diffusion barrier layer and separated from the hydrogen environment by the diffusion barrier layer) is not affected by hydrogen. If the diffusion barrier layer partially blocks hydrogen, the hydrogen can partially diffuse through the diffusion barrier layer. This means that the underlying material (disposed below the diffusion barrier layer and separated from the hydrogen environment by the diffusion barrier layer) is affected by hydrogen.

  A planar field effect transistor comprises a channel in the plane of the wafer surface and a gate disposed on the wafer surface in the same plane as the channel. The present invention relates to multi-gate field effect transistors (MUGFETs). In order to produce a multi-gate field effect transistor, a semiconductor material (eg, Si, SiGe) is patterned to form a fin-shaped body. Because of this fin-shaped body, multi-gate devices are often referred to as finfet devices. The fins are raised on the wafer / substrate surface. A fin is defined by its width (W), height (H), and length (L) and includes a top surface, a bottom surface, and two sidewall surfaces. The gate electrode is wrapped around the fin channel region. A multi-gate field effect transistor can be defined depending on the shape of the gate electrode. A double-gate fin FET is a multi-gate device where the gate controls only the conductivity of the two sidewall surfaces of the fin. Such a device is also called a double gate device. An omega gate fin FET (Ω gate fin FET) is a multi-gate device where the gate controls the conductivity of the two sidewall surfaces and the top surface of the fin. A U-gate fin FET is a multi-gate device where the gate controls the conductivity of the two sidewall surfaces and the bottom surface of the fin. A circular gate fin FET is a multi-gate device where the gate controls the conductivity of the two sidewall surfaces of the fin, the top surface of the phone, and the bottom surface of the fin.

A MUGFET can be fabricated on a silicon-on-insulator substrate (SOI). The SOI substrate can be manufactured by different methods such as separation by implanted oxygen (IMOX) and wafer bonding. To introduce distortion to the substrate, it may be used strained silicon-on-insulator substrate (SSOI) or relaxed _{Si 1-X} Ga X · on-insulator (SGOI).

The strained silicon-on-insulator substrate (SSOI) has the advantages of using a silicon-on-insulator substrate (SOI) (improved insulation and reduced parasitic capacitance) and the advantages of using a strained substrate (SOI) ( (Increased mobility). The insulating layer is formed between the strained silicon layer and the bulk substrate. The substrate may be made of silicon, for example. The strained silicon layer has a thickness in the range of 10 nm to 50 nm, for example. The insulating layer is generally SiO ₂ having a thickness of, for example, 130 nm.

Use relaxed _{Si 1-X} Ga X · on-insulator (SGOI) substrate, the advantages of using a silicon-on-insulator substrate (SOI) and (improved insulation, reduction in parasitic capacitance), the SiGe technology Together with the advantages (increased mobility). The insulating layer is formed between the Si _1-X Ga _X layer and the bulk silicon substrate. The relaxed Si _1-X Ga _X layer has a thickness in the range of, for example, 10 nm to 50 nm. The insulating layer is generally SiO ₂ having a thickness of, for example, 130 nm. Furthermore, a silicon layer may be crystal-grown on the SGOI substrate. Due to the lattice constant mismatch between Si and SiGe, the silicon layer is under tensile strain. Further, the strained SiGe layer may be crystal-grown on the SGOI substrate.

  The present invention provides a method for controlling and mitigating strain in a multi-gate device. After patterning the fins in the strained material of the substrate, a first region and a second region are defined, each including at least one fin. In the next step, a diffusion barrier layer is deposited on the first region and a hydrogen anneal is performed to relieve strain in the strained material in the second region that is not covered by the diffusion barrier layer.

  Each step of the present invention is described in more detail with reference to FIG.

  The starting material is a substrate 100 comprising a bulk layer 101, an insulating layer 102, and a strained material 103 (FIG. 1a). The strained material is preferably selected from strained Si or strained SiGe. The substrate may be, for example, an SSOI substrate, an SGOI substrate having a strained Si surface layer, or a tilted SiGe substrate having a strained Si surface layer. Alternatively, a substrate with a rotated notch may be used to further increase mobility in the device.

  A plurality of fins 103 are patterned in the strained substrate using a photolithography process or a spacer technique for patterning defined fin spacers (FIG. 1b). At least two fins need to be patterned. In this regard, all fins include strained material 103. The width and height of the fin depends on the technology node. The width of the fin may be within a range of 10 nm to 50 nm, for example. The height of the fin may be in the range of 10 nm to 60 nm, for example. For example, for a 32 nm technology node, the fin width is 10 nm to 20 nm and the fin height is about 60 nm.

  In the next step (FIG. 1c), the first region 103a is defined to include at least one fin, and the second region 103b is defined to include at least another fin. After this step of defining the first region 103a and the second region 103b, all the fins in the first region and the second region contain strained material.

  In the next step, a diffusion barrier layer 104 is provided at least over the patterned fins on the first region 103a (FIG. 1c). The diffusion barrier layer may contain nitride. Deposition is performed by CVD, such as LP-CVD, plasma enhanced CVD, or other known deposition techniques. The thickness of the diffusion barrier layer depends on the hydrogen annealing parameters.

In the next step, hydrogen (H ₂ ) annealing is performed (FIG. 1d). During this H ₂ annealing, the strained material in the at least one fin of the second region 103b that is not covered by the diffusion barrier layer 104 is reflowed to relieve the strain. After hydrogen annealing (FIG. 1f), the strained material in the first region 103 remains distorted, while the strain in the strained material in the second region 105 is relaxed. The thickness of the diffusion barrier layer 104 depends on parameters of the hydrogen annealing process, such as temperature, time, concentration, and pressure. Preferably, the temperature and time of hydrogen annealing are selected so that hydrogen does not affect the strain of the strained material in the at least one fin in the first region 103a covered with the diffusion barrier layer 104. This means that the diffusion barrier region 104 completely blocks hydrogen. Depending on the fin width, hydrogen annealing parameters must be applied to ensure reflow of the strained material. Smaller fin widths require a smaller amount of heat from hydrogen annealing to relax the strained material. Preferably, the hydrogen anneal is 900 ° C. or lower and is performed for a time in the range of 1 to 5 minutes. More preferably, the fin width is between 10 nm and 50 nm and the hydrogen anneal is performed at 900 ° C. for 2 minutes. However, by adjusting the thickness of the diffusion barrier layer, almost hydrogen is blocked by the diffusion barrier layer, and as a result, the general strain in the strained material covered by the diffusion barrier layer is alleviated. Thus, the diffusion barrier layer is used to completely or partially block hydrogen from flowing into the strained material under the diffusion barrier layer, thereby mitigating strain in the strained material. The amount of strain relaxation depends on the hydrogen annealing parameters such as pressure, temperature, concentration, and time.

  In a preferred embodiment, the diffusion barrier layer 104 includes a nitride such as SiN or SiON.

  In another preferred embodiment, the diffusion barrier layer 104 is a contact etch stopper layer (CESL). The CESL layer is compressed or pulled. The CESL layer blocks hydrogen during the hydrogen annealing process. In addition, the CESL layer also introduces more strain into the underlying material. In order to increase the mobility in the nMOS MUGFET, the CESL layer is preferably tensile strain, while in order to increase the mobility in the pMOS MUGFET, the CESL layer is preferably compressive strain.

  In a preferred embodiment, the substrate comprises strained silicon. The substrate is preferably, for example, an SSOI substrate, an SGOI substrate having a strained Si surface layer, or a tilted SiGe substrate having a strained Si surface layer.

  In another preferred embodiment, the substrate comprises silicon germanium. The substrate is preferably an SGOI substrate, for example.

FIG. 2 is a flow diagram illustrating a preferred embodiment of a method for mitigating distortion in a multi-gate device. An SSOI substrate is used as a starting material. This embodiment would be readily applicable to any substrate containing strained silicon by those skilled in the art. A plurality of fins are patterned 201 into a strained silicon layer by using a photolithography process or a spacer technique for patterning spacers that define the fins 201. At least two fins need to be patterned. In the next step, an nMOS region is defined to include at least one fin and a pMOS region is defined 202 to include at least one fin. After this step of defining the nMOS and pMOS regions, both the pMOS and nMOS regions contain strained silicon. Strained silicon is beneficial for the mobility of electrons in at least one fin of the nMOS region, but not for the mobility of holes in the at least one fin of the pMOS region. It is an object of the present invention to mitigate strain in strained silicon in the pMOS region in order to increase the mobility of holes in at least one fin in the pMOS region. In the next step, a SiN layer is deposited 203 on the patterned fins. This may be done by CVD. The thickness of the SiN layer depends on the parameters of the hydrogen annealing process, such as temperature, time, pressure and concentration. A contact etch stop layer may be used instead of the SiN layer. By using a compressed strained contact etch stop layer, more strain is introduced under the at least one fin in the nMOS region. Subsequently, an oxide layer is deposited 204 on the SiN layer. The oxide may be deposited by CVD. The thickness of the oxide layer is preferably in the range between 2 nm and 20 nm. Subsequently, the oxide layer is partially etched using a photoresist etch mask to expose the underlying SiN layer for the pMOS region, while the oxide and SiN layers remain 205 in the nMOS region. The etching step is preferably performed by wet chemical etching, such as is performed in 5% buffer HF. After this step, the photoresist is stripped and the SiN layer on the pMOS region is selectively etched 206. The oxide layer on the nMOS region serves as a hard mask for etching the SiN layer. This etching is preferably performed by wet chemical etching, for example, etching performed in phosphoric acid (H ₃ PO ₄ ) at 150 ° C. After this step, the remaining oxide layer on the nMOS region is removed 207. This step of removing the oxide film is preferably performed by a wet chemical etching step. In the next step, at least one fin of strained silicon in the nMOS region is still covered by the SiN layer, while at least one fin of strained silicon in the pMOS region is exposed. The SiN layer over the at least one fin of strained silicon in the nMOR region is a diffusion barrier layer. In the next step, hydrogen (H ₂ ) annealing is performed 208. During this H ₂ anneal, the silicon in at least one fin in the pMOS region that is not covered by the SiN layer is reflowed to relieve strain. On the other hand, in at least one fin in the nMOS region, the strained silicon still has strain due to the SiN layer covering the at least one fin. Hydrogen does not affect the strain of the silicon covered by the SiN layer that completely blocks hydrogen. In the next step, the SiN layer is etched away 209 toward the insulating layer of the SSOI substrate. By using the method described in the present invention, at least one fin in the nMOS region is formed from the starting strained silicon, while at least one fin in the pMOS region is formed from low strain (relaxed) silicon. It is formed.

FIG. 3 is a flow diagram illustrating another preferred embodiment of a method for mitigating distortion in a multi-gate device. An SGOI substrate is used as a starting material. This embodiment will be readily applicable to those skilled in the art for any substrate comprising strained SiGe. A plurality of fins are patterned 301 into strained SiGe by using a photolithographic process or spacer technology that patterns the spacers that define the fins. At least two fins need to be patterned. In the next step, an nMOS region is defined to include at least one fin, and a pMOS region is defined 302 to include at least one fin. After this step of defining the nMOS and pMOS regions, both the pMOS and nMOS regions contain strained SiGe. Strained SiGe is beneficial for the mobility of holes in at least one fin in the pMOS region, but not for the mobility of electrons in at least one fin in the nMOS region. It is an object of the present invention to mitigate strain in strained SiGe in the nMOS region in order to increase the mobility of electrons in at least one fin in the nMOS region. In the next step, a SiN layer is deposited 303 over the patterned fins. This may be done by CVD. The thickness of the SiN layer depends on parameters of the hydrogen annealing process, such as temperature, time, concentration, and pressure. A contact etch stop layer may be used instead of the SiN layer. By using a strained strain contact etch stop layer, more strain is introduced below the at least one fin in the pMOS region. Subsequently, an oxide layer is deposited 304 over the SiN layer. The oxide may be deposited by CVD. The thickness of the oxide layer is preferably in the range between 2 nm and 20 nm. Subsequently, the oxide layer is partially etched using a photoresist etch mask to expose the underlying SiN layer for the nMOS region while the oxide and SiN layers remain 305 in the pMOS region. The etching step is preferably performed by wet chemical etching, such as is performed in 5% buffer HF. After this step, the photoresist is stripped and the SiN layer on the pMOS region is selectively etched 306. The oxide layer on the pMOS region serves as a hard mask for etching the SiN layer. This etching is preferably performed by wet chemical etching, such as performed in phosphoric acid (H ₃ PO ₄ ) at 150 ° C., for example. After this step, the remaining oxide layer on the pMOS region is removed 307. This step of removing the oxide film is preferably performed by a wet chemical etching step. In the next step, at least one fin of strained SiGe in the pMOS region is still covered by the SiN layer, while at least one fin of strained SiGe in the nMOS region is exposed. In the next step, hydrogen (H ₂ ) annealing is performed 308. During this H ₂ annealing, the SiGe in the at least one fin in the nMOS region that is not covered with the SiN layer is reflowed to relax the strain. On the other hand, in the at least one fin in the pMOS region, the strained SiGe is still strained by the SiN layer covering the at least one fin. H ₂ does not affect the strain of SiGe covered by a SiN layer that completely blocks hydrogen. In the next step, the SiN layer is etched away 309 toward the insulating layer of the SGOI substrate. By using the method described in the present invention, at least one fin in the pMOS region is formed from the starting strained SiGe, while at least one fin in the nMOS region is made from low strained (relaxed) SiGe. It is formed.

  After using the method of the present invention, multi-gate devices comprising at least one fin in the nMOS region and at least one fin in the pMOS region are known to those skilled in the art, for example, gate oxide deposition, gate patterning Different manufacturing processes such as source / drain extension implantation are performed. Furthermore, in order to increase the mobility of the multi-gate device, those skilled in the art, for example, SiGe source / drain regions, additional CESL layers, can add other stress factors in such subsequent steps. Can be added to the gate device. These stress factors can be applied to the nMOS region or the pMOS region.

  The method of the present invention can be applied to analog I / O and electrostatic discharge (ESD) transistors. A problem called electrostatic discharge or ESD is a major concern in IC manufacturing. ESD occurs when a finite charge moves between two objects with different electrostatic potentials due to direct contact or an electrostatic field. This charge transfer causes a large current to flow through the chip in a very short time, resulting in circuit damage. By using different transistors with different resistances, a circuit can be formed that provides resistance to disturbance from electrical discharge. In order to obtain transistors with high and low resistance characteristics, the mobility in those transistors is adjusted. This mobility adjustment is performed by applying the present invention. By applying different hydrogen annealing parameters, or by using different thickness barrier diffusion layers for each transistor, the strain in the transistor can be tuned.

  In a specific example of the present invention, for example, a high mobility nMOS transistor and a low mobility nMOS transistor can be fabricated from the same material stack.

  A plurality of fins are patterned in the strained substrate using a photolithographic process or a spacer technique for patterning defined fin spacers. At least two fins need to be patterned. At this point, all fins contain strained material. The width of the fin is preferably selected from the range of 10 nm to 50 nm. The height of the fin is preferably selected from the range of 10 nm to 60 nm.

  In the next step, the first region is defined to include at least one fin, and the second region is defined to include at least one other fin. After defining the first region and the second region, all of the fins of the first region and the second region include strained material. In this example, the fins of the first region and the second region are the same conductivity, that is, an nMOS transistor.

  In the next step, a diffusion barrier layer is provided at least over the patterned fins in the first region. The diffusion barrier layer may include nitride. Deposition is performed by CVD, such as LP-CVD, plasma enhanced CVD, or other known deposition techniques. The thickness of the diffusion barrier layer depends on the hydrogen annealing parameters.

In the next step, hydrogen (H ₂ ) annealing is performed. During this H ₂ anneal, the strained material in the at least one fin of the second region that is not covered by the diffusion barrier layer is reflowed to relieve the strain. The thickness of the diffusion barrier layer depends on the temperature and time of the hydrogen annealing process. Preferably, the temperature and time of the hydrogen anneal is selected so that hydrogen does not affect the strain of the strained material in the at least one fin in the first region covered with the diffusion barrier layer. This means that the diffusion barrier region completely blocks hydrogen. Depending on the fin width, hydrogen annealing parameters must be applied to ensure reflow of the strained material.

  The method of the present invention is also applicable to planar devices. In planar devices, different stress factors may be introduced to increase the mobility of the channel region. By using the method of the present invention, channel region distortion is mitigated in a controlled manner.

  In the specific example of the present invention, for example, a high mobility nMOS transistor having a channel region made of strained silicon and a high mobility pMOS transistor can be manufactured from the same material stack.

  The nMOS transistor and the pMOS transistor are defined in a substrate containing a strained material. The channel regions of the nMOS transistor and the pMOS transistor both contain strained material. Strained silicon is useful for electron mobility in nMOS transistors, but not for hole mobility in pMOS transistors. It is an object of the present invention to alleviate strain in strained silicon in the pMOS region in order to increase the mobility of holes in the pMOS transistor.

  In the next step, a diffusion barrier region is provided at least in the channel region of the nMOS transistor. The diffusion barrier layer may include nitride. Deposition is performed by CVD, such as LP-CVD, plasma enhanced CVD, or other known deposition techniques. The thickness of the diffusion barrier layer depends on hydrogen annealing parameters such as temperature, time, pressure, and concentration.

In the next step, hydrogen (H ₂ ) annealing is performed. During this H ₂ annealing, the strained material in the channel of the pMOS transistor that is not covered by the diffusion barrier layer is reflowed to relieve the strain. Preferably, the temperature and time of hydrogen annealing is selected so that hydrogen does not affect the strain of the strained material in the channel of the nMOS transistor covered with the diffusion barrier layer.

  After using the method of the present invention, a planar CMOS device comprising at least one nMOS region and at least one pMOS region is known to those skilled in the art, for example, gate oxide deposition, gate patterning, source / drain. Different manufacturing processes such as injection are performed. In addition, different manufacturing processes known to those skilled in the art, such as SiGe source / drain regions, additional CESL layers, may be performed to increase the mobility of planar CMOS devices. In such subsequent steps, other stress factors can be added to the multi-gate device to further increase the mobility of the planar CMOS device, such as, for example, SiGe source / drain regions, additional CESL layers. These stress factors can be applied to the nMOS region or the pMOS region.

FIG. 4 shows the effect of H ₂ annealing on the strain in the nMOSMUGFET formed on the SSOI substrate. The experimental result by micro-Raman (micro-Raman) spectroscopic measurement is shown. The circle indicates the amount of strain as a function of fin width after fin patterning. The triangles show the strain as a function of fin width after H ₂ annealing using a hard mask. The hard mask functions as a diffusion barrier layer. The hard mask is a nitride / oxide mask. The squares indicate the amount of strain as a function of fin width after H ₂ annealing without a diffusion barrier layer, such as a hard mask.

After fin patterning of the SSOI substrate, the total amount of distortion decreases as the fin width decreases. This is due to biaxial stress changes for wide fins and uniaxial longitudinal tensile stress for narrow fins. For fins with fin widths between 50 nm and 2 μm, an increase in strain level is evident in devices that have undergone H ₂ annealing (without using a hard mask). This is due to the extra strain introduced by the wide fin surface reflow. However, in the fin having a fin width of less than 50 nm, Si reflow affects the entire fin and relaxes the strain. On the other hand, when the strain after fin patterning is 1000 MP, the strain after H ₂ annealing (without hard mask) is reduced to 500 MP. By covering a fin with a fin width of 35 nm with a nitride / oxide hard mask during H ₂ annealing, the strain is again increased by a factor of 2.5, in particular from 500 MPa to 1400 MPa. It can also be observed that by covering a fin having a fin width of 35 nm with a hard mask during H ₂ annealing, the strain becomes larger than after fin patterning. This is due to strain induced by the hard mask during H ₂ annealing.

  All drawings are intended to illustrate some aspects and embodiments of the present invention. The drawings are only schematic and are non-limiting. In the drawings, the size of some of the elements are exaggerated and not drawn to scale for illustrative purposes.

It is a schematic diagram of the process flow for relieving distortion of the 2nd field concerning the example of the present invention. It is a flow diagram for relieving the distortion of the pMOS region in the MUGFET on the SSOI substrate according to a specific example of the present invention. It is a flow diagram for relieving the distortion | strain of the nMOS area | region in MUGFET on the SGOI board | substrate concerning the example of this invention. 3 shows the effect of hydrogen (H ₂ ) annealing on strain in an nMOS MUGFET formed on an SSOI substrate according to an embodiment of the present invention. Experimental results are based on micro-Raman measurements. The circles show strain as a function of fin width after fin patterning. The squares show the strain as a function of fin width after H ₂ annealing without using a diffusion barrier layer (no hard mask). The triangles show strain as a function of fin width after H ₂ annealing using a diffusion barrier layer (with a hard mask).

Explanation of symbols

  100 substrate, 101 bulk layer, 103 strained material, 103a first region, 103b second region, 104 diffusion barrier layer.

Claims (21)

A method of reducing distortion in a multi-gate device,
Providing a substrate comprising a strained material;
Patterning a plurality of fins in the strained material;
Defining a first region including at least one fin;
Defining a second region including at least one fin;
Forming a diffusion barrier layer on the first region;
Performing hydrogen annealing so that the strained material of the at least one fin in the second region is relaxed.   The method according to claim 1, wherein the strain material of at least one fin in the first region is partially relaxed after the hydrogen annealing step.   The method according to claim 1, wherein the strained material of at least one fin in the first region remains unchanged after the hydrogen annealing step.   The method according to claim 1, wherein the diffusion barrier layer has a predetermined thickness, and the thickness depends on an annealing parameter of the hydrogen annealing.   The method according to claim 4, wherein the annealing parameters include temperature, pressure, concentration, or time.   The method according to claim 5, wherein the temperature of the hydrogen annealing is 900 ° C. or lower.   The method according to claim 5, wherein the hydrogen annealing time is in the range of 1 to 5 minutes.   The method according to claim 1, wherein the diffusion barrier layer has a thickness in the range of 5 nm to 50 nm.   The method according to claim 1, wherein the diffusion barrier layer contains nitride.   The method according to claim 1, wherein the diffusion barrier layer comprises a contact etch stop layer.   The method according to claim 1, wherein the contact etch stop layer has a compressive strain or a tensile strain.   The method according to claim 1, wherein the strained material comprises strained silicon.   The method according to claim 12, wherein the substrate is a strained silicon-on-insulator substrate.   14. A method according to claim 12 or 13, wherein the first region is an NMOS region and the second region is a PMOS region.   The method according to claim 1, wherein the strained material comprises germanium.   The method according to claim 15, wherein the substrate is a silicon-germanium-on-insulator substrate.   The method according to claim 15 or 16, wherein the first region is a PMOS region and the second region is an NMOS region. A method for alleviating strain in a semiconductor device,
Providing a substrate comprising a strained material;
Defining a first region;
Defining a second region;
Forming a diffusion barrier layer on the first region;
And hydrogen annealing so that the strained material in the second region is relaxed.   The method according to claim 18, wherein the strained material in the first region is partially relaxed after the hydrogen annealing step.   The method according to any one of claims 18 to 19, wherein the diffusion barrier layer has a predetermined thickness, and the thickness depends on an annealing parameter of the hydrogen annealing.   21. The method according to claim 20, wherein the annealing parameters include temperature, pressure, concentration, or time.