JP2003229542A - Manufacturing method for semiconductor device and heat treatment apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a simple manufacturing method for a semiconductor device for preventing the deterioration of characteristics in a ferroelectric capacitor due to hydrogen, and at the same time for recovering characteristics in a transistor due to the supply of the hydrogen. <P>SOLUTION: The manufacturing method includes a process for forming transistors T1, T2, and T3 on one surface of a semiconductor substrate 10, a process for forming an interlayer dielectric containing an insulating hydrogen barrier film 19, a process for forming contact holes 17a to 17e at a given section in the interlayer dielectric, a process for forming metal plugs 22a to 22e containing conductive hydrogen barrier films 20a to 20e in the contact holes 17a to 17e, a process for forming a ferroelectric capacitor Q connected to the predetermined metal plugs 22b and 22c, and a process for exposing the other surface of the semiconductor substrate 10 to a hydrogen-containing atmosphere and at the same time for heat-treatment the semiconductor substrate 10 without exposing one surface to the hydrogen-containing atmosphere. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device and a heat treatment apparatus, and more particularly to a method of manufacturing a semiconductor device having a ferroelectric capacitor and a heat treatment apparatus used in this method.

[0002]

2. Description of the Related Art In recent years, information can be retained even when the power is turned off,
Moreover, a ferroelectric non-volatile memory (FeRAM) has been attracting attention as a memory capable of writing and reading with low power consumption. The FeRAM has a memory cell including a transfer transistor and a ferroelectric capacitor.

Ferroelectric films forming a ferroelectric capacitor are lead zirconate titanate (PZT) and La-doped PZT.
PZT-based materials such as (PLZT) and SrBi ₂ Ta ₂ O ₉
(SBT, Y1), SrBi ₂ (Ta, Nb) ₂ O ₉ (SB
TN, YZ) or other Bi layer structure compound material,
These materials are sol-gel method, sputtering method, MOCVD
The film is formed by a method or the like. Usually, a ferroelectric film is formed by forming a ferroelectric film in an amorphous phase on a lower electrode and then crystallizing the ferroelectric film into a perovskite structure by heat treatment. Then, an upper electrode is formed on the ferroelectric film to obtain a capacitor structure.

An outline of a general manufacturing method of such an FeRAM will be described with reference to FIG. As shown in FIG. 6, first, an n-type or p-type silicon (semiconductor) substrate 10 is formed.
Element isolation insulating film 10 around the 0 transistor formation region.
Form 2. Then, a p-type impurity is introduced into the transistor formation region of the silicon substrate 100 to form the p-well 100a.
To form. Further, the surface of the transistor formation region of the silicon substrate 100 is thermally oxidized to form the gate insulating film 103.

Next, a gate electrode 104a made of a silicon film and a tungsten silicide film is formed on a predetermined portion of the gate insulating film 103.

Next, first to third n-type impurity diffusion regions 105 to be the source / drain are formed by ion-implanting n-type impurities into both sides of the gate electrode 104a in the p-well 100a.
a to 105c are formed.

Further, after an insulating film is formed on the entire surface of the silicon substrate 100 by the CVD method, the insulating film is etched back to form sidewall spacers 106 on both sides of the gate electrode 104a.

Then, using the gate electrode 104 and the side wall spacer 106 as a mask, the first to third n-type impurity diffusion regions 105a to 105c are ion-implanted again with the n-type impurity. The n-type impurity diffusion regions 105a to 105c are made to have an LDD structure.

Through the above steps, the n-type impurity diffusion layer 1 having the LDD structure and the gate electrode 104a is formed in the p well 100a.
Two MOS transistors T having 05a to 105c
1, T2 are formed.

Next, a cover insulating film 107 that covers the MOS transistors T1 and T2 is formed on the entire surface of the silicon substrate 100, and then a first interlayer insulating film 108 is formed. Then, the cover insulating film 107 and the first interlayer insulating film 108 are patterned to form the first to third impurity diffusion regions 105a to 105a.
First contact hole 10 having a depth reaching 105c
8a is formed. After that, the first to third conductive plugs 109a to 109c are respectively placed in the contact holes 108a.
To form.

After that, the second and third conductive plugs 10 are formed.
A ferroelectric capacitor Q composed of the lower electrode 115, the ferroelectric film 116 and the upper electrode 117 is formed so as to be connected to 9b and 109c, respectively.

After that, the second capacitor which covers the ferroelectric capacitor Q
The interlayer insulating film 120 is formed, and the first conductive plug 109a is formed.
A via hole 120a is formed in the upper second interlayer insulating film 120. Furthermore, the fourth conductive plug 121 is formed by being embedded in the via hole 120a. Then, the via hole 120 is formed in the second interlayer insulating film 120 on the ferroelectric capacitor Q.
b is formed.

Next, a first layer metal wiring 123 and a conductive pad 123a connected to the upper electrode 117 of the ferroelectric capacitor Q and the fourth conductive plug 121 are formed.

Further, a third interlayer insulating film 124 is formed on the second interlayer insulating film 120, the first layer metal wiring 123 and the conductive pad 123a. Then, the third interlayer insulating film 12
4 is patterned to form a via hole 124a on the conductive pad 123a, and a fifth conductive plug 125 is embedded in the via hole 124a. After that, a second multilayer wiring is formed on the third interlayer insulating film to form a predetermined multilayer wiring.

As described above, in a general FeRAM manufacturing method, the transistors T1 and T2 are formed on the semiconductor substrate 100, and then the transistors T1 and T2 are formed.
A ferroelectric capacitor Q is formed above the substrate via an insulating film. After that, a multilayer wiring for connecting the basic elements such as the transistors T1 and T2 and the ferroelectric capacitor Q to each other is formed.

In the transistors T1 and T2, semiconductor active layers (channel portion, source portion, drain portion, etc.) of the semiconductor active layer (channel portion, source portion, drain portion, etc.) are caused by process damage based on heat treatment or plasma treatment performed in the step of forming the ferroelectric capacitor Q and the multilayer wiring. Since dangling bonds are likely to occur in), variations and deviations in the threshold voltage of the transistors T1 and T2 are likely to occur.

Therefore, after forming the multilayer wiring, there is a method of suppressing variation or deviation of the threshold voltage of the transistor by annealing in a hydrogen-containing gas atmosphere to repair the dangling bond of the semiconductor active layer. Has been.

On the other hand, it is well known that the ferroelectric film 116 of the ferroelectric capacitor Q has its characteristics deteriorated by a reducing atmosphere, especially hydrogen. Therefore, when annealing is performed in a hydrogen-containing gas atmosphere, the transistor T
The threshold voltages of 1 and T2 are stable at desired values, but the characteristics of the ferroelectric capacitor Q are deteriorated.

In order to solve this problem, for example, Japanese Patent Laid-Open No. 11-126881 (Prior Art 1) discloses that between a capacitor in a region where a ferroelectric capacitor is formed and a transistor, and further on the ferroelectric capacitor. It is described that by partially forming a hydrogen diffusion preventing layer in the above, the entry of hydrogen from above and below the ferroelectric capacitor is prevented.

Further, in Japanese Patent Laid-Open No. 11-8355 (Prior Art 2), a first hydrogen barrier film and a second hydrogen barrier film are formed above and below a ferroelectric capacitor so as to cover the entire memory cell array. By forming
It is described that hydrogen is prevented from entering from above and below the ferroelectric capacitor.

[0021]

However, in the above-mentioned prior art 1, in order to restore the characteristics of the peripheral transistor by performing sufficient hydrogen heat treatment on the peripheral transistor, the peripheral transistor of the memory cell transistor and the peripheral transistor is not affected. In addition, the first and second hydrogen barrier films are not formed. Therefore, a step of forming the first and second hydrogen barrier films and a step of patterning these films are required, which complicates the manufacturing method, resulting in an increase in product cost. Become.

Also, in the above-mentioned conventional technique 2, it is necessary to form the first and second hydrogen barrier films on the upper and lower sides of the ferroelectric capacitor, respectively, which complicates the manufacturing method.

The present invention has been made in view of the above problems, and it is possible to prevent the characteristic deterioration of the ferroelectric capacitor due to hydrogen and to recover the characteristic of the transistor by supplying hydrogen by a simple manufacturing method. An object of the present invention is to provide a semiconductor device manufacturing method and a heat treatment apparatus used in the manufacturing method.

[0024]

In order to solve the above problems, the present invention relates to a method of manufacturing a semiconductor device, including a step of forming a predetermined transistor on one surface of a semiconductor substrate, and a step of forming the transistor and the semiconductor substrate. A step of forming an interlayer insulating film including an insulating hydrogen barrier film thereon, a step of forming a contact hole in a predetermined portion of the interlayer insulating film on the transistor, and a conductive hydrogen barrier film and a conductive film in the contact hole. Forming a conductive plug formed of a film, and connecting to the predetermined conductive plug,
Forming a ferroelectric capacitor composed of a lower electrode, an upper electrode and a ferroelectric film sandwiched between the lower electrode and the upper electrode; and hydrogen gas or hydrogen-containing gas on the other surface of the semiconductor substrate. And heat treating the semiconductor substrate in a state where the one surface of the semiconductor substrate is not exposed to the atmosphere of the hydrogen gas or the hydrogen-containing gas.

The present invention has a simple structure in which a hydrogen barrier film is not formed above and below the ferroelectric capacitor, that is, the transistor and the ferroelectric capacitor are separated by the hydrogen barrier film. It is devised so that hydrogen annealing for repairing the characteristics of the transistor can be performed while preventing deterioration due to the above.

In the present invention, first, an interlayer insulating film including an insulating hydrogen barrier film (for example, an alumina film) is formed over the entire substrate above a transistor formed on a semiconductor substrate, and a predetermined interlayer insulating film is formed. A conductive plug including a conductive hydrogen barrier film (for example, a titanium nitride film) is formed in the contact hole formed in the portion. Then, the ferroelectric capacitor is connected to the predetermined conductive plug.

As a result, the upper and side portions of the transistor are surrounded by the insulating hydrogen barrier film and the conductive hydrogen barrier film, respectively, and the transistor and the ferroelectric capacitor are separated by the insulating hydrogen barrier film and the conductive hydrogen barrier film. It is completely separated by the barrier film.

After that, when hydrogen heat treatment is performed to restore the characteristics of the transistor, a hydrogen-containing gas is supplied to the surface of the semiconductor substrate on which the transistor or the like is not formed (the other surface (back surface)), and the transistor of the semiconductor substrate is also supplied. For example, an inert gas is supplied to the surface on which the above is formed (one surface (front surface)) and hydrogen heat treatment is performed from the back surface of the semiconductor substrate in a state where hydrogen does not wrap around the front surface of the substrate.

By adopting such a heat treatment method,
Hydrogen supplied from the back surface of the semiconductor substrate is blocked by the hydrogen barrier film after diffusing in the transistor region, while
Hydrogen is no longer supplied from the front surface side of the semiconductor substrate. In other words, while the transistor and the ferroelectric capacitor have a simple structure in which they are separated by the hydrogen barrier film, hydrogen is supplied to the active layer of the transistor while the diffusion of hydrogen into the ferroelectric capacitor is blocked. It becomes possible to restore its characteristics.

Therefore, unlike the conventional example, the steps of forming the hydrogen barrier film on the upper and lower sides of the ferroelectric capacitor and patterning the hydrogen barrier film are unnecessary,
The manufacturing method can be simplified, and as a result, the yield of the semiconductor device can be improved and the increase in manufacturing cost can be suppressed.

In order to solve the above-mentioned problems, the present invention relates to a heat treatment apparatus, and a reaction chamber having a gas introduction part for introducing hydrogen gas or a hydrogen-containing gas, and a gas discharge part, and arranged in the reaction chamber. With a gas hole for introducing an inert gas, and has a substrate supporting portion for supporting the substrate, and a lamp arranged above the reaction chamber and radiating heat to the substrate, the substrate is An element surface of the substrate opposite to the element surface on which the element is formed is placed on the substrate supporting portion with the lamp side, and the opposite surface is exposed to the hydrogen gas or hydrogen-containing gas, and It is characterized in that the surface is heat-treated while the inert gas is supplied.

The heat treatment apparatus of the present invention is an RTA apparatus used in the above-described method for manufacturing a semiconductor device, wherein hydrogen gas is supplied to one surface of the substrate to be heat-treated and hydrogen gas is supplied to the other surface. The substrate can be heat-treated with hydrogen while the inert gas is supplied so as not to go around.

The surface (back surface) of the substrate to be heat-treated opposite to the element surface on which the elements are formed is the lamp side in which the hydrogen gas atmosphere is provided, and the element surface (front surface) of the substrate is the substrate supporting portion side. That is, the substrate is placed on the substrate support with the front and back reversed. Then, at the same time as exposing the back surface of the substrate to a hydrogen gas atmosphere, an inert gas is supplied to the front surface of the substrate from the gas holes of the substrate supporting portion to prevent the hydrogen gas from flowing from the back surface of the substrate to the front surface of the substrate. Hydrogen heat treatment can be performed from the back surface side.

By using the heat treatment apparatus having such a structure, the above-described method for manufacturing a semiconductor device can be easily performed.

[0035]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings.

1 to 3 are sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. An FeRAM will be described as an example of the semiconductor device of this embodiment.

First, steps required until a sectional structure shown in FIG. 1 is obtained will be described. As shown in FIG. 1, LOCOS (Local Oxidation of) is formed on the surface of a p-type silicon (semiconductor) substrate 10.
The element isolation insulating film 11 is selectively formed by the silicon method. As the element isolation insulating film 11, STI (Shallow Trench)
Isolation) may be adopted. Then, the silicon substrate 1
Memory cell area 1, which becomes the FeRAM area of 0, Logi
A p-type impurity and an n-type impurity are respectively added to predetermined active regions (transistor formation regions) in the peripheral circuit region 2 which becomes the c region.
A p-well 12a and an n-well 12b are formed by selectively introducing a type impurity. Although not shown in FIG. 1, a p-well (not shown) is also formed in the peripheral circuit region 2 to form a CMOS.

After that, the surface of the active region of the silicon substrate 10 is thermally oxidized to form a silicon oxide film as the gate insulating film 10a.

Next, an amorphous silicon film and a tungsten silicide film are sequentially formed on the entire upper surface of the silicon substrate 10, and the amorphous silicon film and the tungsten silicide film are patterned into a predetermined shape by a photolithography method, so that the gate electrodes 13a ... Thirteen
form c. A polysilicon film may be formed instead of the amorphous silicon film forming the gate electrodes 13a to 13c.

In the memory cell region 1, one p well 1
Two gate electrodes 13a and 13b are arranged in parallel on 2a, and these gate electrodes 13a and 13b form a part of the word line WL.

Next, in the memory cell region 1, n-type impurities are ion-implanted into the p-well 12a on both sides of the gate electrodes 13a and 13b to form the first, second and first n-channel MOS transistors. 3n-type impurity diffusion regions 15a, 15b, 15c are formed. At the same time, the p-well (not shown) in the peripheral circuit region 2 has an n
A type impurity diffusion region may be formed.

Subsequently, in the peripheral circuit region 2, p-type impurities are ion-implanted into the n-wells 12b on both sides of the gate electrode 13c to form the source / source of the p-channel MOS transistor.
First and second p-type impurity diffusion regions 15 to be drains
d, 15e are formed. The n-type impurities and the p-type impurities are separately implanted using a resist pattern.

After that, an insulating film is formed on the entire surface of the silicon substrate 10, and then the insulating film is etched back to leave side wall insulating films 16 on both sides of the gate electrodes 13a to 13c. As the insulating film, for example, a silicon oxide (SiO ₂ ) film is formed by the CVD (chemical vapor deposition) method.

Further, using the gate electrodes 13a, 13b and the sidewall insulating film 16 as a mask, the first, second and third n-type impurity diffusion regions 15a, 15b,
The first, second and third n-type impurity diffusion regions 15a, 1 are formed by ion-implanting n-type impurities into 15c again.
5b and 15c have an LDD structure. At the same time, the first and second n-type impurity diffusion regions 15 in the peripheral circuit region 2 are formed.
d and 15e also have an LDD structure. In addition, the peripheral circuit area 2
In the first and second p-type impurity diffusion regions 15d, 15
The first and second p-type impurity diffusion regions 15d and 15e are LDDed by ion-implanting p-type impurities into e.
Make it a structure.

Through the above steps, two MOS transistors T1 and T2 having the gate electrodes 13a and 13b and the first, second and third n-type impurity diffusion layers 15a, 15b and 15c of the LDD structure are formed in the p well 12a. To be done. Further, a MOS transistor T3 having a gate electrode 13c and first and second p-type impurity diffusion layers 15d and 15e having an LDD structure is formed in the n-well 12b.

Next, the MOS transistors T1, T2,
A silicon oxynitride (SiON) film having a thickness of about 200 nm is formed as a cover insulating film 14 covering T3 on the entire surface of the silicon substrate 10 by the plasma CVD method. Then TE
By a plasma CVD method using OS gas, silicon oxide (SiO 2) having a thickness of about 1.0 μm is formed as the intermediate insulating film 17.
₂ ) A film is grown on the cover insulating film 14.

Then, as a densification treatment of the intermediate insulating film 17, the intermediate insulating film 17 is formed in a nitrogen atmosphere at a normal pressure, for example.
Heat treatment is performed at a temperature of 0 ° C. for 30 minutes. After that, the upper surface of the intermediate insulating film 17 is flattened by the chemical mechanical polishing (CMP) method.

Next, an alumina film 18 (insulating hydrogen barrier film) having a film thickness of 50 nm, for example, is formed on the intermediate insulating film 17. As a result, the first interlayer including the cover insulating film 14, the intermediate insulating film 17, and the alumina film 18 (insulating hydrogen barrier film) is sequentially arranged from the bottom on the silicon substrate 10 on which the transistors T1, T2, T3 are formed. Insulating film 19
Is formed.

In this embodiment, the first interlayer insulating film 1
Although the example in which the alumina film 18 is formed as the uppermost layer is shown as 9, the invention is not limited to this, and the first interlayer insulating film 19 may include the alumina film 18.
Although the alumina film 18 is illustrated as the insulating hydrogen barrier film, a silicon oxynitride film (SiON film) or a silicon nitride film (SiN film) may be used instead of the alumina film 18.

In this way, first, the sectional structure shown in FIG. 1A is obtained.

Then, as shown in FIG. 1B, the alumina film 18 and the intermediate insulating film 1 are formed by photolithography.
7 and the cover insulating film 14 are patterned to form contact holes 17a to 17e having a depth reaching the impurity diffusion regions 15a to 15e, respectively.

Subsequently, a Ti (titanium) thin film having a film thickness of 30 nm and a TiN (titanium nitride) thin film having a film thickness of 50 nm are sequentially formed on the upper surface of the alumina film 18 and the inner surfaces of the contact holes 17a to 17e by a sputtering method to form a glue film. And Further, tungsten (W) is grown on the glue film by the CVD method. As a result, the contact hole 1
The tungsten film is embedded in 7a to 17e.

Thereafter, as shown in FIG. 1C, the tungsten film and the glue film are polished by the CMP method until the upper surface of the alumina film 18 is exposed, whereby the glue films 20a to 20e and the glue films 20a to 20e are formed in the contact holes 17a to 17e. The tungsten plugs 21a to 21e are embedded.

As a result, one p in the memory cell area 1 is
In the well 12a, two gate electrodes 13a, 1
The first n-type impurity diffusion region 15a sandwiched between
The conductive plug 22a is formed, and the second and third n
Second and third conductive plugs 22b and 22c are formed on the type impurity diffusion regions 15b and 15c, respectively. At the same time, fourth and fifth conductive plugs 22d and 22e are formed on the first and second p-type impurity diffusion regions 15d and 15e of the peripheral circuit region 2, respectively. And the first
The conductive plug 22a is connected to a bit line described later, and the second and third conductive plugs 22b and 22c are connected to ferroelectric capacitors described later, respectively.

These first to fifth conductive plugs 22a ...
Since the glue films 20a to 20e of 22e are films containing at least a TiN film, they function as a conductive hydrogen barrier film.

In this way, the transistors T1, T
2, T3 has an upper portion covered with an alumina film 18 (insulating hydrogen barrier film) over the entire substrate, and has side portions formed in the contact holes 17a to 17e.
It is covered with glue films 20a to 20e (conductive hydrogen barrier film) including an iN film.

Then, as shown in FIG.
On the fifth conductive plugs 22a to 22e and the alumina film 18, for example, iridium (I
r) A film 23x, a platinum (Pt) oxide film 23y having a thickness of 230 nm, and a platinum film 23z having a thickness of 50 nm are formed as a first conductive film 23a.

Before or after forming the first conductive film 23a, the silicon substrate 10 is annealed to prevent film peeling. The annealing in this case is performed by, for example, RTA (Rapid Thermal Annea) at a substrate temperature of 750 ° C. in an argon atmosphere.
ling).

Next, a PZT film having a film thickness of, for example, 200 nm is formed as the ferroelectric film 24a on the first conductive film 23a by the sputtering method. The method for forming the ferroelectric film 24a is
In addition, MOD (metal organic deposition) method, MO
There are a CVD (organic metal CVD) method, a sol-gel method, and the like.
In addition to PZT, other PZT-based materials such as PLCSZT and PLZT, and Bi such as SrBi ₂ Ta ₂ O ₉ and SrBi ₂ (Ta, Nb) ₂ O ₉ may be used as the material of the ferroelectric film 24a. It may be a layered structure compound material or other metal oxide ferroelectric material.

Then, in the oxygen atmosphere, the ferroelectric film 24a is formed.
Is crystallized by annealing. As the annealing, for example, in a mixed gas atmosphere of argon and oxygen, the substrate temperature 600
A two-step RTA process is employed in which the first step is a condition of 90 ° C. for 90 seconds, and the second step is a substrate temperature of 750 ° C. for 60 seconds in an oxygen atmosphere.

Further, as the second conductive film 25a on the ferroelectric film 24a, for example, iridium oxide having a film thickness of 200 nm is formed.
A (IrO ₂ ) film is formed by the sputtering method.

After this, the second and third conductive plugs 22 are formed.
A hard mask 26 made of a TiN film and a SiO ₂ film is formed on a predetermined portion of the second conductive film 25a on the surfaces b and 22c in order from the bottom.
To form. The hard mask 26 is patterned by photolithography so as to have a planar shape of the capacitor.

Next, as shown in FIG. 2B, the second conductive film 25a, the ferroelectric film 24a and the first conductive film 23a in the region not covered with the hard mask 26 are sequentially etched. In this case, the ferroelectric film 24a is etched by the sputter reaction in the atmosphere containing chlorine and argon.
The second conductive film 25a and the first conductive film 23a are made of bromine (B
r ₂ ) Introduced atmosphere, in an atmosphere containing Br, or in an atmosphere in which only HBr and oxygen are introduced, etching is performed by a sputter reaction.

As described above, the ferroelectric capacitor Q composed of the lower electrode 25, the capacitor dielectric film 24, and the second conductive film 23 is formed. In the transistor formation region 1, one lower electrode 23 is connected to the second conductive plug 2
2b is electrically connected to the second impurity diffusion region 15b, and the other lower electrode 23 is connected to the third conductive plug 2
It is electrically connected to the third impurity diffusion region 15c via 2c. After that, the hard mask 26 is removed.

Subsequently, the ferroelectric film 24 by etching
Recovery anneal is performed to recover the damage. Recovery annealing in this case is performed, for example, at a substrate temperature of 650 ° C.
It is carried out in an oxygen atmosphere under the condition of 60 minutes.

When this step is completed, the transistors T1, T2, T3 and the ferroelectric capacitor Q are separated by the alumina film 18 (insulating hydrogen barrier film) and the conductive plug 22a.
A structure completely separated by the glue films 20a to 20e (conductive hydrogen barrier film) of .about.22e is obtained. As a result, when hydrogen annealing for repairing the characteristics of the transistors T1, T2, T3 is performed in a later step, first of all,
It can be seen that the diffusion of hydrogen from the lower side of the transistors T1, T2, T3 into the ferroelectric capacitor is completely prevented.

After that, as shown in FIG.
As the second interlayer insulating film 28 covering the ferroelectric capacitor Q, the film thickness is 1.0 μm by the plasma CVD method using S gas.
A silicon oxide (SiO ₂ ) film of about m is formed on the structure of FIG. Further, the upper surface of the second interlayer insulating film 28 is flattened by the CMP method. In this example, the remaining film thickness of the second interlayer insulating film 28 after CMP is about 300 nm on the upper electrode 25 of the ferroelectric capacitor Q.

Subsequently, the second interlayer insulating film 28 is selectively etched by using a resist mask (not shown), so that the first, fourth and fifth conductive plugs 22a, 22d,
Via holes 28a, 28d, and 28e on 22e, respectively.
To form. After the etching, in order to recover the capacitor ferroelectric film 24 from damage, annealing is performed for 60 minutes at a substrate temperature of 550 ° C. in an oxygen atmosphere, for example.

Further, the via holes 28a, 28d, 28
A film having a thickness of 3 as a glue film is formed in the inside of e and on the second interlayer insulating film 28.
A 0 nm Ti film and a 50 nm thick TiN film are sequentially formed by a sputtering method. Further, a W film is grown on the glue layer by the CVD method and the via holes 28a, 28d,
28e is completely embedded.

Subsequently, the W film, the TiN film and the Ti film are replaced with C
Polishing is performed by the MP method and removed from the upper surface of the second interlayer insulating film 28. And the via holes 28a, 28d, 28e
The tungsten film and the glue layer embedded in the inside are respectively replaced by sixth, seventh and eighth conductive plugs 29a, 29b and 2
9c. The sixth conductive plug 29a has the first n-type impurity diffusion region 15a via the first conductive plug 22a.
Electrically connected to.

Then, the second interlayer insulating film 28 is patterned by photolithography to form via holes 28 on the upper electrodes 27 of the two ferroelectric capacitors Q, respectively.
b, 28c are formed.

The capacitor Q damaged by forming the via holes 28b and 28c is recovered by annealing. The annealing is performed for 60 minutes at a substrate temperature of 550 ° C. in an oxygen atmosphere, for example.

Next, as shown in FIG. 3, a multi-layer metal film is formed on the structure of FIG. 2C, and this multi-layer metal film is patterned to form the first-layer metal wiring 30a and the conductive pad 30b. Form. In the memory cell region 1, the first-layer metal wiring 30a has via holes 28b and 28c.
Is connected to the upper electrode 25 of the ferroelectric capacitor Q through, and the conductive pad 30b is connected to the sixth conductive plug 29.
connected to a. On the other hand, in the peripheral circuit region 2, the first-layer metal wiring 30a is connected to the eighth conductive plug 29c, and the conductive pad 30b is connected to the seventh conductive plug 29.
connected to b.

As this multilayer metal film, for example, a film thickness 60
nm Ti film, 30 nm thick TiN film, 400 n thick
m Al—Cu film, 5 nm thick Ti film, and 70 nm thick
nm TiN film is sequentially formed.

As a method for patterning the multilayer metal film, an antireflection film (not shown) made of a SiON film having a film thickness of 31 nm is formed on the multilayer metal film, and after applying a resist on the antireflection film, A method is used in which a resist is exposed and developed to form a resist pattern such as a wiring shape, and the resist pattern is used for etching.

Further, a third interlayer insulating film 31 is formed on the second interlayer insulating film 28, the first-layer metal wiring 30a and the conductive pad 30b. Then, by patterning the third interlayer insulating film 31, the first-layer metal wiring 30 on the conductive pad 30b in the memory cell region 1 and in the peripheral circuit region 2 is patterned.
Via holes 31a and 31b are formed on a, respectively.
Subsequently, the via holes 31a and 31b are formed by burying the ninth and tenth conductive plugs 32a and 32b made of a Ti film, a TiN film and a W film in order from the bottom.

After that, although not particularly shown, a second layer wiring including a bit line is formed on the third interlayer insulating film 31. The bit line is connected to the ninth conductive plug 3 in the memory cell area 1.
It is electrically connected to the first n-type impurity diffusion region 15a through 2a and the conductive pad 30b formed below it in a stack structure, the sixth conductive plug 29a, and the first conductive plug 22a. Subsequently, an insulating film or the like covering the second wiring layer is formed to form a predetermined multilayer wiring, but the details thereof will be omitted.

As described above, the predetermined transistors T1, T2 and T3 are formed on the silicon substrate 10, the ferroelectric capacitors Q are formed above the transistors T1 and T2 in the memory cell region 1, and then the ferroelectric capacitors Q are formed. , Multilayer interconnections for interconnecting the transistors T1, T2, T3 and the ferroelectric capacitor Q are formed.

The active layers such as the channel portion, the source portion and the drain portion of the transistors T1, T2 and T3 formed on the silicon substrate 10 are subjected to the heat treatment for forming the ferroelectric capacitor by undergoing the above-mentioned manufacturing process. Dangling bonds are formed due to process damage caused by plasma treatment used in the insulating film forming step and the etching step.

For this reason, the transistor T
Even if 1, T2 and T3 are created, the threshold voltage (Vt
In some cases, characteristic defects such as variation or deviation of h) may occur. In particular, in a high-performance transistor having a short gate length, such characteristic defects are likely to occur.

Therefore, the semiconductor substrate 10 on which the above-described multi-layer wiring formation process has been completed is annealed with hydrogen to restore the dangling bonds in the active layers of the transistors T1, T2 and T3, and to improve the transistor characteristics. It is preferable to repair.

In the method of manufacturing the semiconductor device of this embodiment,
As described above, the alumina film 18 (insulating hydrogen barrier film) is formed over the entire silicon substrate 10 above the transistors T1, T2 and T3, and the transistor T
Glue film 2 including a TiN film on the side of 1, T2, T3
A structure having 0a to 20e (conductive hydrogen barrier film) is formed.

That is, when hydrogen annealing is performed, the lower side of the transistors T1, T2, T3 (silicon substrate 10
Hydrogen diffused from the side) is completely blocked by the alumina film 18 (insulating hydrogen barrier film) and the glue films 20a to 20e (conductive hydrogen barrier film), so that the characteristics of the ferroelectric capacitor Q are deteriorated by hydrogen. To be prevented.

On the other hand, when hydrogen annealing is carried out, hydrogen diffused from the upper side of the transistors T1, T2, T3 (the side of the multi-layer wiring) into the ferroelectric capacitor Q can be obtained by using the following heat treatment apparatus. Even if the hydrogen barrier film is not formed on the upper side (multilayer wiring side) of the ferroelectric capacitor Q, hydrogen can be prevented from diffusing into the ferroelectric capacitor.

FIG. 4 is a cross-sectional view showing how the silicon substrate according to the method of manufacturing the semiconductor device of this embodiment is annealed by hydrogen, and FIG. 5 is a cross-sectional view showing the heat treatment device of the embodiment of the present invention.

As shown in FIG. 5, the heat treatment apparatus 52 of the present embodiment is an RTA apparatus, and includes a reaction chamber 34 for heat treating the silicon substrate 10 and an infrared lamp housing section 46 arranged above the reaction chamber 34. , Heating the silicon substrate 10,
Infrared lamp 44 stored in infrared lamp storage section 46
It is basically configured by (heating means), a substrate supporting portion 38 formed in a cylindrical shape in the reaction chamber 34, and a substrate chuck 36 for fixing the silicon substrate 10.

Around the region of the hydrogen atmosphere in the reaction chamber 34, a gas introducing portion 33 for introducing hydrogen gas or hydrogen-containing gas and a gas discharging portion 35 for discharging gas are connected,
They are provided with valves 33a and 35a, respectively. Further, the reaction chamber 34 and the infrared lamp housing 46 are shut off by a quartz plate 48. Further, a moving shaft 42 is connected to a lower portion of the peripheral portion of the substrate supporting portion 38 via a metal bellows 40 capable of expanding and contracting.

Further, in the lower central portion of the substrate supporting portion 38,
Gas holes 38a penetrating in the thickness direction (gas introducing means)
Is formed, and an inert gas supply portion 37 having a valve 37a is connected to the lower portion of the gas hole 38 through a stretchable metal bellows 40a.

Then, first, the silicon substrate 10 is carried and placed on the substrate supporting portion 38 in the heat treatment apparatus 52. At this time, the silicon substrate 10 is mounted so that the surface (front surface) on which the transistors, the ferroelectric capacitors, and the like are formed faces the substrate supporting portion 36 side.

That is, as shown in FIG. 4, the silicon substrate 10 which has been subjected to the multi-layer wiring process of FIG. 3 is turned upside down so that the back surface is the infrared lamp 44 side and the front surface is the substrate supporting portion 3.
It is placed so that it is on the 8 side. After that, the substrate supporting portion 38 moves upward in cooperation with the movement of the moving shaft 42, so that the peripheral portion of the silicon substrate 10 is sandwiched and fixed by the substrate supporting portion 38 and the substrate chuck 36.

Next, the valve 33a is opened and hydrogen gas or hydrogen-containing gas, for example, preferably 3 is supplied from the gas supply unit 33.
2000% hydrogen / nitrogen mixed gas containing 10% hydrogen
The gas is supplied to the reaction chamber 34 at a flow rate of sccm, the valve 35a of the gas discharge part is opened to discharge the gas, and the gas pressure is controlled to a predetermined value. As a result, as shown in FIG. 4, the surface (rear surface) of the silicon substrate 10 on which the transistors and the ferroelectric capacitors are not formed is exposed to the hydrogen-containing gas atmosphere.

At the same time, the gas holes 3 of the substrate supporting portion 30.
From 8a, an inert gas such as nitrogen, argon, helium or a mixed gas thereof, preferably, for example, nitrogen gas 10
It is supplied at a flow rate of 0 sccm to the surface (front surface) of the silicon substrate 10 on which transistors, ferroelectric capacitors, and the like are formed. This inert gas flows from the central portion of the surface of the silicon substrate 10 to the peripheral portion, and the surface of the silicon substrate 10 becomes an inert gas atmosphere.

The substrate chuck 36, together with the substrate supporting portion 38, also functions as a partition for separating the hydrogen atmosphere region to which the front surface of the silicon substrate 10 is exposed and the inert gas atmosphere region to which the back surface thereof is exposed.

Next, with the front and back surfaces of the silicon substrate 10 in the above-mentioned gas atmosphere, the infrared lamp 44
The lamp heating is carried out for 30 minutes so that the substrate temperature becomes about 450 ° C.

At this time, since the back surface of the silicon substrate 10 is heated in the hydrogen-containing gas atmosphere, hydrogen diffuses from the back surface of the silicon substrate 10 to the active layers of the transistors T1, T2 and T3 and is bonded to the dangling bond. . As a result, the dangling bond that causes the characteristic deterioration of the transistors T1, T2, T3 is restored, and the transistor T1 is restored.
Characteristics such as threshold voltages of 1, T2 and T3 are restored to desired values.

Moreover, the alumina film 18 (insulating hydrogen barrier film) is formed between the transistors T1, T2, T3 and the ferroelectric capacitor Q over the entire substrate, and the contact holes 17a to 17e are covered with glue. Films 20a to 20e (conductive hydrogen barrier film) are formed. Therefore, hydrogen diffusing from the back surface of the silicon substrate 10 is blocked by these hydrogen barrier films,
There is no fear that hydrogen will diffuse into the ferroelectric capacitor Q and its characteristics will deteriorate.

On the other hand, on the front surface side of the silicon substrate 10, an inert gas such as nitrogen gas, that is, a gas that does not cause the characteristic deterioration of the ferroelectric capacitor Q is supplied at any time during hydrogen annealing, so that the back surface of the silicon substrate 10 is There is no possibility that the supplied hydrogen will go around to the surface side of the silicon substrate 10. That is, during hydrogen annealing, the silicon substrate 10
Since it is devised so that hydrogen does not wrap around to the surface side of, the hydrogen barrier film need not be specially formed on the multilayer wiring side above the ferroelectric capacitor Q.

In this way, the semiconductor device 50 shown in FIG. 4 is manufactured by the method for manufacturing a semiconductor device of this embodiment. In the method of manufacturing the semiconductor device of this embodiment, the alumina film 18 (insulating hydrogen barrier film) and the glue film 2 are formed on the upper and side portions of the transistors T1, T2, T3, respectively.
0a to 20e (conductive hydrogen barrier film) is used to form a structure, and the heat treatment device 52 is devised so that hydrogen does not diffuse from the front surface of the silicon substrate 10. T1, T2, T
I am trying to supply to 3.

Therefore, the transistors T1, T2 and T3 are
By providing a hydrogen barrier film between the ferroelectric capacitor Q and the ferroelectric capacitor Q, sufficient hydrogen can be supplied to the transistors T1, T2, T3 to restore their characteristics, and at the same time,
It is possible to prevent the characteristic deterioration of the ferroelectric capacitor due to hydrogen.

Further, unlike the prior arts 1 and 2, it is not necessary to provide two layers of hydrogen barrier films above and below the ferroelectric capacitor Q and to pattern each of them, so that the manufacturing process is simplified. And as a result,
It is possible to improve the yield of semiconductor devices and
It will be possible to suppress the cost increase.

[0101]

As described above, according to the present invention, the transistor and the ferroelectric capacitor formed on the semiconductor substrate are the interlayer insulating film including the insulating hydrogen barrier film and the contact formed on the predetermined portion thereof. A completely separated structure is formed by the conductive hydrogen barrier film in the hole. After that, when hydrogen heat treatment is performed to restore the characteristics of the transistor, a hydrogen-containing gas is supplied to the surface of the semiconductor substrate on which the transistor is not formed (rear surface), and the surface of the semiconductor substrate on which the transistor is formed (front surface). ) Is supplied with an inert gas to prevent hydrogen from wrapping around the surface of the semiconductor substrate, and hydrogen heat treatment is performed from the back surface of the semiconductor substrate.

By adopting such a heat treatment method,
Hydrogen supplied from the back surface of the semiconductor substrate is blocked by the hydrogen barrier film, while hydrogen is not supplied from the front surface of the semiconductor substrate, so the diffusion of hydrogen into the ferroelectric capacitor is blocked and the active transistor is activated. It will be possible to supply hydrogen to the layer and restore its properties.

As described above, since it is not necessary to form the hydrogen barrier films above and below the ferroelectric capacitor and to pattern them, the manufacturing method can be simplified. Therefore, the yield of the semiconductor device can be improved, and the increase in manufacturing cost can be suppressed.

[Brief description of drawings]

FIG. 1 is a sectional view (No. 1) showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view (No. 2) showing the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a sectional view (3) showing the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view showing how the silicon substrate according to the method for manufacturing a semiconductor device of the embodiment of the present invention is subjected to hydrogen annealing.

FIG. 5 is a sectional view showing a heat treatment apparatus according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

10 ... Silicon substrate (semiconductor substrate), 11 ... Element isolation insulating film, 12a, 12b ... Well regions, 13a, 13b,
13c ... Gate electrode, 14 ... Cover insulating film, 15a, 1
5b, 15c ... N-type impurity diffusion layers, 15d, 15e ... p
Type impurity diffusion region, 16 ... Sidewall, 17 ...
Intermediate insulating film, 17a to 17e ... Contact hole, 20
a to 20e ... Glue film (conductive hydrogen barrier film), 18 ...
Alumina film (insulating hydrogen barrier film), 19 ... First interlayer insulating film, 21a to 21e ... Tungsten plug, 22a to
22e ... Conductive plug, 23x ... Iridium film, 23y
... Platinum oxide film, 23z ... Platinum film, 23a ... First
Conductive film, 24a ... Ferroelectric film, 25a ... Second conductive film, 2
3 ... Lower electrode, 24 ... Ferroelectric film for capacitor, 25 ...
Upper electrode, 26 ... Hard mask, 22a to 22e, 29
a to 29c, 32a, 32b ... Conductive plug, 30a ...
First layer metal wiring, 30b ... Conductive pad, 28 ... Second interlayer insulating film, 28a to 28e, 31a, 31b ... Via hole, 31 ... Third interlayer insulating film, 33 ... Gas introducing part, 33
a, 35a, 37a ... Valve, 34 ... Reaction chamber, 35 ... Gas discharge part, 36 ... Substrate chuck, 37 ... Inert gas supply part, 38 ... Substrate support part, 38a ... Gas hole, 40, 40a
... metal bellows, 42 ... moving shaft, 44 ... infrared lamp,
46 ... Infrared lamp storage section, 48 ... Quartz plate, 50 ... Semiconductor device, 52 ... Heat treatment apparatus.

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F048 AB01 AC03 BA01 BB08 BC06                       BE03 BF06 BF16 BG01 BG13                       DA25 DA27                 5F083 FR02 GA25 JA15 JA17 JA33                       JA35 JA38 JA39 JA40 JA43                       MA06 MA16 MA17 NA01 NA08                       PR34 PR40 ZA12

Claims (5)

[Claims] 1. A step of forming a predetermined transistor on one surface of a semiconductor substrate; a step of forming an interlayer insulating film including an insulating hydrogen barrier film on the transistor and the semiconductor substrate; Forming a contact hole in a predetermined portion of the interlayer insulating film; forming a conductive plug composed of a conductive hydrogen barrier film and a conductive film in the contact hole; connecting to the predetermined conductive plug And forming a ferroelectric capacitor composed of a lower electrode, an upper electrode, and a ferroelectric film sandwiched between the lower electrode and the upper electrode on the interlayer insulating film, and the other of the semiconductor substrates. Is exposed to the atmosphere of hydrogen gas or hydrogen-containing gas, and the one surface of the semiconductor substrate is not exposed to the atmosphere of hydrogen gas or hydrogen-containing gas. In method of manufacturing a semiconductor device characterized by a step of annealing the semiconductor substrate. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of heat treating the semiconductor substrate, an inert gas is supplied to the one surface of the semiconductor substrate. 3. The insulating hydrogen barrier film is an alumina film,
3. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive hydrogen barrier film is a silicon oxynitride film or a silicon nitride film, and the conductive hydrogen barrier film is a titanium nitride film or a laminated film including a titanium nitride film. . 4. A heat treatment apparatus for heat-treating the substrate by exposing one surface of the substrate to a hydrogen gas atmosphere and exposing the other surface of the substrate to an inert gas atmosphere, wherein the hydrogen gas atmosphere contains hydrogen. A gas introducing part for introducing a gas or a gas containing hydrogen, and a reaction chamber provided with a gas exhausting part, and being arranged in the reaction chamber, supporting the substrate,
And a substrate supporting part having a gas introducing means for introducing an inert gas into the inert gas atmosphere, and a heating means arranged above the reaction chamber and irradiating the substrate with heat. Heat treatment equipment. 5. The heat treatment according to claim 4, wherein one surface of the substrate is an element surface on which elements are formed, and the other surface of the substrate is an opposite surface to the element surface. apparatus.