KR19990085617A - Manufacturing Method of Semiconductor Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device that minimizes junction leakage currents, wherein shallow trench isolation (STI) is formed on the semiconductor substrate to define active and inactive regions. Impurity ions are implanted into the active region to form at least one impurity region. A gate electrode is formed on the active region with a gate insulating film interposed therebetween. The semiconductor substrate is heat-treated by a rapid heat treatment (RTP) method to remove stresses and defects in the substrate generated when the device isolation film and the impurity ion implantation are formed. In this method of manufacturing a semiconductor device, by performing a rapid heat treatment process after the formation of the gate electrode, it is possible to cure damage to the gate oxide film on both lower sides of the gate electrode, and at the same time to remove the stress and defects in the substrate and to perform the subsequent heat treatment. It is possible to prevent the bonding damage occurring in the step. Therefore, the quality of the gate insulating film can be improved and the junction leakage current can be minimized.

Description

A METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for minimizing a junction leakage current due to a defect in a semiconductor substrate.

A semiconductor device is completed by repeating a unit process such as a photolithography process, an ion implantation process, a diffusion process, and a cleaning process. As the unit process technology has been developed and the semiconductor devices have been highly integrated, the semiconductor memory devices have entered the era of giga DRAM.

However, as the size of the device scales down to 0.10 μm or less, the stress generated during the manufacturing process is further increased. When the stress exceeds the threshold, dislocations, which are line defects in a crystal, are generated in the single crystal substrate, thereby intensifying the stress.

A shallow trench isolation method is used as a device isolation method due to high integration of semiconductor devices. The shallow trench isolation method induces more stress in the substrate than the conventional local oxidation of silicon (LOCOS) method. As semiconductor devices using this shallow trench isolation method increase, P. M. Fahey et. as reported in papers such as "stress-induces dislocations in silicon integrated circuits" (IBM J. RES. DEVELOP, v. 36, p 158, 1992). There is an increasing number of joint damages and reports to improve them.

On the other hand, as the device junction forming technology, many ion implantation (ion implantation) methods that can easily control the doping concentration and the doping profile have been used. However, as the ions having high energy penetrate single crystal silicon, when the doping concentration exceeds the threshold, the crystallinity of the silicon substrate is broken to form an amorphous layer. The amorphous layer recovers its crystallinity in a subsequent heat treatment process, in which residual defects gather together to form collective lattice defects, stacking faults, and dislocation loops. ("Formation of extended defects in silicon by high energy implantation of B and P", JY Cheng et. Al., J. Appl. Phys., V. 80 (4), p. 2105, 1996), ("Annealing behaviors of dislocation loops near the projected range in high-dose As implanted (001) Si ", SN Hsu, et. al., J. Appl. Phys. v.86 (9) p.4503, 1990)

1 is an X-transmission electron microscopy (XTEM) photograph showing defects in a conventional semiconductor substrate.

Dislocations, bunch defects, collective lattice defects, and the like, generated during the manufacturing process of the semiconductor device as described above, are denoted by reference symbol 'A' in FIG. 1 to depletion regions of the p / n junction of the semiconductor device. When penetrated, the semiconductor device has abnormal bonding characteristics.

2 is a graph showing the electrical characteristics (electric characteristics) of the conventional p / n junction.

In FIG. 2, when the reverse bias is applied to a conventional p / n junction, the graph characteristic shows an abnormally large current flow. This problem increases the standby current of the semiconductor device. This not only causes serious problems in the manufacture of low power consumption devices, but also causes a malfunction of the semiconductor device when the standby current is high.

The present invention has been proposed to solve the above-mentioned problems, and provides a method of manufacturing a semiconductor device capable of preventing the bonding damage generated during the subsequent heat treatment process by removing potentials and collective lattice defects existing in the semiconductor substrate. The purpose is.

Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of curing a gate insulating film damage generated during an etching and cleaning process for forming a gate electrode.

1 is an X-transmission electron microscopy (XTEM) photograph showing defects in a conventional semiconductor substrate;

2 is a graph showing the electrical properties of a conventional p / n junction;

3A to 3E are flowcharts sequentially showing processes of a method of manufacturing a semiconductor device according to an embodiment of the present invention;

4 is an enlarged view of reference numeral 19 of FIG. 3C;

5 is an enlarged view of reference numeral 20 of FIG. 3D;

FIG. 6 is a graph showing reverse bias current against reverse bias voltage of a p / n junction according to the prior art and the present invention. FIG.

* Explanation of symbols for the main parts of the drawings

10 semiconductor substrate 12 device isolation film

14a and 14b well region 16 gate insulating film

18a and 18b gate electrodes 22 insulating film

24: gate spacers 26a, 26b: source / drain regions

(Configuration)

According to the present invention for achieving the above object, a manufacturing method of a semiconductor device, comprising: forming an isolation layer on the semiconductor substrate to define an active region and an inactive region; Implanting impurity ions into the active region to form at least one impurity region; Forming a gate electrode on the active region with a gate insulating layer interposed therebetween; And rapid thermal processing of the semiconductor substrate to remove stresses and defects in the substrate generated when the device isolation layer and the impurity ion implantation are formed.

(Action)

Referring to FIG. 6, in the novel semiconductor device manufacturing method according to the exemplary embodiment of the present invention, well ion implantation or the like is performed after shallow trench isolation is formed. A rapid heat treatment process is performed to remove stress and defects in the substrate generated during the shallow trench isolation and ion implantation processes. According to such a semiconductor device manufacturing method, by performing a rapid heat treatment process after the formation of the gate electrode, it is possible to cure damage to the gate oxide film on both lower sides of the gate electrode, and to prevent the bonding damage due to stress and defects in the substrate. . Therefore, the quality (Q _BD , T _DDB ) of the gate insulating film can be improved, and the junction leakage current can be minimized.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 3 to 6.

3A to 3E are flowcharts sequentially illustrating processes of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3A, a device isolation layer 12 is formed on the semiconductor substrate 10 to define an active region and an isolation region. The device isolation film 12 is here formed by a shallow trench isolation method. More specifically, after the active region photoresist pattern is formed on the semiconductor substrate 10, a mask etching process, a trench etching process, a separator deposition process, and a chemical mechanical polishing (CMP) process are performed. As a result, the device isolation film 12 having the surface where the active region and the inactive region are flat to each other is formed.

In FIG. 3B, a well ion implantation process is performed on a region where a MOS transistor is to be formed. In addition, a channel stop ion implantation process for improving device and device isolation characteristics, and a threshold voltage regulation ion implantation process for adjusting a threshold voltage of a transistor are performed. Then, well regions 14a and 14b, channel stop regions (not shown), and threshold voltage adjusting regions (not shown) are formed, respectively. The well regions 14a and 14b include a p-type well region 14a and an n-type well region 14b.

Referring to FIG. 3C, gate electrodes 18a and 18b are formed on the active region with the gate insulating layer 16 interposed therebetween. The gate insulating film 16 is formed of, for example, an oxide film, and the gate electrodes 18a and 18b are formed of, for example, a multilayer film in which a metal silicide film is stacked on a polysilicon film. The gate electrodes 18a and 18b are formed by patterning using the photolithography process well known in the art after the multilayer film is deposited.

4 is an enlarged view of reference numeral 19 of FIG. 3C.

However, in the etching and cleaning process for forming the gate electrode, as shown in FIG. 4, damage to the gate insulating layer 16 under both sides of the gate electrodes 18a and 18b occurs.

In FIG. 3D, a rapid thermal process (RTP) process, which is a core process according to the present invention, is performed on the semiconductor substrate 10. The rapid heat treatment process cures the damaged gate insulating layer 16, and removes stress and defects in the semiconductor substrate 10 generated during the formation of the shallow isolation isolation device 12 and the ion implantation process. To be performed.

The rapid heat treatment process should preferably be carried out under conditions such that at least the lattice defects are removed and the diffusion of impurities introduced into the ion implantation process is suppressed as much as possible. In general, the rapid heat treatment process has a high stress relaxation effect because it reaches a high temperature in a very short time compared to the furnace heat treatment process, and the lattice while suppressing the diffusion of the dopant injected by the ion implantation process as much as possible It is very advantageous to eliminate the defect.

If the lattice defects generated by the ion implantation process are not eliminated, growth is performed by forming collective lattice defects and dislocations during a subsequent heat treatment process, for example, a source / drain activation heat treatment process or a capacitor dielectric film formation process. And move. In particular, it is moved to an edge portion of the device isolation film 12. In addition, when thermal stress exceeds a critical stress, dislocations are generated in the silicon single crystal substrate (J. F. Ziegler, "Ion implantation science and technology", pp. 63-92, Academic press, 1988).

At this time, as the gate channel length L _gate of the transistor is reduced, it is very important to reduce the depth of the source / drain junction in order to suppress the short channel effect of the transistor as much as possible. An energy of about 3 eV to 4 eV is required to diffuse impurities implanted in the ion implantation process, and about 5 eV is required to remove lattice defects (such as interstitial and vacancy). The diffusion distance L is L ∝ (D × T) ^1/2 (D: diffusion coefficient, T: time), which is proportional to time.

In order to remove at least the lattice defects as described above and to suppress the diffusion of impurities as much as possible, the rapid heat treatment process is preferably performed for about 2 seconds to 200 seconds, in a temperature range of 800 ° C to 1200 ° C.

In addition, the rapid heat treatment process is performed in an inert gas atmosphere such as oxygen (O 2) atmosphere, Ar, or nitrogen (N 2) atmosphere to ammonia (NH 3) atmosphere.

5 is an enlarged view of reference numeral 20 of FIG. 3D.

As the rapid heat treatment process is performed in the atmosphere, as illustrated in FIG. 5, an insulating film 22, such as an oxide film or a nitride film, is formed on a damaged portion of the gate insulating film 16, thereby healing the gate insulating film 16.

In the case of the oxygen atmosphere, since a new defect (interstitial, etc.) may be generated as the oxidation occurs on the surface of the silicon single crystal, it is performed in the inert gas atmosphere or the reactive nitrogen atmosphere or the ammonia atmosphere in which relatively new lattice defects are not generated. It is more preferable.

As described above, the stresses and lattice defects generated in the silicon single crystal substrate are eliminated, thereby preventing them from growing and moving to collective lattice defects and dislocations during subsequent heat treatment. Thus, as in the prior art, collective lattice defects and dislocations are prevented from being present in the depletion region of the p / n junction, resulting in abnormal p / n junction characteristics.

Finally, gate spacers 24 are formed on both sidewalls of the gate electrodes 18a and 18b. The gate spacer 24 is formed of an oxide film, a nitride film, or the like. High concentration impurity ions are implanted into the active regions on both sides of the gate spacer 24. Then, high concentration source / drain regions 26a and 26b, for example, n + type source / drain regions 26a and p + type source / drain regions 26b are formed in the active region, respectively, as shown in FIG. 3E. , Transistors are formed. In this case, low concentration impurity ions are implanted to form a lightly doped drain (LDD) on active regions on both sides of the gate electrodes 18a and 18b before the gate spacers 24 are formed.

FIG. 6 is a graph showing reverse bias current versus reverse bias voltage of a p / n junction according to the prior art and the present invention.

Referring to FIG. 6, when reverse bias is applied to a p + / n junction, the conventional graph 2 exhibits abnormal bonding characteristics, while the graph 30 of the present invention in which the rapid heat treatment process is performed shows normal bonding characteristics.

According to the present invention, by performing a rapid heat treatment process after the formation of the gate electrode, it is possible to heal the damage of the gate oxide film on both lower sides of the gate electrode, and at the same time to remove the stress and defects in the substrate, thereby preventing the bonding damage, and thus The quality can be improved and the junction leakage current can be minimized.

Claims (10)

Forming an isolation layer to define an active region and an inactive region on the semiconductor substrate; Implanting impurity ions into the active region to form at least one impurity region; Forming a gate electrode on the active region with a gate insulating layer interposed therebetween; And a rapid thermal process of the semiconductor substrate to remove stresses and defects in the substrate generated during the isolation of the device isolation film and the impurity ion implantation. The method of claim 1, And the device isolation film is formed by a shallow trench isolation method. The method of claim 1, The impurity ion implantation may be any one of well ion implantation, channel stop ion implantation, and threshold voltage controlled ion implantation. The method of claim 1, The rapid heat treatment is performed in a semiconductor (O 2) atmosphere. The method of claim 1, The rapid heat treatment is carried out in an inert gas atmosphere such as Ar. The method of claim 1, The rapid heat treatment is performed in a nitrogen (N 2) atmosphere. The method of claim 1, The rapid heat treatment is performed in ammonia (NH 3) atmosphere. The method of claim 1, The rapid heat treatment is carried out under a condition that at least the lattice defect is removed and the diffusion of impurity ions is suppressed as much as possible. The method according to claim 1 or 8, The rapid heat treatment is performed for about 2 seconds to 200 seconds in a temperature range of 800 ℃ to 1200 ℃. The method of claim 1, The rapid heat treatment is a method for manufacturing a semiconductor device that cures damage to gate insulating films under both gate electrodes generated when the gate electrode is formed.