KR20000053450A - Method of forming a transistor with improved hot carrier degradation - Google Patents

Abstract

PURPOSE: A method for fabricating a transistor is provided which reduces the hot carrier degradation. CONSTITUTION: A method for fabricating a transistor reducing hot carrier degradation is provided. An active device region(18) is formed on a silicon substrate. A gate conductor region(20) is formed and has gate side walls, and is separated by a gate oxide layer on a channel region defined within source and drain regions. A lightly doped drain structure and a gate side wall spacer are formed. The drain region is annealed at an interface located between the lightly doped drain structure and the gate oxide in the drain region with an amount sufficient to combine nitrogen with silicon in an atmosphere having at least one of NO, NH3 or N2O.

Description

Method of forming a transistor with improved hot carrier degradation

The present invention relates to a method of manufacturing a transistor, and more particularly, to a method of manufacturing a transistor with reduced hot carrier degradation.

A metal oxide semiconductor (MOS) transistor includes a source and drain region and a gate region normally separated by a dielectric over a channel region defined between the source and drain regions. Source and drain regions are often doped to form deep junctions. When a voltage is applied to the gate and the voltage exceeds a certain threshold, the channel between the source and drain becomes conductive and the transistor turns on, causing current to flow from the source to the drain.

However, transistors are often damaged from what is known as hot carrier injection by high-speed electrons impacting the silicon / substrate interface formed between the source and the gate, such as silicon dioxide and silicon interface. These phenomena can cause excessive oxide degradation. The term 'hot carrier' refers to high energy electrons, ie "hot." Sometimes called hot carrier aging or hot carrier degradation.

Hot carrier injection or degradation is formed when the kinetic energy of charged carriers, such as holes or electrons, increases as carriers are accelerated through large potential gradients and trapped in the gate dielectric. This large potential increase and decrease is called the maximum electric field ("E _M ") that occurs near the drain during the saturation operation of the transistor. This large electric field stands out at the side junction of the drain adjacent to the channel. When hot carriers move through the drain, the hot carriers lose their energy by a process called impingement ionization. As a result, an electron-hole pair is created, moving to the gate dielectric near the drain junction and injected into the gate dielectric. The electron trap can form a net negative charge density in the gate dielectric. This may accumulate overtime causing the transistor threshold voltage to change from its design specification.

To overcome these problems with hot carrier degradation, alternative drain structures known as lightly doped drains (“LDDs”) have been envisioned. Although the drain structure is very important, it is often formed in both the source and drain regions to adapt the semiconductor fabrication process. The lightly doped drain structure absorbs the potential into the drain and reduces the potential gradient near the drain during the saturation operation of the transistor.

Typical lightly doped drain structures have a low concentration of impurities aligned in the gate conductor region, followed by more doped regions aligned with the gate conductor region in which sidewall spacers are formed. The oblique junction formed by the impurity sensitization creates an interface between the lightly doped drain structure and the channel, and also creates an interface between the lightly doped drain structure and the source / drain region. Generally, lightly doped drain structures are formed simultaneously in both the source and drain regions to facilitate processing. Usually, as is well known to those skilled in the art, subsequent annealing steps follow. Even so, in the formation of a lightly doped drain structure, electron energy causes problems at the junction of the structure. There are various types of MOS structures, including modified lightly doped drain structures, and fabrication methods to reduce hot carrier effects. Examples including these structures and methods are disclosed in US Pat. Nos. 5,827,769, 5,847,428, 5,882,974, 5,920,782, the disclosures of which are hereby incorporated by reference in their entirety.

It is therefore an object of the present invention to provide a method of manufacturing a transistor with reduced hot carriers that does not add subsequent processing steps.

It is another object of the present invention to provide a method of manufacturing a transistor with reduced hot carrier degradation that can be performed by low temperature processing during annealing, for example, without adding a processing step.

1 is a schematic cross-sectional view of a silicon substrate illustrating the formation of a shallow trench to separate active device regions.

FIG. 2 is another schematic partial cross-sectional view of a silicon substrate showing the formation of gate conductor regions separated by a gate oxide layer over a channel region defined between source and drain regions, with gate sidewalls;

3 is another schematic side view illustrating the lightly doped drain structure and source and drain regions doped with an amount of impurities sufficient to form a gate spacer.

4 is another schematic cross-sectional view illustrating an anneal step and an etched dielectric oxide layer forming spacers extending vertically along gate sidewalls with the doped source and drain regions extending deeper than lightly doped drain structures;

5 shows an enlarged view of the interface located between the gate oxide and the lightly doped drain structure in the drain region, showing nitrogen bonded in the region.

* Description of the symbols for the main parts of the drawings *

12 trench 16 silicon dioxide

18: active device region 20: gate conductor region

In accordance with the present invention, a method of manufacturing a transistor with reduced hot carrier degradation is described herein. An active device region is formed in the silicon substrate. A gate conductor region is formed, having a gate sidewall, which is separated and spaced apart by a gate oxide layer over a channel region defined between a source and a drain region in the active device region. The source and drain regions are doped in the silicon substrate in an amount sufficient to form a lightly doped drain structure having a silicon / silicon dioxide interface with the gate oxide layer. A dielectric oxide layer is deposited over the gate conductor region and the source and drain regions. The deposited dielectric oxide layer is etched to form spacers extending vertically along the gate sidewalls. The source and drain regions have a higher doping concentration than lightly doped drain structures and are doped in an amount sufficient to form deeply extending source and drain implants. The drain region combines nitrogen and silicon at the interface located between the lightly doped drain structure in the drain region and the gate oxide in an atmosphere having at least one of nitrogen oxides (NO), ammonia (NH ₃ ) or nitrogen monoxide (N ₂ O). Annealed in an amount sufficient to

During annealing, the entire active device region may be annealed to couple nitrogen and silicon at an interface located between the lightly doped drain structure in the source and drain regions and the gate oxide. The annealing can take place at a pressure of about 1 mTORR to 10 atm, in particular at a pressure of about 1 atm. Annealing may occur at temperatures between about 600 and 950 ° C. The gas stream is preferably formed at a rate of about 1% to 100% during the annealing step, and at a rate of about 50% in one aspect of the invention. Annealing can also occur for about 1 minute to about 10 hours, preferably for about 10 minutes. Spacers can be formed by anisotropically removing the oxide layer to form the spacers.

In another aspect of the invention, the active device region is formed on the silicon substrate by shallow trench isolation. The gate oxide layer is formed as a silicon dioxide layer over the channel region. The gate conductor region includes a tungsten silicide contact and a polysilicon layer overlying the gate oxide layer. The source and drain regions of the silicon substrate are doped with an amount of impurities sufficient to form a lightly doped drain structure having a silicon / silicon dioxide interface with the gate oxide layer.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of the invention which is understood upon consideration of the accompanying drawings.

The present invention is advantageous because it allows mixing of high concentrations of nitrogen at the interface located between the lightly doped drain structure and the gate oxide to reduce hot carrier injection and degradation. High concentrations of nitrogen can be embodied in low cost low temperature treatments within the addition process step and during the annealing process, as used in the formation of integrated MOS circuits.

1 illustrates a silicon substrate 10 in which a trench 12 is formed by techniques known to those skilled in the art. A layer (not shown), such as silicon dioxide, is then deposited over the entire wafer surface. Silicon dioxide is then polished or treated by techniques known to those skilled in the art to form shallow trench isolation regions 14 filled with silicon dioxide 16 and to form active device regions 18 on silicon substrate 10. do. Through suitable photolithographic steps and drying of the various layers, a gate conductor region 20 is formed on the substrate 10 and extends substantially perpendicular to the gate sidewall 22. Gate conductor region 20 is formed by, for example, a silicon dioxide layer and is deposited over a channel region defined between active source and drain regions 28 and 30 in active device region 18, for example. Are separated by). In the embodiment shown in FIG. 2, the gate conductor region 20 includes a tungsten silicide contact 32 and a polysilicon layer 34 positioned over the gate oxide layer 24 and below the tungsten silicide contact 32.

The first doping in the source and drain regions 28 and 30 form what will be the lightly doped drain structures 36 and 38. The degree of doping can be determined by techniques known to those skilled in the art. The spacer 40 is formed as shown in FIG. 3 by generally depositing a conformal oxide layer by CVD treatment or the like as known to those skilled in the art. The oxide layer is then substantially etched by anisotropic etching to remove the oxide layer from the horizontal plane substantially faster than the oxide removed from the vertical plane, leaving the spacer 40 on the vertical sidewall 22 of the gate conductor region 20. .

The spacer 40 is formed so that the spacer 40 has a lightly doped drain structure 36, 38 with appropriate dimensions with respect to the more heavily doped implants 42, 44 after the spacer 40 has been etched. In each source and drain formed at (Fig. 4).

After spacer etching, the source and drain regions 28 and 30 are sufficient to form source and drain implants 42 and 44 having deeper impurities and higher concentrations of impurities than the lightly doped drain structures 36 and 38. Doped in positive amounts. As is well known to those skilled in the art, implanting impurity atoms to form source and drain implants results in damage to the wafer crystal structure that is corrected by the annealing process. The present invention is advantageous because it uses an annealing step to mix high concentrations of nitrogen in the interface between the lightly doped drain structure and the gate oxide structure. FIG. 5 shows nitrogen 50 mixed into the interfacial region 52 between the lightly doped drain structure and the gate oxide layer.

The entire active device region can also be annealed and the source region as well as the drain region can also contain the mixed nitrogen.

The drain region 30 is between the gate oxide 24 and the lightly doped drain structure 38 in the drain region in an atmosphere having at least one of nitrogen oxides (NO), ammonia (NH ₃ ) or nitrogen monoxide (N ₂ O). The silicon / silicon dioxide interface located at annealed in an amount sufficient to bond nitrogen and silicon. In general, the annealing occurs at a pressure of about 1 atmosphere, but can occur in a pressure range of as low as 1 mTORR to as high as about 10 atmospheres, depending on the requirements and end use determined by those skilled in the art. The temperature is generally between about 600 and about 950 ° C. and the gas flow rate is about 1% to 100%, generally about 50%, during the annealing step. Annealing generally occurs for about 10 minutes, but can occur for about 1 minute to about 10 hours. The amount of nitrogen mixed is about 0.5% to 3.0%.

More nitrogen can be mixed at lower temperatures when annealed with NO than N ₂ O. Preferably the annealing temperature is in the range of about 600 to about 850 ° C, preferably about 700 ° C.

It is clear that the present invention is advantageous as it allows for high nitrogen concentrations and mixing without additional processing steps and occurs at low temperature annealing treatments at low cost. Therefore, hot carrier degradation is reduced.

Many modifications and other embodiments of the invention will come to mind to one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Thus, it is to be understood that the invention is not limited to the disclosed feature embodiments but variations and embodiments are within the scope of the dependent claims.

The present invention provides a method of manufacturing a transistor with reduced hot carriers that does not add subsequent processing steps, and manufactures transistors with reduced hot carrier degradation that do not add processing steps, such as can be performed with low temperature processing during annealing. Provide a way to.

Claims (20)

As a method of manufacturing a transistor with improved hot carrier deterioration, Forming an active device on the silicon substrate, Forming a gate conductor region separated by a gate oxide layer over the channel region defined between the source and drain regions in the active device region and having gate sidewalls; Doping the source and drain regions of the silicon substrate with an amount of impurities sufficient to form a lightly doped drain structure having an interface with a gate oxide layer; Depositing a dielectric oxide layer over the gate conductor region and source and drain regions; Etching the deposited dielectric oxide layer to form spacers extending vertically along the gate sidewalls; Doping the source and drain regions in an amount sufficient to form a source and drain implant that extends deeper than the lightly doped drain structure and has a higher concentration of impurities; In an atmosphere having at least one of nitrogen oxides (NO), ammonia (NH ₃ ) or nitrogen monoxide (N ₂ O) nitrogen and silicon at the interface located between the lightly doped drain structure in the drain region and the gate oxide Annealing the drain region in an amount sufficient to couple. The method of claim 1, Annealing the entire active device region during the annealing step. The method of claim 1, Annealing at a pressure of about 1 mTorr to about 10 atmospheres. The method of claim 3, wherein Annealing at a pressure of about 1 atmosphere. The method of claim 1, Annealing at a temperature between about 600 and 950 ° C. The method of claim 1, Forming a gas flow rate of about 1% to 100% during the annealing step. The method of claim 6, Said gas flow rate is about 50%. The method of claim 1, Anneal for a treatment time of about 1 minute to about 10 hours. The method of claim 8, Anneal for a treatment time of about 10 minutes. The method of claim 1, And anisotropically removing the oxide layer to form the spacers. As a method of manufacturing a transistor with improved hot carrier deterioration, Forming an active device on the silicon substrate by shallow trench isolation; Forming a gate conductor region having gate sidewalls spaced apart by a gate oxide layer formed as a silicon dioxide layer over a channel region defined between the source and drain regions in the active device region, the gate conductor region being tungsten silicide Forming a gate conductor region comprising a contact portion and a polysilicon layer overlying the gate oxide layer; Doping the source and drain regions of the silicon substrate with an amount of impurities sufficient to form a lightly doped drain structure having a silicon / silicon dioxide interface with a gate oxide layer; Depositing a dielectric oxide layer over the gate conductor region and source and drain regions; Etching the deposited dielectric oxide layer to form spacers extending vertically along the gate sidewalls; Doping the source and drain regions in an amount sufficient to form a source and drain implant that extends deeper than the lightly doped drain structure and has a higher concentration of impurities; At the silicon / silicon dioxide interface located between the gate oxide and the lightly doped drain structure in the drain region in an atmosphere having at least one of nitrogen oxides (NO), ammonia (NH ₃ ) or nitrogen monoxide (N ₂ O). Annealing said drain region in an amount sufficient to combine nitrogen and silicon. The method of claim 11, Annealing the entire active device region during the annealing step. The method of claim 11, Annealing at a pressure of about 1 mTorr to about 10 atmospheres. The method of claim 13, Annealing at a pressure of about 1 atmosphere. The method of claim 11, Annealing at a temperature between about 600 and 950 ° C. The method of claim 11, Forming a gas flow rate of about 1% to 100% during the annealing step. The method of claim 16, Said gas flow rate is about 50%. The method of claim 11, Anneal for a treatment time of about 1 minute to about 10 hours. The method of claim 18, Anneal for a treatment time of about 10 minutes. The method of claim 11, And anisotropically removing the oxide layer to form the spacers.