JP3875040B2 - Semiconductor substrate and manufacturing method thereof, and semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor substrate and a method for manufacturing the same, and a semiconductor device and a method for manufacturing the same, and more particularly, a semiconductor substrate capable of using a strained superlattice heterostructure in a silicon substrate and a SiGe layer as a channel, and the manufacturing thereof. The present invention relates to a method, a semiconductor device, and a manufacturing method thereof.
[0002]
[Prior art]
In a semiconductor device, improving the mobility of electrons moving through a semiconductor element is one of effective means for improving the performance.
However, in general, in a semiconductor device formed on a substrate made of a silicon single crystal, the upper limit of mobility of electrons moving through the silicon single crystal is determined based on the physical properties of the silicon single crystal.
On the other hand, in recent years, it has been reported that the mobility of electrons is improved in a strained silicon crystal than in a strainless silicon crystal.
For this reason, in order to obtain a semiconductor element such as a transistor with improved electron mobility, it is effective to use a silicon crystal layer having sufficient distortion and a low defect density in its operating region. is there.
Therefore, for example, a SiGe crystal layer having a large lattice constant relative to silicon is stacked on a silicon substrate, and this stacked structure is used as a virtual substrate, and a silicon crystal layer is grown thereon.
It should be noted that the SiGe crystal layer used in this virtual substrate needs to have sufficiently relaxed strain on the uppermost surface.
[0003]
Normally, when a SiGe crystal layer is grown on a silicon single crystal substrate, the SiGe crystal layer is formed in a state that includes strain up to the critical film thickness depending on the concentration of germanium. It is known that defects such as these are introduced and distortion is alleviated. Therefore, in order to obtain a SiGe crystal layer with relaxed strain, it is usually necessary to grow the SiGe crystal layer thicker than the critical film thickness.
In addition, in order to obtain a silicon crystal layer having a strain high enough to form a semiconductor element such as a transistor, it is necessary to reduce defects introduced during crystal formation, so at least a virtual substrate is formed. It is also necessary that the defect density be low on the outermost surface of the SiGe crystal layer. Thereby, the lattice constant can be further increased.
Therefore, an attempt has been made to form a virtual substrate having SiGe crystals with sufficiently reduced strain at the outermost surface and a low defect density.
For example, in Japanese Patent Laid-Open No. 5-129201, a germanium composition is gradually increased toward the surface to relax the lattice, and a SiGe crystal layer having a low defect density is formed, and a strained silicon crystal layer is formed thereon. The forming technique is described. Moreover, as a method for forming a SiGe layer with reduced strain and low defect density, a method as described below has been proposed.
[0004]
According to this method, as shown in FIG. 6, the first SiGe layer 402, the second SiGe layer 405, and the third SiGe layer 408 having a lattice constant larger than this are epitaxially grown on the silicon substrate 401 sequentially. Let Here, the SiGe layers 402, 405, and 408 have a large lattice constant as a graded composition that sequentially increases the germanium concentration. The film thickness of each SiGe layer 402, 405, 408 is set to a critical film thickness or less depending on the germanium concentration.
Next, by the heat treatment at 350 ° C., the strain existing in the layer is removed by using misfit dislocations caused by lattice matching as nuclei. Thereby, the SiGe layer 408 having a low defect density and relaxed strain can be obtained.
Thereafter, semiconductor elements such as a diode 409 and a transistor 410 are formed on the uppermost SiGe layer 405.
[0005]
[Problems to be solved by the invention]
In the above method, it is necessary to form a plurality of epitaxial layers having graded compositions in order to obtain SiGe crystals with reduced defect density with relaxed strain. In addition, in order to grow a silicon crystal having a larger strain on the SiGe layer, a higher germanium concentration is required on the outermost surface of the SiGe layer as in the above method.
However, in consideration of defects, each SiGe layer, particularly the outermost SiGe layer, cannot be made thicker than the critical film thickness corresponding to each germanium concentration SiGe layer. Therefore, in order to obtain a SiGe layer having a high germanium concentration on the outermost surface, it is necessary to stack a thicker SiGe layer having a thickness equal to or less than the critical thickness. For example, when a SiGe layer having a germanium concentration of 20% on the outermost surface is formed, if the germanium concentration is increased every 5%, epitaxial growth is not performed 8 times when the germanium concentration is 40%. must not. For this reason, it takes a long time to form the SiGe crystal layer, which is a virtual substrate, and there is a problem that the throughput is deteriorated and the productivity is poor, which makes mass production difficult.
The present invention has been made in view of the above problems, and a semiconductor substrate that can improve the mobility of both electrons and holes more easily and inexpensively using a normal silicon single crystal substrate, An object of the present invention is to provide a semiconductor device and a manufacturing method thereof.
[0006]
[Means for Solving the Problems]
According to the present invention, there is provided a semiconductor substrate in which a SiGe layer containing strain is laminated on a silicon substrate, and in a partial region of the SiGe layer, a part of the SiGe layer is formed in the SiGe layer. Thus, there is provided a semiconductor substrate having a defect layer accompanying the introduction of an electrically neutral element, including a strain under the defect layer, and the strain being relaxed on the defect layer.
Also, (a) by laminating a SiGe layer on a silicon substrate, a SiGe layer containing strain is formed,
(B) forming a defect layer in a part of the SiGe layer by ion-implanting an electrically neutral element in the SiGe layer into a part of the SiGe layer and performing a heat treatment; There is provided a method for manufacturing a semiconductor substrate that relieves strain of a SiGe layer in a region through which ions have passed.
[0007]
Furthermore, according to the present invention, the semiconductor substrate,
In some part of that layer SiGe layer with relaxed strain Area When In all layers SiGe layer containing strain Area An element isolation region formed in a region between and
An NMOS transistor formed on the SiGe layer in the strain-relaxed region and comprising a gate insulating film, a gate electrode, and a source / drain region;
A semiconductor device is provided that has a gate insulating film, a gate electrode, and a PMOS transistor formed of a source / drain region, which is formed on a SiGe layer in a region containing strain.
In addition, after forming the semiconductor substrate,
(C) In some part of that layer SiGe layer with relaxed strain Area When In all layers SiGe layer containing strain Area Forming an element isolation region in the region between
(D) A semiconductor device in which an NMOS transistor and a PMOS transistor each including a gate insulating film, a gate electrode, and a source / drain region are formed on the SiGe layer in the strain-relieved region and the SiGe layer in the region containing the strain, respectively. A manufacturing method is provided.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
The semiconductor substrate of the present invention is mainly composed of a silicon substrate and a SiGe layer formed thereon.
The silicon substrate is not particularly limited as long as it is normally used for manufacturing a semiconductor device, and amorphous, microcrystal, single crystal, polycrystal, and two or more of these crystal states are mixed. A substrate made of silicon can be mentioned. Further, an SOI substrate having a surface silicon layer made of these silicon, a multilayer SOI substrate, or the like may be used. Among these, a substrate made of single crystal silicon is preferable.
[0009]
The SiGe layer formed thereon is preferably substantially formed as a crystal layer. Here, the crystal layer includes a microcrystal, a polycrystal, a single crystal, or a mixed state thereof. The SiGe layer is a layer having a larger lattice constant than silicon due to germanium. When such a SiGe layer is formed on the silicon substrate, the SiGe layer is distorted based on the difference between these lattice constants, and particularly compressive strain is included.
The composition ratio of silicon and germanium in the SiGe layer is not particularly limited, but about 9: 1 to 7: 3 is appropriate. This composition ratio may vary within the above range continuously or stepwise in the film thickness direction of the SiGe layer, but is preferably uniform. Further, it may be partially different in the layer surface (in-plane) direction, but is preferably uniform. The film thickness of the SiGe layer is preferably not more than the critical film thickness of germanium concentration in order to avoid the introduction of unintended defects in the SiGe layer, and for example, about 100 to 300 nm is appropriate.
[0010]
This SiGe layer has a defect layer accompanying the introduction of an electrically neutral element in the SiGe layer in a part of the region and in a part of the inside of the layer. This defect layer is a layer that can be distinguished from a layer having a defect that is unintentionally introduced in the formation of the SiGe layer. Specifically, the defect layer is actively introduced by ion implantation, subsequent heat treatment, or the like. , Means a layer with accumulated defects. The position where the defect layer is formed can be adjusted according to the film thickness of the SiGe layer, and for example, it is appropriate to be between about 50 and 100 nm from the surface of the SiGe layer. Moreover, the thickness is about 30-50 nm. The defect layer may be formed in the entire region of the SiGe layer in the surface (in-plane) direction, but depending on the type, characteristics, performance, etc. of the semiconductor device formed on the semiconductor substrate of the present invention, It may be formed in a part thereof, or may be formed in one region or a plurality of regions (for example, stripes, islands, etc.). When formed in a plurality of regions, they may be formed at different depths and different thicknesses within the SiGe layer.
[0011]
Elements that are electrically neutral in the SiGe layer introduced to form the defect layer include hydrogen; elements belonging to Group 4 of the periodic table such as carbon, silicon, germanium, and tin; He, Ne, Examples include elements belonging to Group 0 such as Ar, Kr, and Xe.
In the SiGe layer, strain is included under the defect layer. In other words, the SiGe layer formed on the silicon substrate inherently contains strain due to the difference in lattice constant between the two, so that the contained strain remains under the defect layer. Means that.
On the other hand, in the SiGe layer, strain is relaxed on the defect layer. The relaxation of strain here means a state in which stress due to inherently contained strain is reduced. Specifically, when ions are implanted into the SiGe layer, it is converted to amorphous due to crystal dislocation, crystallinity breakage, etc., and further, the crystallinity is restored by heat treatment, and defects are converted into defect layers. accumulate. Therefore, the defect is almost recovered or removed in the upper part of the defect layer.
The thickness of the portion including these strains or the strains being relaxed can be appropriately adjusted depending on the thickness of the SiGe layer, the position and thickness of the defect layer.
[0012]
On the semiconductor substrate of the present invention, that is, on the SiGe layer, one or more semiconductor layers may be further laminated. Here, as the semiconductor layer, a silicon layer, a germanium layer, a SiC layer, a SiGe layer, a SiGeC layer, a group IV element semiconductor such as GeC and a mixed semiconductor, and a III-V group such as GaAs, InP, ZnSe, or II- Group VI compound semiconductor layers may be mentioned. In particular, when SiC is used, a larger strain is applied to the SiGe layer, so that the mobility of electrons and holes can be further improved. When Ge is used, SiGe is used. Since compressive stress is generated on the layer, only the mobility of holes is improved, but Ge is preferable because the mobility of electrons and holes is larger than that of Si. Note that the semiconductor layer may be a microcrystal, a polycrystal, a single crystal, or the like, but is preferably a single crystal layer.
The film thickness of the semiconductor layer formed on the SiGe layer can be appropriately adjusted according to the characteristics of the substrate to be obtained, the type and performance of the semiconductor device formed thereon, and is, for example, 10 to 30 nm. Degree.
[0013]
The semiconductor device of the present invention is formed on the substrate in which an element isolation region is formed in a region between the SiGe layer in which the strain is relaxed and the SiGe layer containing the strain. Examples of the element isolation region include element isolation regions known in the art such as a LOCOS film, an STI (Shallow Trench Isolation) film, and a trench element isolation film.
Examples of the semiconductor device include various semiconductor devices such as a MOS transistor, a diode, a capacitor, and a bipolar transistor. Among these, a CMOS transistor composed of a PMOS transistor and an NMOS transistor is preferable. In this case, an NMOS transistor is formed on the SiGe layer in the region where the strain is relaxed, and a PMOS transistor is formed on the SiGe layer in the region including the strain. Since performance can be improved, it is preferable.
[0014]
The gate oxide film, the gate electrode, and the source / drain region that constitute the MOS transistor can be formed by a method that is usually formed depending on the film thickness, material, and the like that are usually used to form a semiconductor device such as a MOS transistor. it can. In addition, sidewall spacers may be formed on the gate electrode, and the source / drain regions may have an LDD structure or a DDD structure. Further, the source / drain regions may be formed by laminating semiconductor layers on both sides of the gate electrode and the sidewall spacer, and the semiconductor layers. Examples of the semiconductor layer in this case include the same semiconductor layer as described above, but a silicon layer is preferable. The film thickness of the semiconductor layer constituting the source / drain region can be appropriately adjusted according to the performance of the MOS transistor to be obtained.
[0015]
In the method for manufacturing a semiconductor substrate of the present invention, first, in step (a), a SiGe layer is laminated on a silicon substrate. Thus, as described above, the SiGe layer is distorted due to the difference in lattice constant between silicon and SiGe. Here, the SiGe layer can be formed by a known method such as an epitaxial growth method or a CVD method.
Next, in step (b), an electrically neutral element in the SiGe layer is ion-implanted into a partial region of the SiGe layer, and heat treatment is performed. Ion implantation conditions, such as dose and implantation energy, can be appropriately set according to the types of the elements described above. For example, 1 × 10 ¹⁵ ~ 1x10 ¹⁷ cm ^-2 Dosage of a certain degree, such that the implantation peak comes to the position where the above-mentioned defect layer is to be formed, specifically, implantation energy at which the implantation depth is about 50 to 100 nm from the surface, more specifically Is an implantation energy of about 20 to 300 keV. In this implantation, in order to reduce the implantation depth, a cover film made of an insulating film such as an oxide film or a nitride film may be formed on the surface of the SiGe layer, and then ion implantation may be performed through the cover film. .
[0016]
For the heat treatment, methods and conditions known in the art can be used. Specifically, furnace annealing, lamp annealing, RTA, etc. are mentioned, and it is performed at a temperature range of 600 to 900 ° C. for about 5 to 30 minutes under an air atmosphere, a nitrogen gas atmosphere, an oxygen gas atmosphere, a hydrogen gas atmosphere or the like. be able to. In this heat treatment, the cover film as described above may be attached and heat treated in consideration of surface flattening of the SiGe layer. Thereby, while forming a defect layer in a part in SiGe layer, the crystallinity of the SiGe layer in the area | region which ion passed can be recovered, and distortion can be relieved.
In addition, after performing the step (b), one or more semiconductor layers may be further stacked on the obtained SiGe layer. The semiconductor layer stacking method here can be performed in the same manner as described above.
[0017]
In the present invention, after forming the semiconductor substrate as described above, in step (c), an element isolation region is formed in a region between the strain-relieved SiGe layer and the strained SiGe layer. . In this case, the element isolation region can be formed by various methods such as LOCOS method, STI method, trench element isolation method and the like.
In step (d), an NMOS transistor and a PMOS transistor each including a gate insulating film, a gate electrode, and source / drain regions are formed. As a method for forming the MOS transistor, a method known in this field can be used.
When the source / drain regions are formed by semiconductor layers located on both sides of the gate electrode and the sidewall spacer, after the sidewall spacer is formed on the side wall of the gate electrode, the semiconductor is selectively epitaxially grown thereon. By stacking the layers, the source / drain regions can be formed by a known method, that is, ion implantation or the like. The introduction of impurities into the source / drain regions includes ion implantation, a method of epitaxial growth while doping impurities, and a method of solid phase diffusion or vapor phase diffusion after the semiconductor layer is formed by epitaxial growth.
Below, the semiconductor substrate of this invention, a semiconductor device, and those manufacturing methods are demonstrated in detail based on drawing.
[0018]
Embodiment 1
In the semiconductor substrate of this embodiment, as shown in FIG. 3 (k), a SiGe crystal layer 102 is stacked on a p-type single crystal silicon substrate 101 in a state where strain is included. The SiGe crystal layer 102 has a SiGe layer 104 containing a large number of defects in a part of the SiGe crystal layer 102, and an undistorted or relaxed SiGe crystal layer 106 is formed on the SiGe layer 104. The SiGe crystal layer 102 in the state where the strain is included is disposed below the layer.
Further, in such a semiconductor substrate, an element isolation region 111 is formed between the first SiGe crystal layer 106 without strain and the SiGe crystal layer 102 containing the strain, and the SiGe crystal layer 106 without strain is formed. A strained silicon crystal layer 109 is formed thereon, and a strained silicon crystal layer 110 is formed on the strained SiGe crystal layer 102. A gate electrode is formed on the silicon crystal layers 109 and 110 via a gate insulating film 112. Further, source / drain regions 118 and 119 are formed on the SiGe crystal layers 106 and 102 and the silicon crystal layers 109 and 110, respectively. Are formed to constitute NMOS and PMOS transistors.
The semiconductor substrate and the semiconductor device can be formed by the following method.
[0019]
First, as shown in FIG. 1A, organic heavy metals on the surface of the p-type single crystal silicon substrate 101 are removed by a cleaning process, and further, natural oxidation formed on the surface of the silicon substrate 101 using a dilute HF solution. Remove the membrane.
Next, as shown in FIG. 1B, a silicon substrate 101 is introduced into a rapid heating CVD apparatus (RT-CVD apparatus), and heat treatment is performed at 850 to 1000 ° C. in a hydrogen gas atmosphere. The natural oxide film formed on the surface of the substrate 101 is removed. Thereafter, the temperature of the silicon substrate 101 is set to 500 ° C., and the SiGe crystal layer 102 having a film thickness of 100 nm and a germanium concentration of 20% is formed as a virtual substrate. Since the critical film thickness decreases as the germanium concentration in the SiGe layer increases or the substrate temperature increases, the film thickness of the SiGe crystal layer 102 exceeds the critical film thickness at this concentration and the substrate temperature of about 300 nm. It is set not to be. For this reason, the SiGe crystal layer 102 grows in a state including strain, dislocations for relaxing the strain are not introduced, and a high-quality crystal layer is obtained.
[0020]
Subsequently, as shown in FIG. 1C, the PMOS transistor formation region is covered with a resist pattern 103 formed in a desired shape using a photolithography technique, and only the NMOS transistor formation region has a large current ion. 1 × 10 hydrogen with injector ¹⁵ ~ 5x10 ¹⁶ cm ^-2 The energy is set so that the implantation depth is about 50 to 100 nm from the surface. As a result, the crystallinity is destroyed in the region through which hydrogen ions have passed, and the SiGe amorphous layer 105 is formed. The implanted hydrogen remains at the interface between the SiGe crystal layer 102 and the SiGe amorphous layer 105 (FIG. 1 (d)). Note that hydrogen is electrically neutral in the SiGe crystal layer 102 and the SiGe amorphous layer 105, and thus has no electrical influence when a transistor is manufactured.
[0021]
As shown in FIG. 2E, after the resist pattern 103 is removed, heat treatment is performed in a temperature range of 600 to 900 ° C. for 5 to 30 minutes in a nitrogen atmosphere. As a result, as shown in FIG. 2F, the SiGe amorphous layer 105 recovers its crystallinity using the SiGe crystal layer 102 as a seed, and is converted into a first SiGe crystal layer 106 without strain. Further, at the interface between the SiGe crystal layer 102 and the SiGe amorphous layer 105, crystal defects are accumulated due to hydrogen remaining at the interface, and the SiGe layer 104 containing many defects is formed. That is, the strain included in the SiGe crystal layer 102 is released by the SiGe layer 104 containing many defects, and the recrystallized SiGe crystal layer 105 is in a state in which the strain is relaxed. It should be noted that the SiGe crystal layer 102 in the PMOS transistor formation region where implantation is not performed still contains strain.
Further, the natural oxide film formed on the surface of the SiGe crystal layers 102 and 106 is removed with a dilute HF solution, and the obtained silicon substrate 1 is again introduced into the RT-CVD apparatus, and 850 to 1000 in a hydrogen gas atmosphere. The natural oxide film formed on the surfaces of the SiGe crystal layers 102 and 106 when the apparatus is introduced is removed by heating to 0 ° C.
[0022]
Thereafter, as shown in FIG. 2G, silicon crystal layers 109 and 110 having a thickness of 20 nm are formed at 650.degree. The film thickness of the silicon crystal layers 109 and 110 is a critical film thickness (approximately about the difference in lattice constant between the silicon crystal layers 110 and 109 and the SiGe crystal layers 102 and 106 having a germanium concentration of 20% as a virtual substrate and the silicon crystal layers 110 and 109. Therefore, the silicon crystal layers 109 and 110 having a defect density low enough to form a transistor can be formed. Note that since the lattice constant of the SiGe crystal layer 106 without strain is larger than the lattice constant of the silicon crystal layer 109 formed thereon, the silicon crystal layer 109 is formed in a state of being subjected to tensile stress. This stress improves the mobility of electrons in the strained silicon crystal layer 109. Further, the Si crystal layer 110 formed on the strained SiGe crystal layer 102 has no strain. That is, since the SiGe crystal layer 102 is formed on the silicon substrate 101, the lattice constant of the SiGe crystal layer 102 is close to that of silicon, and therefore close to the lattice constant of the silicon crystal layer 110 formed thereon. Does not have
[0023]
A CMOS transistor is formed on the silicon crystal layer 110 thus obtained by applying a normal field effect transistor manufacturing technique. That is, as shown in FIG. 2 (h), the element isolation region 111 is formed by using the STI technique, and as shown in FIG. 3 (i), the silicon oxide film 112 and the polycrystalline silicon serving as a gate insulating film are formed. A layer 113 is deposited, and a resist pattern 114 having a desired shape is formed thereon by using a photolithography technique.
Subsequently, as shown in FIG. 3J, the polycrystalline silicon layer 113 is patterned using the resist pattern 114 as a mask to form gate electrodes in the NMOS transistor formation region and the PMOS transistor formation region, respectively. Side wall spacers 116 are formed on the side walls of the obtained gate electrode.
Thereafter, as shown in FIG. 3K, source / drain regions 118 and 119 are formed by ion implantation in the NMOS transistor formation region and the PMOS transistor formation region, respectively, using a resist pattern having a desired shape. .
[0024]
Embodiment 2
First, a SiGe crystal layer 202 containing a germanium concentration of 20% and strain is formed on a p-type single crystal silicon substrate 201 by the same method as in the first embodiment (FIGS. 1A to 2F). A first SiGe crystal layer 206 having no defects and a SiGe layer 204 containing many defects are formed.
Next, as shown in FIG. 4, second SiGe layers 207 and 208 having a film thickness of 150 nm and the same germanium concentration (20%) as the first SiGe layers 202 and 206 are formed. The second SiGe crystal layer 208 formed on the SiGe crystal layer 202 containing the strain is in a strained state, and the second SiGe layer 207 formed on the first SiGe crystal layer 206 without the strain is not strained. State.
[0025]
Thereafter, a CMOS transistor is formed in the same manner as in the first embodiment (FIGS. 2G to 3K).
In this manner, by providing the second SiGe crystal layers 207 and 208, for example, when a field effect (MOS) transistor or the like is manufactured, the SiGe layer 204 containing many defects can be easily isolated from the transistor operation region. Can do. That is, in the MOS transistor, when the depletion layer formed between the drain and the substrate overlaps the SiGe layer 204 containing many defects, a generated recombination current is generated in the SiGe layer 204 containing many defects, and thus a leakage current is generated. Will increase. Therefore, the leakage current can be prevented by forming the SiGe layer 204 containing many defects at a depth away from the depletion layer formed between the drain and the substrate.
[0026]
Embodiment 3
First, by a method similar to that of the first embodiment (FIGS. 1A to 2H), a SiGe crystal layer 302 containing a 20% germanium concentration and strain is formed on a p-type single crystal silicon substrate 301, A first SiGe crystal layer 306 having no defects, a SiGe layer 304 containing many defects, silicon crystal layers 309 and 310, and an element isolation region are formed.
Next, as shown in FIG. 5A, a silicon oxide film 312, a polycrystalline silicon layer 313, and a silicon oxide film 315 to be a gate insulating film are formed.
Thereafter, as shown in FIG. 5B, gate electrodes and sidewall spacers 316 are formed in the same manner as in the first embodiment (FIGS. 3I to 3J).
Subsequently, as shown in FIG. 5C, silicon crystal layers 317 are formed on both sides of the sidewall spacer 316 by selective epitaxial growth. Thereafter, in the same manner as in the first embodiment (FIG. 3K), source / drain regions are formed in the silicon crystal layer 317 by ion implantation.
Thereby, as in the second embodiment, the SiGe layer 304 containing many defects can be isolated from the transistor operation region.
It has been confirmed by Raman spectroscopic analysis that the strain of the SiGe layer can be relaxed even if the implantation depth peak at the time of hydrogen ion implantation is set in the silicon substrate.
[0027]
【The invention's effect】
According to the present invention, there is provided a semiconductor substrate in which a SiGe layer containing strain is stacked on a silicon substrate, and in a partial region of the SiGe layer, a part of the SiGe layer is included in the SiGe layer. Since it has a defect layer due to the introduction of electrically neutral elements, it contains strain under the defect layer, and strain is relaxed on the defect layer, so that the mobility of electrons can be improved on the same substrate. It is possible to easily coexist the layer in which the contributing strain is relaxed and the layer containing the strain contributing to the improvement in hole mobility by a thin SiGe layer in a flat state.
Further, when one or more semiconductor layers are stacked on the SiGe layer, the defect layer can be isolated from the operation region of the semiconductor device formed on the semiconductor substrate, and leakage current, etc. Therefore, it is possible to obtain a semiconductor substrate capable of providing a higher performance semiconductor device.
Furthermore, when the electrically neutral element in the SiGe layer is hydrogen, a Group 4 element of the periodic table, or an inert gas, the operation of the semiconductor device formed on the semiconductor substrate is affected. Without giving, it is possible to introduce a layer in which effective strain is relaxed into the semiconductor substrate.
[0028]
In addition, a defect layer can be effectively formed in a part of the SiGe layer by ion-implanting an electrically neutral element in the SiGe layer into a part of the SiGe layer and performing a heat treatment. In addition, the strain of the SiGe layer in the region where ions have passed can be relaxed, and a useful semiconductor device can be manufactured easily and in a short time without increasing the thickness of the SiGe layer. Thus, it is possible to increase the throughput and, in turn, mass production by increasing the efficiency of the productivity, and it becomes possible to manufacture a useful semiconductor substrate at a low cost.
Furthermore, in a semiconductor device using the semiconductor substrate, particularly a CMOS transistor, high mobility can be obtained for both electrons and holes at the same height on the same substrate, and high performance and high reliability can be obtained. .
In addition, when one or more semiconductor layers are stacked on the SiGe layer and an NMOS transistor and a PMOS transistor are formed on the semiconductor layer, the gate electrode has a sidewall spacer on its sidewall. And the source / drain region is formed by a semiconductor layer stacked on both sides of the gate electrode and the sidewall spacer formed on the SiGe layer or the semiconductor layer, Since the defect layer can be reliably isolated, a higher-performance semiconductor device can be obtained.
Furthermore, according to the method for manufacturing a semiconductor device of the present invention, a high-performance semiconductor device can be manufactured easily and in a short time, and mass production can be achieved by improving throughput and, in turn, improving productivity. It becomes possible to manufacture a useful semiconductor device.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view of a main part showing a semiconductor substrate and a semiconductor device of the present invention.
FIG. 2 is a schematic cross-sectional process diagram of the main part showing the method for manufacturing a semiconductor device of the present invention.
FIG. 3 is a schematic cross-sectional process diagram of the main part showing the method for manufacturing a semiconductor device of the present invention.
FIG. 4 is a schematic cross-sectional process diagram of a substantial part showing another embodiment of a method for producing a semiconductor device of the present invention.
FIG. 5 is a schematic cross-sectional process diagram of a substantial part showing still another embodiment of a method for producing a semiconductor device of the present invention.
FIG. 6 is a schematic cross-sectional view of a main part showing a conventional semiconductor device.
[Explanation of symbols]
101, 201, 301 Silicon substrate
102, 202, 302 SiGe crystal layer (layer containing strain)
103, 114, 314 resist pattern
104, 204, 304 SiGe layer containing many defects (defect layer)
105 SiGe amorphous layer
106, 206, 306 First SiGe crystal layer (layer with relaxed strain) 207, 208 Second SiGe layer
109, 110, 209, 210, 309, 310 Silicon crystal layer
111 element isolation region
112, 312, 315 Silicon oxide film
113, 313 Polycrystalline silicon layer
116, 316 Side wall spacer
118, 119 source / drain regions
317 silicon crystal layer

Claims (11)

A semiconductor substrate configured by laminating a SiGe layer containing strain on a silicon substrate,
In a partial region of the SiGe layer, a part of the SiGe layer has a defect layer due to introduction of an electrically neutral element in the SiGe layer, and includes a strain under the defect layer; and A semiconductor substrate, wherein distortion is relaxed on the defect layer. The semiconductor substrate according to claim 1, further comprising one or more semiconductor layers stacked on the SiGe layer. The element of electrically neutral in SiGe layer is hydrogen, the semiconductor substrate according to claim 1 or 2 which is a Group 4 element or the inert gas of the Periodic Table. (A) By stacking a SiGe layer on a silicon substrate, a SiGe layer containing strain is formed,
(B) forming a defect layer in a part of the SiGe layer by ion-implanting an electrically neutral element in the SiGe layer into a part of the SiGe layer and performing a heat treatment; A method for manufacturing a semiconductor substrate, comprising: relaxing distortion of the SiGe layer in a region through which ions pass. A SiGe layer containing strain is laminated on a silicon substrate, and in a part of the SiGe layer, a part of the SiGe layer includes a defect layer due to introduction of an electrically neutral element in the SiGe layer. A semiconductor substrate configured to contain strain under the defect layer and relax the strain on the defect layer;
An element isolation region formed in a region between the region of the SiGe layer strained in the region and all layers of the SiGe layer which distortion is relaxed by the part of the layer in,
An NMOS transistor formed on the SiGe layer in the strain-relieved region and comprising a gate insulating film, a gate electrode, and a source / drain region;
A semiconductor device, comprising: a PMOS transistor formed on a SiGe layer in a region including the strain and comprising a gate insulating film, a gate electrode, and a source / drain region. Further, the on the SiGe layer is one layer or laminated two or more layers of the semiconductor layer, the semiconductor device according to claim 5, wherein the said semiconductor layer NMOS transistor and the PMOS transistors are formed. The gate electrode has a sidewall spacer on the sidewall, and the source / drain regions, formed by formed by the SiGe layer or the semiconductor layer, wherein the stacked on the semiconductor layer on both sides of the sidewall spacer claims Item 7. The semiconductor device according to Item 5 or 6. (A) By stacking a SiGe layer on a silicon substrate, a SiGe layer containing strain is formed,
(B) forming a defect layer in a part of the SiGe layer by ion-implanting an electrically neutral element in the SiGe layer into a part of the SiGe layer and performing a heat treatment; to relax the strain of the SiGe layer in an ion has passed the area,
(C) forming an isolation region in a region between the region of the SiGe layer strained in part enclosing the region and distortion in all layers of the SiGe layer is relaxed in that layer,
(D) on the SiGe layer in the region where the strain containing the SiGe layer and the strain relief region, respectively, forming a gate insulating film, an NMOS transistor and a PMOS transistor composed of a gate electrode and a source / drain region A method for manufacturing a semiconductor device. The method according to claim 8, further comprising depositing one or more semiconductor layers on the SiGe layer after the step (b). The method according to claim 8 or 9, wherein the electrically neutral element in the SiGe layer is hydrogen, a Group 4 element of the periodic table, or an inert gas. Selection in the step (d), the said gate insulating film, after forming the gate electrode, a sidewall spacer is formed on the gate electrode side wall, furthermore, to the sidewall the SiGe layer on both sides of the spacer or the semiconductor layer the method according to laminating semiconductor layers, any one of claims 8-10 for forming the source / drain regions in the semiconductor layer by epitaxial growth.

Images