JP4336407B2 - Circuit board - Google Patents

Circuit board Download PDF

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Publication number
JP4336407B2
JP4336407B2 JP4088399A JP4088399A JP4336407B2 JP 4336407 B2 JP4336407 B2 JP 4336407B2 JP 4088399 A JP4088399 A JP 4088399A JP 4088399 A JP4088399 A JP 4088399A JP 4336407 B2 JP4336407 B2 JP 4336407B2
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circuit board
protective film
mold
semiconductor chip
static electricity
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JP2000243871A (en
Inventor
岸本和之
岡本裕貴
泉勲
北田良二
宮川茂
家村浩文
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Towa Corp
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Towa Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item

Abstract

PROBLEM TO BE SOLVED: To prevent the electrostatic breakdown of a semiconductor chip in a resin sealing process with molding resin when manufacturing a BGA(ball grid array). SOLUTION: On an upper and a lower face of a circuit board 25a, circuit patterns 21a, 21b are formed respectively. On the circuit pattern 21a, protective films 22a and 23a are formed in order. A protective film 22b is formed on the circuit pattern 21b and a land 24 is extended from the circuit pattern 21b. The protective films 23a has a conductivity. Because of this structure, when the circuit board 25a is released from an upper mold 40 after sealed with molding resin, generation of static electricity is suppressed. Therefore, static electricity applied to a semiconductor chip 30 is reduced and the electrostatic breakdown of the semiconductor chip 30 can be prevented.

Description

【０００１】
【発明の属する技術分野】
本発明は、ＩＣ等の電子部品が実装される回路基板であって、特に、実装後にモールド樹脂によって樹脂封止される工程で発生する静電気を抑制する回路基板に関するものである。
【０００２】
【従来の技術】
近年、製品の小型化という要請に対応するために、いわゆるＢＧＡ(Ball Grid Array) が提案されている。このＢＧＡは、回路基板の上面に装着した半導体チップをモールド樹脂内に封止すると共に、回路基板の下面にボールバンプをマトリックス状に配設した構造を備えている。
ＢＧＡに用いられている従来の回路基板について、図５を参照して説明する。図５（１），（２）は、従来の回路基板であって、それぞれ半導体チップが実装された後に、金型にセットされ樹脂封止前の状態と、樹脂封止後に上型が型開きされた状態とを示す断面図である。図５（１），（２）において、基材１の両面に設けられ層間接属された回路パターン２ａ，２ｂ上に、絶縁性樹脂からなる平滑な保護膜３ａ，３ｂが設けられている。上面の保護膜３ａは、例えば、回路パターン２ａを露出させて文字表示として使用する露出部分、ワイヤボンディング用のパッド等の領域以外を、言い換えれば本来露出させる必要がある領域以外をすべて覆うようにして設けられている。下面の保護膜３ｂには、それぞれ回路パターン２ｂから延びてマトリックス状に設けられたランド４を露出させるようにして、開口が設けられている。基材１、回路パターン２ａ，２ｂ、保護膜３ａ，３ｂ、及びランド４は、回路基板５を構成する。
上面の保護膜３ａ上にはＩＣ等の半導体チップ６が載置されている。半導体チップ６の電極（図示なし）と回路パターン２ａとは、ボンディングワイヤ７を介して電気的に接続されている。
【０００３】
回路基板５が樹脂封止される際には、図５（１）に示されているように、上型８と下型９とが型締めされ半導体チップ６の周囲にはキャビティ１０が形成される。更に、溶融された樹脂がキャビティ１０に加圧充填されて、図５（２）に示されているように、充填された樹脂が硬化してモールド樹脂１１が形成された後に上型８が型開きされる。その後に、樹脂封止された回路基板５は、下型９から取り出される。最終的には、ボールバンプ（図示なし）が各ランド４上に設けられて、ＢＧＡが完成する。
【０００４】
【発明が解決しようとする課題】
しかしながら、上記従来の回路基板を使用する場合には、上型８と下型９とから樹脂封止後の回路基板５を取り出す際に、絶縁性樹脂からなる平滑な保護膜３ａ，３ｂが金型から引き離されることによって、保護膜３ａ，３ｂと金型との間において静電気が発生するおそれがあった。そして、発生した静電気は、回路パターン２ａ，２ｂとボンディングワイヤ７とを介して半導体チップ６に印加されて、最悪の場合には半導体チップ６を電気的に破壊すること、すなわち静電破壊が発生していた。また、樹脂封止後のバリの発生を防ぐために、上型８と下型９とが回路基板５を所定の型締圧によって型締めするので、回路基板５の保護膜３ａ，３ｂの広い領域がそれぞれ上型８と下型９とに強く密着して、いっそう静電気が発生しやすくなっていた。
【０００５】
本発明は、上述の課題を解決するためになされたものであり、樹脂封止後の回路基板が金型から取り出される際に静電気の発生を抑制し、ひいては電子部品の静電破壊を防止する回路基板を提供することを目的とする。
【０００６】
【課題を解決するための手段】
【０００７】
【０００８】
上述の技術的課題を解決するために、本発明に係る回路基板は、電子部品が載置された後に金型を使用して電子部品が樹脂封止される回路基板であって、回路基板上に設けられ電子部品に対して電気信号を授受するための回路パターンと、回路パターンを保護するために該回路パターンのうち少なくとも一部を覆って設けられるとともに複数の凸部を有する保護膜とを備え、複数の凸部の存在によって保護膜と金型との接触面積が減少することによって、樹脂封止後の回路基板が金型から引き離される際に静電気の発生が抑制されることを特徴とするものである。
【０００９】
また、本発明に係る回路基板は、上述の回路基板において、複数の凸部は、保護膜に混入された絶縁性粒子によって形成されていることを特徴とするものである。
【００１０】
また、本発明に係る回路基板は、上述の回路基板において、複数の凸部は、回路基板上における保護を必要としない部分を露出させるように保護膜に開口を設けることによって形成されていることを特徴とするものである。
【００１１】
また、本発明に係る回路基板は、上述の回路基板において、複数の凸部は、保護膜が部分的に異なる膜厚を有することによって形成されていることを特徴とするものである。
【００１２】
【作用】
本発明によれば、樹脂封止後であって金型から取り出される前の回路基板において、金型に接触する部分である保護膜が導電性を有しているので、回路基板が金型から取り出される際に静電気の発生が抑制される。更に、静電気が発生した場合でもその静電気が金型へと流出される。したがって、電子部品に対して印加される静電気が低減されるので、電子部品の静電破壊を確実に防止することができる。
また、本発明によれば、凸部を有する保護膜によって、保護膜と金型との接触面積が減少する。これにより、保護膜と金型との間の密着性が低下するので、金型から回路基板が取り出される際に、すなわち金型から保護膜が引き離される際に、静電気の発生が抑制される。したがって、電子部品に対して印加される静電気が低減されるので、電子部品の静電破壊を確実に防止することができる。
【００１３】
【発明の実施の形態】
（参考例）
以下、本発明の参考例について、図面を参照しながら説明する。図１（１），（２）は、本参考例に係る回路基板であって、それぞれ半導体チップが実装された後に、金型にセットされ樹脂封止前の状態と、樹脂封止後に上型が型開きされた状態とを示す断面図である。図１（１），（２）において、基材２０の両面には、層間接属された回路パターン２１ａ，２１ｂが設けられている。上面の回路パターン２１ａ上には、保護膜２２ａ，２３ａが、順次設けられている。ここで、下層の保護膜２２ａは絶縁性樹脂により形成され、最上層の保護膜２３ａは例えば炭素の微粒子等の導電性物質を含んで平滑に形成されている。下面の回路パターン２１ｂ上には、保護膜２２ｂが設けられている。保護膜２２ｂには、それぞれ回路パターン２１ｂから延びてマトリックス状に設けられたランド２４を露出させるように、開口が設けられている。基材２０、回路パターン２１ａ，２１ｂ、保護膜２２ａ，２３ａ，２２ｂ、及びランド２４は、プリント基板(Printed Circuit Board) と称されている回路基板２５ａを構成する。
保護膜２３ａ上には、ＩＣ等の半導体チップ３０が載置されている。半導体チップ３０の電極（図示なし）と回路パターン２１ａとは、ボンディングワイヤ３１を介して電気的に接続されている。最終的には、ボールバンプ（図示なし）が各ランド２４上に設けられて、ＢＧＡが完成する。
回路基板２５ａが樹脂封止される際には、図１（１）に示されているように、上型４０と下型４１とが型締めされ半導体チップ３０の周囲にはキャビティ３２が形成される。更に、溶融された樹脂がキャビティ３２に加圧充填され、図１（２）に示されているように、樹脂が硬化してモールド樹脂３３が形成された後に上型４０が型開きされる。
【００１４】
ここで、本参考例に係る回路基板の特徴は、最上層の保護膜２３ａが、導電性物質を含んで形成されていることである。これにより、保護膜２３ａは導電性を有するので、上型４０から樹脂封止後の回路基板２５ａが引き離される際に、保護膜２３ａと上型４０との間における静電気の発生を抑制することができる。更に、静電気が発生した場合でも、発生した静電気は導電性を有する保護膜２３ａによって下型４１へと導かれる。したがって、半導体チップ３０に印加される静電気が大幅に低減されるので、半導体チップ３０の静電破壊を確実に防止することができる。
【００１５】
なお、本参考例の説明においては、導電性物質を含ませて形成する保護膜を上面の保護膜の最上層としたが、これに限らず、導電性を有する１層の保護膜を回路パターン２１ａ上に設けてもよい。この場合には、各回路パターン２１ａ相互間について必要な絶縁性を確保できる程度に、保護膜に含ませる導電性物質の種類や量等を決定すればよい。
【００１６】
また、必要に応じて、下面の保護膜についても、導電性を有する１層の保護膜を回路パターン２１ｂ上に設けてもよいし、複数の層からなる保護膜の最上層を導電性を有する層にしてもよい。
【００１７】
（第１の実施形態）
以下、本発明の第１の実施形態について、図面を参照しながら説明する。図２（１），（２）は、本実施形態に係る回路基板であって、それぞれ半導体チップが実装された後に、金型にセットされ樹脂封止前の状態と、樹脂封止後に上型が型開きされた状態とを示す断面図である。回路基板２５ｂの上面における保護膜２２ａには、例えばガラス等の絶縁性粒子２６が含まれている。絶縁性粒子２６によって、保護膜２２ａの表面には微小な凸部２７が形成されている。
【００１８】
ここで、本実施形態に係る回路基板の特徴は、保護膜２２ａの表面に微小な凸部２７が形成されていることである。これにより、微小な凹凸を有する保護膜２２ａと上型４０との間の密着性が低下するので、上型４０から回路基板２５ｂが取り出される際に、すなわち上型４０から保護膜２２ａが引き離される際に、静電気の発生が抑制される。したがって、半導体チップ３０に対して印加される静電気が低減されるので、半導体チップ３０の静電破壊を確実に防止することができる。
【００１９】
図３（１），（２）は、本実施形態に係る別の回路基板であって、それぞれ半導体チップが実装された後に、金型にセットされ樹脂封止前の状態と、樹脂封止後に上型が型開きされた状態とを示す断面図である。回路基板２５ｃの上面における保護膜２２ａは、回路パターン２１ａのうち保護が必要な領域、例えば電気的に絶縁コートされることが必要な領域のみを覆っている。言い換えれば、回路基板２５ｃの上面においては、絶縁コートが不要である領域は開口２８によって露出しているので、本来露出されるべき部分以外をすべて覆う場合に比べて、保護膜２２ａの有無による凹凸がより多く生じることになる。
【００２０】
これにより、凹凸を有する保護膜２２ａと上型４０との間の密着性が低下するので、上型４０から回路基板２５ｃが取り出される際に、すなわち上型４０から保護膜２２ａが引き離される際に、静電気の発生が抑制される。したがって、半導体チップ３０に対して印加される静電気が低減されるので、半導体チップ３０の静電破壊を確実に防止することができる。
【００２１】
図４（１），（２）は、本実施形態に係る更に別の回路基板であって、それぞれ半導体チップが実装された後に、金型にセットされ樹脂封止前の状態と、樹脂封止後に上型が型開きされた状態とを示す断面図である。回路基板２５ｄの上面における保護膜２２ａは、所定の部分に凸部２７と凹部２９とが存在するように設けられている。凸部２７と凹部２９とを有する保護膜２２ａは、例えば、保護が必要な領域の全部に下層保護膜を塗布した後に、下層保護膜の上に格子状の上層保護膜を塗布することにより形成することができる。
【００２２】
これにより、凹凸を有する保護膜２２ａと上型４０との間の密着性が低下するので、上型４０から回路基板２５ｄが取り出される際に、すなわち上型４０から保護膜２２ａが引き離される際に、静電気の発生が抑制される。したがって、半導体チップ３０に対して印加される静電気が低減されるので、半導体チップ３０の静電破壊を確実に防止することができる。
【００２３】
以上説明したように、本実施形態によれば、保護膜２２ａの凸部によって、上型４０と保護膜２２ａとの密着性が低下するので、上型４０から回路基板２５ｂ〜２５ｄを取り出す際に静電気の発生が抑制される。したがって、半導体チップ３０に対して印加される静電気が低減されるので、半導体チップ３０の静電破壊を確実に防止することができる。
【００２４】
なお、本実施形態の説明においては、回路基板の上面の保護膜について説明したが、下面の保護膜についても同様に凸部を形成することができる。
また、回路基板の使用されていない部分に凹部又は貫通穴を設けた後に、保護膜を形成してもよい。これにより、その凹部又は貫通穴の上において、保護膜の膜厚が小さくなり、あるいは保護膜が形成されない部分ができる。したがって、回路基板の保護膜において凸部を形成することができる。
【００２５】
また、以上説明した実施形態においては、回路基板としてプリント基板を使用したが、これに限らず、ポリイミド等からなり可撓性を有するフイルム状の基板、いわゆるフレキシブル回路基板(Flexible Printed Circuit)を使用してもよいことはいうまでもない。
更に、本発明に係る回路基板は、半導体チップの他にも、静電気に対して耐性が低い電子部品に対して使用することができる。
【００２６】
【発明の効果】
本発明によれば、モールド樹脂によって封止された後の回路基板を金型から引き離す際に、回路基板上に設けられた導電性を有する保護膜によって静電気の発生を抑制することができる。また、回路基板上に設けられ凸部を有する保護膜によって、保護膜と金型との密着性が低下するので、モールド樹脂によって封止された後の回路基板を金型から引き離す際に、静電気の発生を抑制することができる。
したがって、電子部品に対して印加される静電気が低減されるので、電子部品の静電破壊を確実に防止することができる。これにより、電子部品の静電破壊が確実に防止される回路基板を提供できるという、優れた実用的な効果を奏するものである。
【図面の簡単な説明】
【図１】 （１），（２）は、それぞれ本発明の参考例に係る回路基板上に半導体チップが実装された後に、金型にセットされ樹脂封止前の状態と、樹脂封止後に上型が型開きされた状態とを示す断面図である。
【図２】 （１），（２）は、それぞれ本発明の第１の実施形態に係る回路基板上に半導体チップが実装された後に、金型にセットされ樹脂封止前の状態と、樹脂封止後に上型が型開きされた状態とを示す断面図である。
【図３】 （１），（２）は、それぞれ本発明の第１の実施形態に係る別の回路基板上に半導体チップが実装された後に、金型にセットされ樹脂封止前の状態と、樹脂封止後に上型が型開きされた状態とを示す断面図である。
【図４】 （１），（２）は、それぞれ本発明の第１の実施形態に係る更に別の回路基板上に半導体チップが実装された後に、金型にセットされ樹脂封止前の状態と、樹脂封止後に上型が型開きされた状態とを示す断面図である。
【図５】 （１），（２）は、それぞれ従来の回路基板上に半導体チップが実装された後に、金型にセットされ樹脂封止前の状態と、樹脂封止後に上型が型開きされた状態とを示す断面図である。
【符号の説明】
２０ 基材
２１ａ，２１ｂ 回路パターン
２２ａ，２２ｂ，２３ａ 保護膜
２４ ランド
２５ａ，２５ｂ，２５ｃ，２５ｄ 回路基板
２６ 絶縁性粒子
２７ 凸部
２８ 開口
２９ 凹部
３０ 半導体チップ
３１ ボンディングワイヤ
３２ キャビティ
３３ モールド樹脂
４０ 上型
４１ 下型[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a circuit board on which an electronic component such as an IC is mounted, and more particularly to a circuit board that suppresses static electricity generated in a process of being resin-sealed with a mold resin after mounting.
[0002]
[Prior art]
In recent years, so-called BGA (Ball Grid Array) has been proposed in order to meet the demand for downsizing of products. This BGA has a structure in which a semiconductor chip mounted on the upper surface of a circuit board is sealed in a mold resin, and ball bumps are arranged in a matrix on the lower surface of the circuit board.
A conventional circuit board used for BGA will be described with reference to FIG. FIGS. 5 (1) and 5 (2) are conventional circuit boards, each of which is set in a mold after a semiconductor chip is mounted and before the resin is sealed, and the upper mold is opened after the resin is sealed. It is sectional drawing which shows the state made. 5 (1) and 5 (2), smooth protective films 3a and 3b made of an insulating resin are provided on circuit patterns 2a and 2b that are provided on both surfaces of the base material 1 and indirectly belong to the layer. The protective film 3a on the upper surface covers, for example, all the areas other than the exposed areas where the circuit pattern 2a is exposed to be used for character display, the areas such as the pads for wire bonding, in other words, the areas that should originally be exposed. Is provided. The protective film 3b on the lower surface is provided with openings so as to expose the lands 4 provided in a matrix extending from the circuit pattern 2b. The substrate 1, circuit patterns 2 a and 2 b, protective films 3 a and 3 b, and lands 4 constitute a circuit board 5.
A semiconductor chip 6 such as an IC is placed on the protective film 3a on the upper surface. An electrode (not shown) of the semiconductor chip 6 and the circuit pattern 2 a are electrically connected via a bonding wire 7.
[0003]
When the circuit board 5 is resin-sealed, as shown in FIG. 5A, the upper mold 8 and the lower mold 9 are clamped, and a cavity 10 is formed around the semiconductor chip 6. The Further, the melted resin is pressurized and filled into the cavity 10, and as shown in FIG. 5 (2), after the filled resin is cured and the mold resin 11 is formed, the upper mold 8 is molded. Opened. Thereafter, the resin-sealed circuit board 5 is taken out from the lower mold 9. Finally, ball bumps (not shown) are provided on each land 4 to complete the BGA.
[0004]
[Problems to be solved by the invention]
However, when the conventional circuit board is used, when the circuit board 5 after resin sealing is taken out from the upper mold 8 and the lower mold 9, the smooth protective films 3a and 3b made of an insulating resin are made of gold. When separated from the mold, there is a possibility that static electricity is generated between the protective films 3a and 3b and the mold. The generated static electricity is applied to the semiconductor chip 6 through the circuit patterns 2a and 2b and the bonding wires 7, and in the worst case, the semiconductor chip 6 is electrically destroyed, that is, electrostatic breakdown occurs. Was. Further, in order to prevent the generation of burrs after resin sealing, the upper mold 8 and the lower mold 9 clamp the circuit board 5 with a predetermined mold clamping pressure, so that a wide area of the protective films 3a and 3b of the circuit board 5 is obtained. Are closely attached to the upper die 8 and the lower die 9, respectively, and static electricity is more likely to be generated.
[0005]
The present invention has been made to solve the above-described problems, and suppresses the generation of static electricity when a circuit board after resin sealing is taken out of a mold, and thus prevents electrostatic breakdown of electronic components. An object is to provide a circuit board.
[0006]
[Means for Solving the Problems]
[0007]
[0008]
In order to solve the above-described technical problem, a circuit board according to the present invention is a circuit board in which an electronic component is resin-sealed using a mold after the electronic component is placed on the circuit board. A circuit pattern for transmitting and receiving an electrical signal to an electronic component, and a protective film provided to cover at least a part of the circuit pattern and having a plurality of convex portions in order to protect the circuit pattern. It is characterized in that the generation of static electricity is suppressed when the circuit board after resin sealing is pulled away from the mold by reducing the contact area between the protective film and the mold due to the presence of a plurality of convex portions. To do.
[0009]
The circuit board according to the present invention is characterized in that, in the above-described circuit board, the plurality of convex portions are formed by insulating particles mixed in the protective film.
[0010]
In the circuit board according to the present invention, in the above-described circuit board, the plurality of convex portions are formed by providing openings in the protective film so as to expose portions on the circuit board that do not require protection. It is characterized by.
[0011]
The circuit board according to the present invention is characterized in that, in the above-described circuit board, the plurality of convex portions are formed by the protective films having partially different film thicknesses.
[0012]
[Action]
According to the present invention, in the circuit board after the resin sealing and before being taken out from the mold, the protective film which is a part in contact with the mold has conductivity, so that the circuit board is removed from the mold. Generation of static electricity is suppressed when it is taken out. Furthermore, even when static electricity is generated, the static electricity flows out to the mold. Therefore, since static electricity applied to the electronic component is reduced, electrostatic breakdown of the electronic component can be reliably prevented.
In addition, according to the present invention, the contact area between the protective film and the mold is reduced by the protective film having the convex portions. Thereby, since the adhesiveness between the protective film and the mold is lowered, the generation of static electricity is suppressed when the circuit board is taken out from the mold, that is, when the protective film is separated from the mold. Therefore, since static electricity applied to the electronic component is reduced, electrostatic breakdown of the electronic component can be reliably prevented.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
( Reference example )
Hereinafter, reference examples of the present invention will be described with reference to the drawings. FIGS. 1A and 1B are circuit boards according to this reference example , each of which is set in a mold after a semiconductor chip is mounted and before the resin sealing, and the upper mold after the resin sealing. It is sectional drawing which shows the state by which the mold was opened. 1 (1) and 1 (2), circuit patterns 21a and 21b that are indirectly associated with layers are provided on both surfaces of a base material 20. On the circuit pattern 21a on the upper surface, protective films 22a and 23a are sequentially provided. Here, the lower protective film 22a is formed of an insulating resin, and the uppermost protective film 23a is formed smoothly, for example, containing a conductive substance such as carbon fine particles. A protective film 22b is provided on the circuit pattern 21b on the lower surface. Openings are provided in the protective film 22b so as to expose the lands 24 extending from the circuit pattern 21b and provided in a matrix. The base material 20, the circuit patterns 21a and 21b, the protective films 22a, 23a and 22b, and the land 24 constitute a circuit board 25a called a printed circuit board.
On the protective film 23a, a semiconductor chip 30 such as an IC is placed. An electrode (not shown) of the semiconductor chip 30 and the circuit pattern 21 a are electrically connected via a bonding wire 31. Eventually, ball bumps (not shown) are provided on each land 24 to complete the BGA.
When the circuit board 25a is resin-sealed, as shown in FIG. 1A, the upper mold 40 and the lower mold 41 are clamped, and a cavity 32 is formed around the semiconductor chip 30. The Further, the melted resin is pressurized and filled into the cavity 32, and the upper mold 40 is opened after the resin is cured and the mold resin 33 is formed, as shown in FIG.
[0014]
Here, a feature of the circuit board according to this reference example is that the uppermost protective film 23a is formed to include a conductive substance. Thereby, since the protective film 23a has conductivity, it is possible to suppress the generation of static electricity between the protective film 23a and the upper mold 40 when the circuit board 25a after resin sealing is separated from the upper mold 40. it can. Further, even when static electricity is generated, the generated static electricity is guided to the lower mold 41 by the conductive protective film 23a. Therefore, the static electricity applied to the semiconductor chip 30 is greatly reduced, so that electrostatic breakdown of the semiconductor chip 30 can be reliably prevented.
[0015]
In the description of this reference example , the protective film formed by including a conductive substance is the uppermost layer of the protective film on the upper surface. However, the present invention is not limited to this, and a single protective film having conductivity is used as the circuit pattern. It may be provided on 21a. In this case, what is necessary is just to determine the kind, quantity, etc. of the electroconductive substance contained in a protective film to such an extent that required insulation can be ensured between each circuit pattern 21a.
[0016]
If necessary, the protective film on the lower surface may be provided with a single protective film on the circuit pattern 21b, or the uppermost protective film made of a plurality of layers may be conductive. It may be a layer.
[0017]
( First embodiment )
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. 2 (1) and 2 (2) are circuit boards according to the present embodiment, each of which is mounted on a mold after a semiconductor chip is mounted and before the resin sealing, and the upper mold after the resin sealing. It is sectional drawing which shows the state by which the mold was opened. The protective film 22a on the upper surface of the circuit board 25b includes insulating particles 26 such as glass. Due to the insulating particles 26, minute convex portions 27 are formed on the surface of the protective film 22a.
[0018]
Here, a feature of the circuit board according to the present embodiment is that minute convex portions 27 are formed on the surface of the protective film 22a. As a result, the adhesion between the protective film 22a having minute irregularities and the upper mold 40 is lowered, so that the protective film 22a is pulled away from the upper mold 40 when the circuit board 25b is taken out from the upper mold 40. In this case, generation of static electricity is suppressed. Therefore, since static electricity applied to the semiconductor chip 30 is reduced, electrostatic breakdown of the semiconductor chip 30 can be reliably prevented.
[0019]
3 (1) and 3 (2) are other circuit boards according to the present embodiment, and after each semiconductor chip is mounted, it is set in a mold and before resin sealing, and after resin sealing. It is sectional drawing which shows the state by which the upper mold | type was opened. The protective film 22a on the upper surface of the circuit board 25c covers only a region of the circuit pattern 21a that needs to be protected, for example, a region that needs to be electrically insulated. In other words, on the upper surface of the circuit board 25c, since the region where the insulating coating is unnecessary is exposed by the opening 28, the unevenness due to the presence / absence of the protective film 22a is compared with the case where all the portions other than the portion to be originally exposed are covered. Will occur more.
[0020]
As a result, the adhesion between the protective film 22a having irregularities and the upper mold 40 is lowered, so that when the circuit board 25c is taken out from the upper mold 40, that is, when the protective film 22a is separated from the upper mold 40. The generation of static electricity is suppressed. Therefore, since static electricity applied to the semiconductor chip 30 is reduced, electrostatic breakdown of the semiconductor chip 30 can be reliably prevented.
[0021]
FIGS. 4A and 4B are still another circuit boards according to the present embodiment, each of which is set in a mold after a semiconductor chip is mounted and before resin sealing, and resin sealing. It is sectional drawing which shows the state by which the upper mold was opened afterwards. The protective film 22a on the upper surface of the circuit board 25d is provided so that a convex portion 27 and a concave portion 29 exist in a predetermined portion. The protective film 22a having the convex portions 27 and the concave portions 29 is formed by, for example, applying a lower protective film over the entire region that needs to be protected and then applying a lattice-shaped upper protective film over the lower protective film. can do.
[0022]
As a result, the adhesion between the protective film 22a having projections and depressions and the upper mold 40 is lowered, so that when the circuit board 25d is taken out from the upper mold 40, that is, when the protective film 22a is separated from the upper mold 40. The generation of static electricity is suppressed. Therefore, since static electricity applied to the semiconductor chip 30 is reduced, electrostatic breakdown of the semiconductor chip 30 can be reliably prevented.
[0023]
As described above, according to the present embodiment, the adhesiveness between the upper mold 40 and the protective film 22a is lowered by the convex portion of the protective film 22a, so that the circuit boards 25b to 25d are taken out from the upper mold 40. Generation of static electricity is suppressed. Therefore, since static electricity applied to the semiconductor chip 30 is reduced, electrostatic breakdown of the semiconductor chip 30 can be reliably prevented.
[0024]
In the description of the present embodiment, the protective film on the upper surface of the circuit board has been described. However, a convex portion can be similarly formed on the protective film on the lower surface.
Further, the protective film may be formed after providing the recess or the through hole in the unused portion of the circuit board. Thereby, the thickness of the protective film is reduced or a portion where the protective film is not formed is formed on the concave portion or the through hole. Therefore, a convex part can be formed in the protective film of a circuit board.
[0025]
In the embodiment described above, a printed circuit board is used as a circuit board. However, the present invention is not limited to this, and a flexible film substrate made of polyimide or the like, that is, a so-called flexible printed circuit is used. Needless to say.
Furthermore, the circuit board according to the present invention can be used for an electronic component having low resistance to static electricity in addition to a semiconductor chip.
[0026]
【The invention's effect】
According to the present invention, when the circuit board after being sealed with the mold resin is separated from the mold, the generation of static electricity can be suppressed by the conductive protective film provided on the circuit board. In addition, since the adhesion between the protective film and the mold is reduced by the protective film provided on the circuit board and having the convex portion, when the circuit board sealed with the mold resin is separated from the mold, Can be suppressed.
Therefore, since static electricity applied to the electronic component is reduced, electrostatic breakdown of the electronic component can be reliably prevented. Thereby, the outstanding practical effect that the circuit board by which the electrostatic breakdown of an electronic component is prevented reliably can be provided.
[Brief description of the drawings]
FIGS. 1A and 1B show a state before a semiconductor chip is mounted on a circuit board according to a reference example of the present invention and set in a mold before resin sealing, and after resin sealing, respectively. It is sectional drawing which shows the state by which the upper mold | type was opened.
FIGS. 2A and 2B show a state in which a semiconductor chip is mounted on a circuit board according to the first embodiment of the present invention and then set in a mold and before resin sealing; It is sectional drawing which shows the state by which the upper mold | type was opened after sealing.
FIGS. 3A and 3B show a state before a semiconductor chip is mounted on another circuit board according to the first embodiment of the present invention and set in a mold before resin sealing, respectively. FIG. 3 is a cross-sectional view showing a state where an upper mold is opened after resin sealing.
FIGS. 4A and 4B show a state before a semiconductor chip is mounted on a circuit board according to the first embodiment of the present invention and then set in a mold and before resin sealing, respectively. And a sectional view showing a state where the upper mold is opened after resin sealing.
FIGS. 5A and 5B show a state before a semiconductor chip is mounted on a conventional circuit board and then set in a mold before resin sealing, and the upper mold opens after resin sealing. It is sectional drawing which shows the state made.
[Explanation of symbols]
20 Base material 21a, 21b Circuit pattern 22a, 22b, 23a Protective film 24 Land 25a, 25b, 25c, 25d Circuit board 26 Insulating particle 27 Protruding part 28 Opening 29 Concave part 30 Semiconductor chip 31 Bonding wire 32 Cavity 33 Mold resin 40 On Type 41 Lower type

Claims (4)

電子部品が載置された後に金型を使用して前記電子部品が樹脂封止される回路基板であって、
前記回路基板上に設けられ前記電子部品に対して電気信号を授受するための回路パターンと、
前記回路パターンを保護するために該回路パターンのうち少なくとも一部を覆って設けられるとともに複数の凸部を有する保護膜とを備え、
前記複数の凸部の存在によって前記保護膜と前記金型との接触面積が減少することによって、樹脂封止後の前記回路基板が前記金型から引き離される際に静電気の発生が抑制されることを特徴とする回路基板。A circuit board on which the electronic component is resin-sealed using a mold after the electronic component is placed,
A circuit pattern provided on the circuit board for transmitting and receiving electrical signals to and from the electronic component;
A protective film provided to cover at least a part of the circuit pattern to protect the circuit pattern and having a plurality of protrusions;
The presence of the plurality of convex portions reduces the contact area between the protective film and the mold, thereby suppressing the generation of static electricity when the circuit board after resin sealing is separated from the mold. A circuit board characterized by. 請求項１記載の回路基板において、
前記複数の凸部は、前記保護膜に混入された絶縁性粒子によって形成されていることを特徴とする回路基板。The circuit board according to claim 1 ,
The circuit board, wherein the plurality of convex portions are formed of insulating particles mixed in the protective film. 請求項１記載の回路基板において、
前記複数の凸部は、前記回路基板上における保護を必要としない部分を露出させるように前記保護膜に開口を設けることによって形成されていることを特徴とする回路基板。The circuit board according to claim 1 ,
The circuit board characterized in that the plurality of convex portions are formed by providing openings in the protective film so as to expose portions on the circuit board that do not require protection. 請求項１記載の回路基板において、
前記複数の凸部は、前記保護膜が部分的に異なる膜厚を有することによって形成されていることを特徴とする回路基板。The circuit board according to claim 1 ,
The plurality of convex portions are formed by forming the protective film partially different in film thickness.
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JPH0781284A (en) * 1993-09-14 1995-03-28 Casio Comput Co Ltd Manufacture of information medium
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