JP4309882B2 - Wiring board for multi-cavity - Google Patents

Description

  The present invention provides a multi-wiring circuit board that can easily detect and determine pass / fail of printing misalignment between conductor patterns formed on the front and back surfaces of an insulating layer or misalignment between a plurality of insulating layers to be laminated. About.

According to the recent trend toward higher density and higher performance of wiring on the wiring board, printing misalignment between the upper and lower wiring layers sandwiching the insulating layer, and the wiring layers formed for each of the multiple insulating layers to be stacked It is demanded to reduce the problems caused by the stacking deviation.
For example, in a multi-layer multi-layer wiring board in which wiring circuits and via conductors are formed for each of a plurality of insulating layers to be stacked, a pattern in which the width in a direction orthogonal to the end face of the multi-layer wiring board monotonously changes (for example, A multilayer wiring board has been proposed in which a right-angled triangle pattern in plan view) is formed for each insulating layer, and such a pattern is exposed on an end face after lamination (see, for example, Patent Document 1).

JP 2005-101299 A (pages 1 to 12, FIGS. 1 and 2)

  According to the multilayer wiring board of Patent Document 1, it is possible to easily determine the presence or absence of misalignment by detecting a difference in length between a plurality of patterns exposed on the end face. However, it is necessary to measure, for each multilayer wiring board, the difference in length between the plurality of patterns exposed on the end face to determine whether or not such stacking deviation is within the allowable range. For this reason, there existed a problem that the inspection process of the said multilayer wiring board requires a man-hour and raises cost.

  The present invention solves the problems described in the background art, the presence or absence of misprinting between the upper and lower wiring layers sandwiching the insulating layer, the misalignment between the plurality of insulating layers forming the wiring layer, and It is an object of the present invention to provide a wiring board for multi-cavity that can be easily judged whether it is shifted or not.

Means for Solving the Problems and Effects of the Invention

In order to solve the above problems, the present invention provides a plurality of marks provided on the front and back surfaces of the insulating layer or simultaneously with the wiring layers to be formed on the plurality of insulating layers to be laminated, with a viewing angle along the thickness direction of the wiring board. The idea is to apply the maximum length of the allowable deviation amount to the difference in length between a plurality of marks.
That is, the multi-cavity wiring board according to the present invention (Claim 1) has an insulating layer in which any one of the marks A, B, and C having a rectangular shape in plan view is formed on either the front surface or the back surface. And the insulating layer is laminated adjacent to the back side or the front side, has a rectangular shape in plan view, and the remaining two marks of the marks A, B, and C other than the one mark include the one mark. overlap in the thickness direction, one of the two marks are formed on the surface, and the other is a separate insulating layer formed on the back surface, the unrealized plan view a rectangular surface, back surface, and positioned between the a multi-piece wiring board having four outer surfaces of the length of the mark a exposed to the outside side surface of such a multi-piece wiring substrate, the mark B, longer than the length of C, the mark C The length is between the lengths of marks A and B. In addition, the difference in length between the one mark and one of the remaining two marks is equal to the maximum allowable stacking deviation, and the difference in length between the remaining two marks. Corresponds to the maximum allowable printing deviation amount.

According to this, the (remaining) two marks are separately formed on the surface and the back surface of the other insulating layer, and the surface and the back surface of the other insulating layer are observed by observing the degree of overlap between both marks. It is possible to easily determine whether or not the printing misalignment between the conductor layers printed on the sheet is acceptable . At the same time, by observing the degree of overlap between one mark formed on the front surface or the back surface of the insulating layer and one of the remaining two marks in another insulating layer, it is possible to easily determine whether the stacking deviation between the insulating layers is acceptable or not at a glance. It can also be determined . Further, even if there is a printing misalignment or stacking misalignment along the X direction of the insulating layer and another insulating layer along the width direction of the marks A, B, C, such a misprinting is caused in the Y direction of each insulating layer. By observing the degree of overlap of the marks A, B, and C separately formed along the same, it is possible to easily determine whether or not the product is acceptable . Therefore, since it is possible to determine at a glance whether the misalignment and the misalignment of the multi-wiring substrate having a plurality of multi-layer wiring substrates at the same time, it is possible to reduce the man-hour and cost of the inspection process .

In order to keep the printing misalignment and stacking misalignment within narrow tolerances, for example, the mark C to be compared with the longest mark A is selected as the mark C having an intermediate length, and the mark to be compared with the shortest mark B is A slightly longer mark C is selected .

The insulating layer and the other insulating layer are made of, for example, a ceramic mainly composed of alumina, for example, a glass-ceramic which is a kind of low-temperature fired ceramic made of glass-alumina, or a resin such as BT resin. Via conductors penetrate between the front surface and the back surface. Of these, one of the marks A, B, and C is formed on the front surface or the back surface of the insulating layer, and another insulating layer is the remaining 2 except for the one mark on the front and back surfaces. Two marks are formed individually.
In addition, the multi-piece wiring board includes a wiring board composed of another insulating layer that is a single layer and a single layer or a multi-layer insulating layer, a relay board, a SAW filter, a crystal resonator, or a piezoelectric vibration. This includes a plurality of mounting boards in an electronic component mounting package such as a child.
Furthermore, the remaining two marks formed on the front and back surfaces of the other insulating layer are equally arranged in plan view along the thickness direction of the other insulating layer, that is, both ends of the relatively short mark in the longitudinal direction. Are formed so that both ends of the relatively long mark are exposed with the same length, and the difference between the lengths of both marks is twice the maximum allowable deviation. The deviation refers to printing deviation (or patterning deviation) of a conductor layer (land or connection terminal) to be formed on the front and back surfaces of the insulating layer.
In addition, the outer surface of the multi-cavity wiring board includes not only the outer surface of the substrate but also a cut surface that appears when the substrate is cut along a planned cutting line.

Further, the present invention is the wiring board multi-piece is a rectangular in plan view, the mark A, B, C are formed in each adjacent outer sides in such a multi-piece wiring substrate Also included is a multi-cavity wiring board (claim 2).
According to this, even if printing deviation or stacking deviation along the X direction of each insulating layer exists along the width direction of the marks A, B, and C, such printing deviation is caused in the Y direction of each insulating layer. By observing the degree of overlap of the marks A, B, and C separately formed along the lines, it is possible to easily and accurately determine whether or not it is acceptable.

Further, according to the present invention, the insulating layer and the other insulating layer are large plate insulating plates having a product region to be a plurality of wiring boards and having an ear around the product region. on the outer surface or the cut surface of the ear portion of part, the mark a, B, each cross-section of C is exposed, multi several up wiring board (claim 3) are also included.

  According to this, without using the product area, by observing the degree of overlap between the marks exposed on the outer surface of the surrounding ears, the above-described print misalignment or stacking misalignment can be performed without damaging the product area. It is possible to easily determine the presence / absence and acceptance / rejection.

In other words, according to the present invention, the marks A, B, and C are made of a conductor pattern, and have a large number of rectangular shapes (rectangular shapes) perpendicular to each longitudinal direction and having a certain width or more in plan view. A wiring board for use may also be included. According to this, the marks A, B, and C can be simultaneously formed by printing or patterning with the same mask pattern as that of the conductor layer such as the connection terminal and the wiring layer to be formed on the front surface and the back surface of the insulating layer, and printing misalignment of these can be achieved. And can be used for determination of misalignment between insulating layers.

In addition, the present invention, the overlapping between the remaining two marks mutually Modes of center lines along the width direction of the rectangles of the mark that is perpendicular to the outer surface are matched in a plan view, the outer surface A multi-cavity wiring board in which the short sides of the same end in the longitudinal direction of the rectangles of the marks parallel to each other are in a range up to a form in which the multi-cavity wiring board is aligned in the thickness direction (Claim 4). Is also included.

According to this, it is possible to quickly and accurately determine whether or not the above-described printing misalignment or stacking misalignment is made, and it is possible to reliably increase the efficiency of the inspection process .

Further, in the present invention, the insulating layer and the other insulating layer have product regions to be a plurality of wiring boards, have ears between the product regions and on the outer periphery of the product region, and each ear portion. A multi-piece wiring board in which the marks A, B, and C are formed in the vicinity of or along the middle of each ear may be included.

In this case , without using each of the plurality of product areas, by observing the degree of overlap between the marks exposed on the outer surface of the ear portion surrounding them and the cut surface cut along the middle of the ear portion, It is possible to easily and efficiently determine the presence / absence and pass / fail of the above-described printing misalignment or stacking misalignment without damaging the area.

In the following, the best mode for carrying out the present invention will be described.
FIG. 1 is a plan view showing a multi-piece wiring board K according to an embodiment of the present invention, FIG. 2 is a perspective view showing the wiring board K, and FIG. 3 is a partial side view thereof.
As shown in FIGS. 1 and 2, the multi-cavity wiring board K includes an insulating laminate S in which two upper and lower insulating layers s1 and another insulating layer s2 are stacked, and X for each of the insulating layers s1 and s2. A product area having a total of nine wiring boards 1 divided in each direction by three broken wiring lines c indicated by broken lines along the −Y direction, and ears m surrounding these are provided.
The insulating layer s1 and the other insulating layer s2 have a rectangular shape in plan view, and are, for example, a ceramic obtained by firing a green sheet containing alumina. The insulating layers s1 and s2 may be glass-ceramic which is a kind of low-temperature fired ceramic.

As shown in FIGS. 1 and 2, the surface 2 of the insulating layer s <b> 1 has a longest rectangular shape (rectangular shape) in the vicinity of the center of each of the ears m of the pair of opposed long sides and the pair of short sides. one mark a is formed such. Also, at substantially the same position as above between the back surface 3 and the surface 4 of another insulating layer s2 insulating layer s1 is plan view in the longitudinal direction a rectangular (rectangle) are formed shortest mark B . Furthermore, almost the same position as the the back surface 5 of another insulating layer s2, plan view in the longitudinal direction a rectangular (rectangle) is intermediate the length of the mark C is formed between the marks A and mark B . The marks A to C are also exposed on the outer surface (side surface) of the wiring board K.

The marks A to C are conductor patterns made of W or Mo and having a thickness of several μm to several tens of μm, and the product areas (1, 1, 2) on the surface 2 of the insulating layer s1 and the surface 4 and the back surface 5 of another insulating layer s2. 1,...), When a land, an internal wiring pattern, or a connection terminal (none of which is shown) is screen-printed, it is simultaneously printed and baked near the center of each side of the ear m. Is.
As shown in FIG. 3, the length in the longitudinal direction in the side view is, for example, mark A: 1 mm, mark B: 0.6 mm, and mark C: 0.8 mm. Further, it is desirable that the width (w) of the marks A to C is, for example, 0.2 to 0.4 mm and common. When the insulating layers s1 and s2 are made of glass-ceramic, Cu or Ag is used for the marks A to C.

As shown in FIGS. 1 and 2, the marks A to C are formed on the four sides of the insulating layers s1 and s2 on the front and back surfaces 4 and 5 of another insulating layer s2 in the multi-piece wiring board K. (Remaining) Even if the printing deviation between the two marks B and C is, for example, along the X (long side) direction, the above-mentioned printing can be performed by visually checking the degree of overlap between the marks B and C on the pair of short sides. This is because it is possible to determine whether or not there is a deviation and to determine whether it is acceptable or not. Further, even if the stacking deviation between the insulating layer s1 and another insulating layer s2 is along, for example, the Y (short side) direction, by visually observing the degree of overlap between the marks A and C on the pair of long sides, The presence / absence of the stacking deviation and the pass / fail judgment can be made.

Here, the method of detecting misregistration used in many of the onset bright-piece wiring substrate K, will be described with reference to FIGS. 4-6.
As shown in FIG. 4, two of the marked B formed on the surface 4 of another insulating layer s2 constituting the multi-chip wiring board K, the long mark C than mark B formed on the back surface 5 Are rectangles having the same width w, and the center lines n and n along the width direction of the two coincide in plan view. 4 is a plan view of the marks B and C along the arrow indicated by the thick arrow on the left side, and the right side of FIG. 4 is a perspective view of the marks B and C. The same applies to 6.
That is, the marks B and C in FIG. 4 are equally arranged in a plan view, indicating that there is no printing misalignment between the front and back surfaces 4 and 5 of another insulating layer s2. Incidentally, the length dC of the mark C is obtained by adding a half z1 of an allowable maximum printing deviation amount (length: z1 × 2 ) to the outside of both ends of the length dB of the mark B (see Formula 1). ).

(Equation 1)
dC = dB + (z1 × 2)

In each wiring board 1 of another insulating layer s2, via conductors (both not shown) are formed at appropriate positions by firing a conductive paste containing W or Mo filled in a via hole that has been punched in advance. Yes. When the marks B and C are on the side surfaces of the insulating layer s2 and are in the state shown in FIG. 4, the front surface 4 side (not shown) formed by printing simultaneously with the marks B and C on the front surface 4 and the back surface 5 of the insulating layer s2. The lands and the connection terminals on the back surface 5 side are also in predetermined positions without printing misalignment. For this reason, since the land on the front surface 4 side and the connection terminal on the back surface 5 side are surely conducted via the via conductor, for example, a plurality of the wiring boards 1 can be used as relay boards. .

Further, as shown in FIG. 5, the mark B formed on the surface 4 of another insulating layer s2, the same end in the longitudinal direction of the mark C formed on the back surface 5 is short sides each other (far right), When they coincide with each other in the thickness direction of the insulating layer s2, it indicates that the printing deviation occurs between the front and back surfaces 4 and 5 of the insulating layer s2. However, it can also be determined at a glance that the printing deviation between the marks B and C is within the allowable maximum printing deviation amount (z1 × 2 ).
It should be noted that even when the short sides of the opposite ends (left end in FIG. 5) of the marks B and C coincide with each other in the thickness direction of the insulating layer s2, it is at a glance that the printing misalignment is within an allowable range. Can be determined. Further, between the marks B and C, the print misalignment that is intermediate between the state shown in FIG. 4 where there is no print misalignment and the allowable maximum print misalignment amount (z1 × 2 ) shown in FIG. Also, it can be easily determined at a glance that it is within the allowable range.

On the other hand, as shown in FIG. 6, the end portion in the longitudinal direction of the mark B formed on the surface 4 of another insulating layer s2 short side of (right end) is, in the longitudinal direction of the mark C formed on the back surface 5 There is a case that it protrudes outside (right side) from the short side of the same end (right end). In this case, the marks B and C indicate that a printing deviation exceeding the maximum allowable printing deviation amount (z1 × 2 ) occurs between the front and back surfaces 4 and 5 of the insulating layer s2. Therefore, the lands on the front surface 4 side and the connection terminals on the rear surface 5 side, which are not shown, formed for each wiring board 1 in another insulating layer s2 may become unstable or impossible due to mutual printing misalignment. Therefore, it can be judged at a glance that it is a failure.

As described above, according to the multi-piece wiring substrate K of the present invention, the mark B formed on the surface 4 of another insulating layer s2, the overlap degree between the mark C formed on the back surface 5, FIG. It can easily be visually determined that there is no print misalignment 4 or a print misalignment within the allowable range of FIG. Further, as shown in FIG. 6, it can be easily determined that the printing deviation is out of the allowable range.
Furthermore, as described above, even if the printing deviation between the mark B and the mark C in the insulating layer s2 is along the X (long side) direction or the Y (short side) direction, for example, a pair of short sides or long sides By visually observing the degree of overlap between the other marks B and C on the side, it is possible to determine the presence / absence of the printing deviation and the pass / fail judgment. In this case, even when printing misalignment occurs along both the X (long side) direction and the Y (short side) direction of another insulating layer s2, the overlap shown in FIGS. The degree of printing misalignment can be easily determined based on the degree or the degree of overlap shown in FIG.
Therefore, according to the multi-cavity wiring board K , the presence / absence of printing misalignment and the pass / fail judgment can be easily and quickly performed, so that the number of inspection steps and cost can be reduced.

FIG. 7 is a side view showing a lamination process for obtaining the multi-piece wiring board K, and FIG. 8 is a partial side view of the wiring board K after being laminated and fired.
As shown in FIG. 7, FIG. 8, on the surface 2 of the upper layer of the insulating layer s1, the longest mark A is formed one, the surface 4 of another insulating layer s2 of the lower layer side, the shortest mer click B is formed, on its rear surface 5, mark C of the intermediate length are formed. The length dA in the longitudinal direction of the mark A is longer than the length dC of the mark C, and the length dB of the mark B located between the two is shorter than the marks A and C. Incidentally, the mark B of the surface 4 in another insulating layer s2 of the lower layer side, the mark C of the back surface 5, as shown in FIG. 4, proper like in thickness (plane) direction of the insulating layer s2 It is assumed to be in a minute arrangement.

7, as shown in FIG. 8, a mark A formed on the surface 2 of the insulating layer s1, the short mark C than mark A formed on the back surface 5 of another insulating layer s2, the same width as the The center lines n and n, which are rectangles of w and along the width direction of the two, coincide in plan view. Incidentally, the length dA of the mark A is obtained by adding a half z2 of an allowable maximum stacking deviation amount (length: z2 × 2 ) to the outside of both ends of the length dC of the mark C (see Formula 2). ). 8 is a bottom (plan) view of the marks A and C along the arrow indicated by the thick arrow on the left side, and the right side of FIG. 8 is a perspective view of the marks A and C. 9 and 10 are the same.

(Equation 2)
dA = dC + (z2 × 2)

In each of the wiring substrates 1 of the insulating layers s1 and s2, via conductors obtained by firing a conductive paste containing W or the like in the via holes are formed at appropriate positions and formed on the surface 4 of the insulating layer s2. Simultaneously with the mark B, an internal wiring pattern (none of which is shown) is printed and formed for each wiring board 1.
When the marks A and C are on the side surfaces of the insulating layers s1 and s2 and are in the state shown in FIG. 8, they are printed on the front surface 2 of the insulating layer s1 and the back surface 5 of another insulating layer s2 at the same time as the marks A and C. The land 2 on the front surface 2 side and the connection terminal on the back surface 5 side, not shown, are also at predetermined positions where there is no misalignment between the insulating layers s1 and s2. For this reason, since the land on the front surface 2 side and the connection terminal on the back surface 5 side are reliably conducted through the via conductors and the internal wiring pattern, for example, a plurality of wiring boards 1 are connected to a wiring board having a multilayer structure. Available as

Further, as shown in FIG. 9, the mark A formed on the surface 2 of the insulating layer s1, the same end in the longitudinal direction of the mark C formed on the back surface 5 of another insulating layer s2 (leftmost) Short When the sides coincide with each other in the thickness direction of the insulating layers s1 and s2, it indicates that they are misaligned between the insulating layers s1 and s2. However, it can also be easily determined at a glance that the stacking misalignment between the marks A and C is within the allowable maximum stacking misalignment amount (z2 × 2 ).
Note that even when the short sides of the opposite ends (the right end in FIG. 5) of the marks A and C coincide with each other in the thickness direction of the insulating layers s1 and s2, the stacking deviation may be within an allowable range. Easy to judge. Further, between the marks A and C, the stacking shift that is intermediate between the state where there is no stacking shift amount shown in FIG. 8 and the allowable maximum stacking shift amount (z2 × 2 ) shown in FIG. It can be easily determined at a glance that it is within the allowable range.

On the other hand, as shown in FIG. 10, the end portion in the longitudinal direction of the mark C formed on the back surface 5 of another insulating layer s2 short side (leftmost) is a mark A formed on the surface 2 of the insulating layer s1 May protrude outside (left side) from the short side of the same end (left end) in the longitudinal direction. In such a case, it is indicated that a stacking shift exceeding the allowable stacking shift amount (z2 × 2 ) occurs between the insulating layers s1 and s2 on which the marks A and C are printed / formed. Accordingly, the lands on the front surface 2 and the connection terminals on the rear surface 5 side (not shown) formed on the wiring board 1 in the insulating layers s1 and s2 may become unstable or impossible to conduct due to mutual printing misalignment. , It can be determined at a glance that it is a failure.

As described above, according to the multi several up wiring board K of the present invention, between the mark A formed on the surface 2 of the insulating layer s1, a mark C which is formed on the back surface 5 of another insulating layer s2 Depending on the degree of overlap, it can be easily determined visually that there is no misalignment in FIG. 8 or a misalignment within the allowable range in FIG. Further, as shown in FIG. 10, it can be easily determined that the stacking deviation is out of the allowable range.
Further, as described above, even if the stacking deviation between the insulating layers s1 and s2 is, for example, along the X (long side) direction or the Y (short side) direction, the mark A on the pair of short sides or long sides. , C makes it possible to determine the presence / absence of print misalignment and pass / fail judgment by visually checking the degree of mutual overlap. In this case, the marks shown in FIGS. 8 and 9 can be obtained even when the stacking misalignment occurs along both the X (long side) direction and the Y (short side) direction of the insulating layers s1 and s2. The success or failure of the stacking deviation can be easily determined based on the degree of overlap between A and the mark C or the degree of overlap shown in FIG.
For this reason , according to the multi-cavity wiring board K, it is possible to easily and quickly determine whether or not there is a stacking deviation, and therefore, it is possible to reduce the number of inspection steps and costs.

Further, FIG. 8, also in FIG. 9, the mark B formed on the surface 4 of another insulating layer s2, Two (left) and mark C formed on the back surface 5, and FIG. 4 and FIG. 5 If there is a printing deviation within the range , there is no printing deviation between the internal wiring pattern formed on the front surface 4 of the insulating layer s2 and the connection terminal formed on the back surface 5 or it is within an allowable range. This can be easily determined by visually observing the side surface of the wiring board K for individual pieces.
Therefore, according to the multi-cavity wiring board K of the present invention, the overlap of the marks A and C is accompanied with the presence / absence of the printing deviation between the two marks B and C sandwiching another insulating layer s2 (the remaining) and the pass / fail. The presence / absence of the misalignment of the insulating layers s1 and s2 and the pass / fail can be easily determined depending on the degree.

Figure 11 shows a different morphology than the previous SL multi-piece wiring substrate K.
As shown on the left side of FIG. 11, the longest mark A on the surface 2 of another insulating layer s1, to form a short shortest mark B than the mark A on the back surface 3, the length along the longitudinal direction of both The difference between the lengths dA and dB is set to the maximum printing deviation amount (z1 × 2) , as in the case of Equation 1. The marks A and B are formed so as to be exposed also on the side surface of another insulating layer s1.
The mark A, an overlap of about in a plan view between B, similarly to FIG. 4 to FIG. 5, there are no printing misalignment, by a within the allowable range, the front and rear surface 2 of another insulating layer s1 the land and the connection terminal to be printed, formed, through a via conductor extending through the insulating layer s1 (not shown), ensure that the relay substrate and the multi-several-up wiring board Ru plurality obtained to conduct the be able to.

Further, as shown on the right side of FIG. 11, the lower layer side of another insulating layer s1 forming the mark A and mark B in Table-back surface 2, an intermediate length of the mark A and mark B on the back surface 5 laminating and baking the insulating layer s2 forming the difference mark C, may be formed the same multi several up wiring board K. The marks A to C are formed so as to be exposed also on the side surface of the wiring board K.
Even in such a multi-cavity wiring board K, the overlap between the mark A formed on the front surface 2 of another insulating layer s1 and the mark C formed on the back surface 5 of the insulating layer s2 is appropriately divided as shown in FIG. 9 to the maximum stacking misalignment amount (z2 × 2 ) of the insulating layers s1 and s2 shown in FIG. 9, there is no printing misalignment or misalignment, and both of these are within the allowable range. It can be easily determined whether there is any. Note that the stacking deviation between the insulating layers s1 and s2 may be inspected according to the overlapping degree of the marks B and C.

FIG. 12 shows a multi-cavity wiring board K1 having a different form of the wiring board K and the like.
FIG as shown on the left side of 12, the mark C on the surface 4 of another insulating layer s2, form long mark A than mark C on the back surface 5, the length dA along the longitudinal direction of both, dC Is the maximum printing deviation amount (z1 × 2) as in the case of Equation 2. The marks A and C are also formed so as to be exposed also on the side surface of the insulating layer s2.
The mark A, an overlap of about in a plan view between C, similarly to FIG. 4 to FIG. 5, there are no printing misalignment, by a within the allowable range, the front and rear surface 4, 5 of another insulating layer s2 the land and the connection terminal to be printed, formed, through a via conductor extending through the insulating layer s2 (not shown), and a multi several up wiring board that Yusuke plurality of relay substrate to reliably conduct the can do.

Further, as shown on the right side of FIG. 12, the upper layer side of another insulating layer s2 forming an intermediate length of the mark C and the longest mark A in front surface 4 and the back surface 5, the mark on the surface 2 C by laminating and baking the insulating layer s1 formed a short shortest mark B than may be formed the same multi several up wiring board K1. That is, mark C is longer than the short and mark B than mark A. The marks A to C are formed so as to be exposed also on the side surface of the wiring board K1.
The wiring board K in FIGS. 1 and 2 is different from the wiring board K1 in which the marks A to C are arranged in the thickness direction, and the mark B formed on the surface 2 of the insulating layer s1 and the insulating layer s2 If the overlap with the mark C formed on the front surface 4 is within the range from the proper equally-arranged state shown in FIG. 12 to the maximum stacking deviation (z 2 × 2 ) between the insulating layers s1 and s2. It can be easily determined whether there is no printing misalignment or stacking misalignment, or whether both of these are within the allowable range. Note that the stacking deviation between the insulating layers s1 and s2 may be inspected according to the overlapping degree of the marks A and C.

Figure 13 shows another different embodiment of the like multi-piece wiring substrate K2 before Symbol wiring board K.
As shown on the left side of FIG. 13, the mark A on the surface 4 of another insulating layer s2, forming a short mark C than mark A on the back surface 5, the length dA along both longitudinal, dC Is the maximum printing deviation amount (z1 × 2) as in the case of Equation 2. The marks A and C are also formed so as to be exposed also on the side surface of the insulating layer s2.
The mark A, an overlap of about in a plan view between C, similarly to FIG. 4 to FIG. 5, there are no printing misalignment, by a within the allowable range, the front and rear surface 4, 5 of another insulating layer s2 the land and the connection terminal to be printed, formed, through a via conductor extending through the insulating layer s2 (not shown), and a multi several up wiring board that Yusuke plurality of relay substrate to reliably conduct the can do.

Further, as shown on the right side of FIG. 13, the upper layer side of another insulating layer s2 forming the mark A and mark C in front surface 4 and the back surface 5, on the surface 2 shorter than mark C shortest mer by laminating and baking the insulating layer s1 formed with click B, the may be formed a number of same way-piece wiring substrate K2. That is, mark A is longer than mark C and mark B. The marks A to C are formed so as to be exposed also on the side surface of the wiring board K2.
Even with the multi-piece wiring board K2 as described above, the overlap between the mark B formed on the surface 2 of the insulating layer s1 and the mark C formed on the surface 4 of another insulating layer s2 is appropriate as shown in FIG. As long as it is within the range from the state of equally divided arrangement to the maximum stacking misalignment amount (z 2 × 2 ) between the insulating layers s1 and s2, there is no print misalignment or misalignment, and both of these are within the allowable range. It can be easily determined whether there is any. Note that the stacking deviation between the insulating layers s1 and s2 may be inspected according to the overlapping degree of the marks A and B.

FIG. 14 is a plan view of a multi-cavity wiring board K3 which is an applied form of the wiring board K. FIG. As shown in FIG. 14, the wiring board K3 has a total of nine wirings in the insulating laminate S composed of the insulating layers s1 and s2, each having three vertical and horizontal sections separated by the predetermined cutting line c indicated by a broken line. A total of four product areas a each consisting of the substrate 1 and the ears m surrounding the substrate 1 are provided in both vertical and horizontal directions. The four product areas a are cut along the planned cutting line c1 indicated by the thick broken line in FIG.
As shown in FIG. 14, near the center of the long side and the short side exposed to the outside surface of each product area a, as with the wiring board K, mark B (not shown) with the mark A, and the C , FIG. 4, the proper placement without misregistration and laminating misalignment in FIG 8, FIG. 5, and the maximum print misalignment and maximum stacking deviation of FIG. 9 is formed within an acceptable range.

Moreover, in the ear | edge part m between adjacent product areas a and a, the planar view is nearly square (rectangular) near the center of the planned cutting line c1 passing through the middle across the planned cutting line c1. similar to the mark a, mark B, not shown, it is a C, and is formed by the similar overlapping range.
According to a multi-piece wiring substrate K3 as described above, you exposed on the outer surface B, the C, presence and acceptability of the print deviation between the surface 4 and the back surface 5 of the further insulating layer s2 together with possible determination Whether or not there is a misalignment between the insulating layers s1 and s2 can be determined by the degree of overlap between the mark A formed on the front surface 2 of the insulating layer s1 and the mark C formed on the back surface 5 of another insulating layer s2. Furthermore, along the cutting line c1, by marks A~C exposed on the cut surface of each product area a obtained when cut (side), similar to the above misregistration, and the presence or absence of laminating misalignment both and and their acceptability can be easily determined.
The arrangement of the marks A to C on the multi-cavity wiring board K3 may be in the form shown on the right side of FIGS.

The multi-cavity wiring boards K, K1 to K3 may be configured as an insulating laminate S in which two or more insulating layers excluding another insulating layer are stacked.
Further, the marks A to C may be formed in one set or two or more sets at arbitrary positions on the outer surface of the multi-cavity wiring boards K and K1 to K3.
Furthermore, the mark may be applied to a multi-piece wiring board composed of a plurality of insulating layers of four or more different lengths in the longitudinal direction.
In addition, the insulating layer is made of, for example, a core substrate made of a BT resin, a resin film or a resin layer, and a multi-piece wiring substrate made by laminating them, and the mark A ˜C can be formed by Cu plating as well as the internal wiring pattern, via conductor, land, and connection terminal.

Plan view of an embodiment of a multi-several-up wiring board that by the present invention. The perspective view which shows the wiring board for multi-piece taking of FIG. FIG. 2 is a partial side view of the multi-cavity wiring board of FIG. 1. Schematic which shows a part of said multi-cavity wiring board. Schematic which shows a part of wiring board for multi-piece picking from which the position of a mark differs. Schematic which shows a part of wiring board for multi-piece picking from which the position of a mark differs further. Schematic which shows a part of said wiring board for multi-piece picking. Schematic which shows the wiring board for multi-cavity of FIG. Schematic which shows the wiring board for multi-pieces from which the position of a mark differs from the above. Schematic which shows the wiring board for multi-piece picking from which the position of a mark differs further. Schematic which shows the wiring board for multi-pieces of a different form . Furthermore, the schematic which shows the wiring board for multi-piece taking of a different form . The schematic diagram which shows the wiring board for multi-piece taking of another form . The top view which shows the application form of the said multi-cavity wiring board.

Explanation of symbols

A ……………………… Longest mark B ……………………… Shortest mark C ……………………… Medium length marks K, K1 to K3 ……… Many Wiring boards for individual production s1, s2 ......... Insulating layer / separate insulating layers 2, 4 ............... Front side 3, 5 ............... Back side dA to dC ............... length
z1 × 2 ............ Maximum allowable printing deviation
z2 × 2 ...... …… Maximum allowable stacking displacement n …………………… Center line

Claims (4)

An insulating layer on which either one of the marks A, B, and C having a rectangular shape in plan view is formed on either the front surface or the back surface;
Thickness direction that is laminated adjacent to the back side or the front side of the insulating layer, has a rectangular shape in plan view, and the remaining two marks of the marks A, B, and C other than the one mark include the one mark Another insulating layer that overlaps with each other and one of the two marks is formed on the front surface and the other is formed on the back surface;
The unrealized plan view a rectangular surface, back surface, and a multi-piece wiring board having four outer surfaces located therebetween,
The length of the mark A exposed to the outside side face of the multi-piece wiring substrate, the mark B, longer than the length of C, the length of the mark C are marked A, with an intermediate of the length of B,
The difference in length between the one mark and one of the remaining two marks coincides with the maximum allowable stacking deviation amount,
The difference in length between the remaining two marks coincides with the maximum allowable printing deviation amount.
A wiring board for multi-piece production characterized by the above. The multi-piece wiring substrate, a rectangular in plan view, the mark A, B, C are formed on each outer side surface adjacent in such a multi-piece wiring substrate,
The multi-cavity wiring board according to claim 1, wherein: The insulating layer and the other insulating layer are large plate insulating plates having a product region to be a plurality of wiring boards and having an ear around the product region, and the outer surface or the ear of the ear The cross sections of the marks A, B, C are exposed on the cut surface of
The multi-cavity wiring board according to claim 1 or 2, characterized in that The overlap between the two remaining marks is that each of the mark rectangles parallel to the outer surface has a shape in which the center lines along the width direction of the rectangles orthogonal to the outer surface coincide in plan view. In the range to the form in which the short sides of the same end portion in the longitudinal direction of the same coincide with each other in the thickness direction of the wiring board for multi-cavity,
The multi-cavity wiring board according to any one of claims 1 to 3, wherein:

Images