JP2007103601A - Wiring board for multi-piece arrangement - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board for multi-piece arrangement capable of easily judging presence of dislocation in formation between upper and lower wiring layers, with an insulating layer in-between, as well as dislocation in stacking between a plurality of insulation layers forming the wiring layer, and capable of easily judging tolerable/untolerable for dislocation. <P>SOLUTION: In a wiring board K for multi-piece arrangement, a first mark C and second mark B as square in top view are separately formed on a front surface 4 and a rear surface 5 of an insulating layer s2 on the lower layer side. Relating to the length of exposure of the first mark C and the second mark B on the side surface of the wiring board K for multi-piece arrangement, length dC of the first mark C is longer than length dB of the second mark, with the first mark C and the second mark B overlapping each other in the thickness direction of the wiring board K for multi-piece arrangement. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a multi-cavity wiring board that can easily detect and determine pass / fail of printing misalignment between conductor patterns formed on the front and back surfaces of an insulating layer or misalignment between a plurality of insulating layers to be laminated. About.

According to the recent trend toward higher density and higher performance of wiring on the wiring board, printing misalignment between the upper and lower wiring layers sandwiching the insulating layer, and the wiring layers formed for each of the multiple insulating layers to be stacked It is demanded to reduce the problems caused by the stacking deviation.
For example, in a multi-layer multi-layer wiring board in which wiring circuits and via conductors are formed for each of a plurality of insulating layers to be stacked, a pattern in which the width in a direction orthogonal to the end face of the multi-layer wiring board monotonously changes (for example, A multilayer wiring board has been proposed in which a right-angled triangle pattern in plan view) is formed for each insulating layer, and such a pattern is exposed on an end face after lamination (see, for example, Patent Document 1).

JP 2005-101299 A (pages 1 to 12, FIGS. 1 and 2)

  According to the multilayer wiring board of Patent Document 1, it is possible to easily determine whether or not there is a stacking deviation by detecting a difference in length between a plurality of patterns exposed on the end face. However, it is necessary to measure, for each multilayer wiring board, the difference in length between the plurality of patterns exposed on the end face to determine whether or not such stacking deviation is within the allowable range. For this reason, there existed a problem that the inspection process of the said multilayer wiring board requires a man-hour and raises cost.

  The present invention solves the problems described in the background art, the presence or absence of printing misalignment between the upper and lower wiring layers sandwiching the insulating layer, the stacking misalignment between the plurality of insulating layers forming the wiring layer, and It is an object of the present invention to provide a wiring board for multi-cavity that can be easily judged whether it is shifted or not.

Means for Solving the Problems and Effects of the Invention

In order to solve the above problems, the present invention provides a plurality of marks provided on the front and back surfaces of the insulating layer or simultaneously with the wiring layers to be formed on the plurality of insulating layers to be laminated, with a viewing angle along the thickness direction of the wiring board. The idea is to apply the maximum length of the allowable deviation amount to the difference in length between a plurality of marks.
That is, in the first multi-cavity wiring board according to the present invention (Claim 1), either one of the first mark and the second mark which are rectangular in a plan view is formed on the front surface and the back surface of the insulating layer. The length of the first mark and the second mark exposed on the side surface of the multi-piece wiring board is such that the first mark is longer than the second mark, and the first mark and the second mark are It is characterized in that they overlap each other in the thickness direction of the multi-piece wiring board.

According to this, when the difference in length between the first mark and the second mark is set to be twice the maximum allowable deviation amount as will be described later, both ends of the first mark overlapped with each other. If it falls within the range, it can be easily determined that the printing misalignment of the front and back conductor layers printed or patterned simultaneously with each mark is within the allowable range. On the other hand, if one end of the second mark protrudes outside one end of the overlapping second mark, it can be determined that the printing deviation deviates from the allowable range at a glance. Furthermore, even if there is a printing misalignment along the X direction of the insulating layer along the width direction of the first and second marks, such a misprinting is caused by the overlap of both marks formed separately along the Y direction of the insulating layer. By observing the degree, pass / fail can be easily determined. Accordingly, since it can be easily determined whether or not the misalignment is within an allowable range at the same time as the presence or absence of the printing misalignment, the number of man-hours for the inspection process of the multi-chip wiring board can be reduced and the cost can be reduced.
In the present specification, pattern misalignment of patterning by photolithography technology is included in print misalignment.

The insulating layer is made of, for example, a ceramic mainly composed of alumina, for example, a glass-ceramic that is a kind of low-temperature fired ceramic made of glass-alumina, or a resin such as BT resin. Via conductors pass through between the two.
Further, the first multi-cavity wiring board includes a wiring board made of a single insulating layer, a relay board, or a mounting package for electronic parts such as a SAW filter, a crystal vibrator, and a piezoelectric vibrator. The one having a plurality of substrates is included.
Further, the first mark and the second mark are equally arranged in a plan view along the thickness direction of the insulating layer, that is, both ends of the first mark have the same length at both ends in the longitudinal direction of the second mark. The marks are overlapped so as to be exposed, and the difference between the lengths of both marks is twice the maximum allowable deviation. The deviation refers to printing deviation (or patterning deviation) of a conductor layer (land or connection terminal) to be formed on the front and back surfaces of the insulating layer.
In addition, the side surface of the multi-cavity wiring board includes not only the outer surface of the substrate but also a cut surface that appears when the substrate is cut along a planned cutting line.

  The second multi-cavity wiring board according to the present invention (Claim 2) is a front and back surfaces of two insulating layers adjacent to each other in the vertical direction of the multi-cavity wiring board formed by laminating a plurality of insulating layers. In addition, one of the third mark and the fourth mark that are rectangular in plan view is formed, and the length exposed on the side surface of the multi-cavity wiring board is longer than the fourth mark. At the same time, the third mark and the fourth mark overlap with each other in the thickness direction of the multi-cavity wiring board.

According to this, when the difference in length between the third mark and the fourth mark is set to twice the maximum allowable deviation amount as will be described later, the both ends of the third mark overlapped at both ends of the fourth mark. If it is within the range, it can be easily determined that the stacking deviation between a plurality of insulating layers having a conductor layer printed or patterned at the same time as each mark is within an allowable range. On the other hand, if any one end of the fourth mark is outside of any one end of the third mark that overlaps, it can be determined that the stacking deviation deviates from the allowable range at a glance. Further, even if a stacking shift along the X direction between the plurality of insulating layers exists along the width direction of the third and fourth marks, the stacking shift is separately formed along the Y direction of the plurality of insulating layers. By observing the degree of overlap between the third and fourth marks, it is possible to easily determine whether or not the mark is acceptable. Therefore, since it can be determined whether or not the misalignment is within an allowable range at the same time as the presence or absence of misalignment between the plurality of insulating layers, the number of steps in the inspection process for the multi-cavity wiring board can be reduced and the cost can be reduced.
In addition to the case of two adjacent insulating layers, the plurality of insulating layers include a multilayer insulating layer of three or more layers by determining the success or failure of stacking deviation between adjacent insulating layers.

  Furthermore, in the present invention, a fifth mark having a rectangular shape in a plan view is formed on the front surface or the back surface of the insulating layer located between the third mark and the fourth mark. The length of the fifth mark exposed on the side surface is shorter than the third mark and longer than the fourth mark, or shorter than the third mark and the fourth mark, or the third mark and the fourth mark. A third multi-piece wiring board (claim 3), which is longer than the above, is also stepped on.

  According to this, for example, among the two insulating layers to be laminated, the fifth mark and the fourth mark are individually overlapped and formed on the front and back surfaces of the lower insulating layer, and the overlapping degree of both marks By observing the above, it is possible to determine whether or not the printing misalignment between the conductor layers printed on the front surface and the back surface is the same as in the first multi-chip wiring board. At the same time, by observing the degree of overlap between the third mark formed on the surface of the upper insulating layer and the fourth mark or the fifth mark in the lower insulating layer, the acceptance / rejection of the stacking deviation between the insulating layers at a glance. Can be easily determined. Furthermore, even if printing displacement or stacking displacement along the X direction of each insulating layer exists along the width direction of the third to fifth marks, such printing displacement is separately formed along the Y direction of each insulating layer. By observing the degree of overlap of the third to fifth marks, it is possible to easily determine whether or not the mark is acceptable. Therefore, since it is possible to determine at a glance whether the misalignment and the misalignment of the multi-wiring substrate having a plurality of multi-layer wiring substrates at the same time, it is possible to reduce the man-hour and cost of the inspection process.

  In order to keep printing deviation and stacking deviation within narrow tolerances, for example, the longest third mark is selected from the fourth mark or the fifth mark, whichever is longer, and the shortest second mark is selected. The fifth mark or the fourth mark that is longer than one of these and shorter than the third mark is selected as the mark to be compared with the fourth mark or the fifth mark. The first mark may be the third mark, and the second mark may be the fourth mark. That is, the names of the first to fifth marks are relative and convenient names.

In addition, in the present invention, the overlap between the first mark and the second mark, the overlap between the third mark and the fourth mark, or the overlap between the third mark or the fourth mark and the fifth mark From the form in which the center lines along the width direction of the rectangle of each mark match in plan view, to the form in which the short sides of the same end in the longitudinal direction of the rectangle of each mark match in the thickness direction of the insulating layer A multi-piece wiring board in the range of (4) is also included.
According to this, it is possible to quickly and accurately determine whether or not the above-described printing misalignment or stacking misalignment is made, and it is possible to reliably increase the efficiency of the inspection process.

  In other words, in the present invention, the first, second mark, and third to fifth marks are made of a conductor pattern, and are rectangular (rectangular) having a certain width or more perpendicular to each longitudinal direction in plan view. A multi-cavity wiring board exhibiting a) may also be included. According to this, the first to fifth marks can be simultaneously formed by printing or patterning with the same mask pattern as the conductor layer such as the connection terminal and the wiring layer to be formed on the front surface and the back surface of the insulating layer, and printing misalignment thereof. And can be used for determination of misalignment between insulating layers.

  Further, in the present invention, the insulating layer is a large plate insulating plate having a product region to be a plurality of wiring boards and having an ear portion around the product region, and the outer surface of the ear portion or A wiring board in which cross sections of the first, second mark, and third to fifth marks are exposed on the cut surface of the ear may be included. According to this, without using the product area, by observing the degree of overlap between the marks exposed on the outer surface of the surrounding ears, the above-described print misalignment or stacking misalignment can be performed without damaging the product area. It is possible to easily determine the presence / absence and acceptance / rejection.

  Further, according to the present invention, the insulating layer has a plurality of product regions to be a plurality of wiring boards, and has an ear portion between the product regions and the outer periphery of the product region, and in the vicinity of each ear portion. Alternatively, a multi-piece wiring board in which the first, second, and third to fifth marks are formed along the middle of each ear may be included. According to this, without using each of the plurality of product regions, by observing the degree of overlap between the marks exposed on the outer surface of the ear portion surrounding them and the cut surface cut along the middle of the ear portion, Without damaging the product area, it is possible to easily and efficiently determine the presence / absence and pass / fail of the above-described printing misalignment and stacking misalignment.

In the following, the best mode for carrying out the present invention will be described.
FIG. 1 is a plan view showing a multi-piece wiring board K according to an embodiment of the present invention, FIG. 2 is a perspective view showing the wiring board K, and FIG. 3 is a partial side view thereof.
As shown in FIG. 1 and FIG. 2, the multi-cavity wiring board K includes an insulating laminated body S in which two upper and lower insulating layers s1 and s2 are laminated, and the insulating layers s1 and s2 along the XY direction. A product region having a total of nine wiring boards 1 divided in each direction by three broken wiring lines c indicated by broken lines, and ears m surrounding these. The insulating layers s1 and s2 have a rectangular shape in a plan view, and are ceramics obtained by firing a green sheet containing alumina, for example, and are fired after the insulating laminate S is formed in advance. The insulating layers s1 and s2 may be glass-ceramic which is a kind of low-temperature fired ceramic.

  As shown in FIGS. 1 and 2, the surface 2 of the insulating layer s <b> 1 has a longest rectangular shape (rectangular shape) in the vicinity of the center of each of the ears m of the pair of opposed long sides and the pair of short sides. Mark (third mark) A is formed. Further, at the same position between the back surface 3 of the insulating layer s1 and the front surface 4 of the insulating layer s2, the mark in the plan view is rectangular (rectangular) and has the shortest longitudinal direction (second mark, fifth mark). B is formed. Further, at substantially the same position as the above on the back surface 5 of the insulating layer s2, a mark (first mark, fourth mark) having a rectangular (rectangular) plan view and an intermediate length between the mark A and the mark B in the longitudinal direction. C is formed. The marks A to C are also exposed on the outer surface (side surface) of the wiring board K.

  The marks A to C are conductor patterns made of W or Mo and having a thickness of several μm to several tens of μm, and the product areas (1, 1, 1) on the front surface 2 of the insulating layer s1 and the front surface 4 and the back surface 5 of the insulating layer s2. ...) when the land, the internal wiring pattern, or the connection terminal (none of which is shown) is screen-printed, etc., printed at the center of each side of the ear m and fired at the same time. is there. As shown in FIG. 3, the length in the longitudinal direction in the side view is, for example, mark A: 1 mm, mark B: 0.6 mm, and mark C: 0.8 mm. Further, it is desirable that the width (w) of the marks A to C is, for example, 0.2 to 0.4 mm and common. When the insulating layers s1 and s2 are made of glass-ceramic, Cu or Ag is used for the marks A to C.

  As shown in FIGS. 1 and 2, the marks A to C are formed on the four sides of the insulating layers s1 and s2 because the marks B on the front and back surfaces 4 and 5 of the insulating layer s2 of the multi-layer wiring board K are formed. Even if the printing misalignment between the mark B and the mark C is, for example, along the X (long side) direction, the presence / absence of the printing misalignment and the pass / fail judgment are made by visually checking the degree of overlap between the marks B and C on the pair of short sides. This is because it becomes possible. Further, even if the stacking misalignment between the insulating layers s1 and s2 is, for example, along the Y (short side) direction, by checking the degree of overlap between the marks A and C on the pair of long sides, The pass / fail judgment can be made.

Here, the first multi-cavity wiring board according to the present invention will be described with reference to FIGS. As shown in FIG. 4, a mark (second mark) B formed on the front surface 4 of the insulating layer s2 and a mark (first mark) C longer than the mark B formed on the back surface 5 are rectangles having the same width w. In addition, the center lines n and n along the width direction of both coincide with each other in plan view. 4 is a plan view of the marks B and C along the arrow indicated by the thick arrow on the left side, and the right side of FIG. 4 is a perspective view of the marks B and C. The same applies to 6.
That is, the marks B and C in FIG. 4 are equally arranged in a plan view, indicating that there is no printing misalignment between the front and back surfaces 4 and 5 of the insulating layer s2. Incidentally, the length dC of the mark C is obtained by adding an allowable maximum printing deviation amount (length) z1 to the outside of both ends of the length B of the mark B (see Formula 1).

(Equation 1)
dC = dB + (z1 × 2)

  In each wiring board 1 of the insulating layer s2, via conductors (both not shown) are formed at appropriate positions by firing a conductive paste containing W or Mo filled in a via hole punched in advance. When the marks B and C are on the side surfaces of the insulating layer s2 and are in the state shown in FIG. 4, the front surface 4 side (not shown) formed by printing simultaneously with the marks B and C on the front surface 4 and the back surface 5 of the insulating layer s2. The lands and the connection terminals on the back surface 5 side are also in predetermined positions without printing misalignment. For this reason, since the land on the front surface 4 side and the connection terminal on the back surface 5 side are surely conducted via the via conductor, for example, a plurality of the wiring boards 1 can be used as relay boards. .

Further, as shown in FIG. 5, the same end (right end) in the longitudinal direction of the mark (second mark) B formed on the front surface 4 of the insulating layer s2 and the mark (first mark) C formed on the back surface 5 When the short sides coincide with each other in the thickness direction of the insulating layer s2, it indicates that printing misalignment occurs between the front and back surfaces 4 and 5 of the insulating layer s2. However, it can be determined at a glance that the printing misalignment between the marks B and C is within the allowable maximum printing misalignment amount (z1).
It should be noted that even when the short sides of the opposite ends (left end in FIG. 5) of the marks B and C coincide with each other in the thickness direction of the insulating layer s2, it is at a glance that the printing misalignment is within an allowable range. Can be determined. Further, between the marks B and C, a print misalignment between the state shown in FIG. 4 where there is no print misalignment and the allowable maximum print misalignment amount (z1) shown in FIG. It can be easily determined at a glance that it is within the allowable range.

  On the other hand, as shown in FIG. 6, the short side of the end (right end) in the longitudinal direction of the mark (second mark) B formed on the surface 4 of the insulating layer s2 is the mark formed on the back surface 5 (first mark). In some cases, the outer side (right side) may protrude beyond the short side of the same end (right end) in the longitudinal direction with C. In this case, the marks B and C indicate that a printing deviation exceeding the maximum allowable printing deviation amount (z1) occurs between the front and back surfaces 4 and 5 of the insulating layer s2. Therefore, the lands on the front surface 4 side (not shown) and the connection terminals on the rear surface 5 side that are formed for each of the wiring boards 1 in the insulating layer s2 may become unstable or impossible due to mutual printing misalignment. It can be judged at a glance that it is a failure.

As described above, according to the first multi-cavity wiring board according to the present invention, the mark (second mark) B formed on the front surface 4 of the insulating layer s2 and the mark (first mark) formed on the back surface 5 are provided. Depending on the degree of overlap with C, it can be easily determined visually that there is no print misalignment in FIG. 4 or a print misalignment within the allowable range in FIG. Further, as shown in FIG. 6, it can be easily determined that the printing deviation is out of the allowable range.
Furthermore, as described above, even if the printing deviation between the mark B and the mark C in the insulating layer s2 is along the X (long side) direction or the Y (short side) direction, for example, a pair of short sides or long sides By visually observing the degree of overlap between the other marks B and C on the side, it is possible to determine the presence / absence of the printing deviation and the pass / fail judgment. In this case, even if printing misalignment occurs along both the X (long side) direction and the Y (short side) direction of the insulating layer s2, it is the degree of overlap shown in FIGS. The pass / fail of printing misalignment can be easily determined depending on the degree of overlap shown in FIG.
Therefore, according to the first multi-cavity wiring board, it is possible to easily and quickly determine whether or not there is a printing misalignment, and whether or not to pass the print misalignment, so that the number of inspection steps and cost can be reduced.

FIG. 7 is a side view showing a lamination process for obtaining the multi-piece wiring board K, and FIG. 8 is a partial side view of the wiring board K after being laminated and fired.
As shown in FIGS. 7 and 8, a mark (third mark) A is formed on the surface 2 of the upper insulating layer s1, and a mark (fifth mark) is formed on the surface 4 of the lower insulating layer s2. ) B is formed, and a mark (fourth mark) C is formed on the back surface 5 thereof. The length dA in the longitudinal direction of the mark A is longer than the length dC of the mark C, and the length dB of the mark B located between the two is shorter than the marks A and C. In addition, the mark (fifth mark) B on the front surface 4 and the mark (fourth) on the back surface 5 in the lower insulating layer s2 are in the thickness (planar) direction of the insulating layer s2, as shown in FIG. It is assumed that it is in an appropriate equal distribution.

  As shown in FIGS. 7 and 8, a mark (third mark) A formed on the front surface 2 of the insulating layer s1, and a mark (fourth mark) C shorter than the mark A formed on the back surface 5 of the insulating layer s2. Is a rectangle having the same width w as described above, and the center lines n and n along the width direction of the two coincide in plan view. Incidentally, the length dA of the mark A is obtained by adding an allowable maximum stacking deviation amount (length) z2 to the outside of both ends of the length dC of the mark C (see Formula 2). 8 is a bottom (plan) view of the marks A and C along the arrow indicated by the thick arrow on the left side, and the right side of FIG. 8 is a perspective view of the marks A and C. 9 and 10 are the same.

(Equation 2)
dA = dC + (z2 × 2)

In each of the wiring substrates 1 of the insulating layers s1 and s2, via conductors obtained by firing a conductive paste containing W or the like in the via holes are formed at appropriate positions and formed on the surface 4 of the insulating layer s2. Simultaneously with the mark B, an internal wiring pattern (none of which is shown) is printed and formed for each wiring board 1.
When the marks A and C are on the side surfaces of the insulating layers s1 and s2 and are in the state shown in FIG. 8, they are formed on the front surface 2 of the insulating layer s1 and the back surface 5 of the insulating layer s2 by printing simultaneously with the marks A and C. The land on the front surface 2 side and the connection terminal on the back surface 5 side, not shown, are also in predetermined positions without any misalignment between the insulating layers s1 and s2. For this reason, since the land on the front surface 2 side and the connection terminal on the back surface 5 side are reliably conducted through the via conductors and the internal wiring pattern, for example, a plurality of wiring boards 1 are connected to a wiring board having a multilayer structure. Available as

Further, as shown in FIG. 9, the same end in the longitudinal direction of the mark (third mark) A formed on the front surface 2 of the insulating layer s1 and the mark (fourth mark) C formed on the back surface 5 of the insulating layer s2 When the short sides of the portion (left end) coincide with each other in the thickness direction of the insulating layers s1 and s2, it indicates that they are misaligned between the insulating layers s1 and s2. However, it can be easily determined at a glance that the stacking misalignment between the marks A and C is within the allowable stacking misalignment amount (z2).
Note that even when the short sides of the opposite ends (the right end in FIG. 5) of the marks A and C coincide with each other in the thickness direction of the insulating layers s1 and s2, the stacking deviation may be within an allowable range. Easy to judge. Further, a misalignment between the marks A and C, which is intermediate between the state where there is no misalignment shown in FIG. 8 and the maximum allowable misalignment (z2) shown in FIG. 9, is also allowed. Can be easily determined at a glance.

  On the other hand, as shown in FIG. 10, the mark (fourth mark) C formed on the back surface 5 of the insulating layer s2 has a short side at the end (left end) in the longitudinal direction. The third mark (A) may protrude outward (left side) from the short side of the same end (left end) in the longitudinal direction. In such a case, it is indicated that a stacking shift exceeding the allowable stacking shift amount (z2) is generated between the insulating layers s1 and s2 on which the marks A and C are printed / formed. Accordingly, the lands on the front surface 2 and the connection terminals on the rear surface 5 side (not shown) formed on the wiring board 1 in the insulating layers s1 and s2 may become unstable or impossible to conduct due to mutual printing misalignment. , It can be determined at a glance that it is a failure.

As described above, according to the second multi-cavity wiring board K according to the present invention, the mark (third mark) A formed on the front surface 2 of the insulating layer s1 and the mark formed on the back surface 5 of the insulating layer s2. Depending on the degree of overlap with (fourth mark) C, it can be easily determined visually that there is no stacking deviation in FIG. 8 or a stacking deviation within the allowable range in FIG. Further, as shown in FIG. 10, it can be easily determined that the stacking deviation is out of the allowable range.
Further, as described above, even if the stacking deviation between the insulating layers s1 and s2 is, for example, along the X (long side) direction or the Y (short side) direction, the mark A on the pair of short sides or long sides. , C makes it possible to determine the presence / absence of print misalignment and pass / fail judgment by visually checking the degree of mutual overlap. In this case, the marks shown in FIGS. 8 and 9 can be obtained even when the stacking misalignment occurs along both the X (long side) direction and the Y (short side) direction of the insulating layers s1 and s2. The success or failure of the stacking deviation can be easily determined based on the degree of overlap between A and the mark C or the degree of overlap shown in FIG.
Therefore, according to the second multi-cavity wiring board, since it is possible to easily and quickly determine whether or not there is a stacking deviation, it is possible to reduce the number of inspection steps and cost.

8 and 9, the mark (fifth mark) B formed on the front surface 4 of the insulating layer s2 and the mark (fourth mark) C formed on the back surface 5 are the same as those shown in FIGS. If the printing deviation is not within the range, there may be no printing deviation between the internal wiring pattern formed on the front surface 4 of the insulating layer s2 and the connection terminal formed on the back surface 5, or it may be within an allowable range. This can be easily determined by visually observing the side surface of the wiring board K for collection.
According to the third multi-cavity wiring board K of the present invention, the insulating layer s1 depends on whether or not there is a printing deviation between the marks B and C across the insulating layer s2 and whether or not the marks A and C overlap. , S2 and the presence / absence of the misalignment and the pass / fail status can be easily determined.

FIG. 11 shows different forms of the first to third multi-chip wiring boards K.
As shown on the left side of FIG. 11, a mark (first mark) A is formed on the front surface 2 of the insulating layer s1, and a mark (second mark) B shorter than the mark A is formed on the back surface 3, along the longitudinal direction of both. The difference between the lengths dA and dB is set to be twice the maximum printing deviation amount z3 as in the equation 1. The marks A and B are formed so as to be exposed also on the side surface of the insulating layer s1.
The degree of overlap between the marks A and B in a plan view is printed on the front and back surfaces 2 and 3 of the insulating layer s1 by making sure that there is no printing misalignment or within an allowable range, as in FIGS. A first multi-cavity wiring board that obtains a plurality of relay boards in which the formed lands and connection terminals are surely conducted through via conductors (not shown) penetrating the insulating layer s1. Can do.

Further, as shown on the right side of FIG. 11, the mark A on the back surface 5 is formed on the lower surface side of the insulating layer s1 in which the mark (third mark) A and the mark (fifth mark) B are formed on the front and back surfaces 2 and 3. The insulating layer s2 on which the mark (fourth mark) C having an intermediate length with the mark B is formed may be laminated and fired to form the second and third multi-cavity wiring boards K similar to the above. The marks A to C are formed so as to be exposed also on the side surface of the wiring board K.
Even in such a multi-cavity wiring board K, the overlap between the mark A formed on the front surface 2 of the insulating layer s1 and the mark C formed on the back surface 5 of the insulating layer s2 is in an appropriate equally divided state shown in FIG. From the above, if there is a range up to the maximum stacking deviation amount (z2) of the insulating layers s1 and s2 shown in FIG. 9, whether there is no printing misalignment and stacking misalignment, or both of these are within the allowable range. Easy to judge. Note that the stacking deviation between the insulating layers s1 and s2 may be inspected according to the overlapping degree of the marks B and C.

FIG. 12 shows a multi-piece wiring board K1 and the like of still another form of the first to third wiring boards K.
As shown on the left side of FIG. 12, a mark (second mark) C is formed on the front surface 4 of the insulating layer s2, and a mark (first mark) A longer than the mark C is formed on the back surface 3, along the longitudinal direction of both. The difference between the lengths dA and dC is set to twice the maximum printing misalignment amount z2 in the same manner as the above formula 2. The marks A and C are also formed so as to be exposed also on the side surface of the insulating layer s2.
The degree of overlap between the marks A and C in a plan view is printed on the front and back surfaces 4 and 5 of the insulating layer s2 so that there is no printing misalignment or within an allowable range, as in FIGS. A first multi-cavity wiring board having a plurality of relay boards in which the formed lands and connection terminals are surely conducted via via conductors (not shown) penetrating the insulating layer s2. Can do.

Further, as shown on the right side of FIG. 12, the mark C on the surface 2 is formed on the upper layer side of the insulating layer s2 in which the mark (fifth mark) C and the mark (third mark) A are formed on the front and back surfaces 4 and 5. The insulating layer s1 in which the shorter shortest mark (fourth mark) B is formed may be laminated and fired to form the second and third multi-cavity wiring boards K1 similar to the above. That is, the mark (fifth mark) C is shorter than the mark (third mark) A and longer than the mark (fourth mark) B. The marks A to C are formed so as to be exposed also on the side surface of the wiring board K1.
The wiring board K in FIGS. 1 and 2 is different from the wiring board K1 in which the marks A to C are arranged in the thickness direction, and the mark B formed on the surface 2 of the insulating layer s1 and the insulating layer s2 If the overlap with the mark C formed on the front surface 4 is within the range from the proper equally arranged state shown in FIG. 12 to the maximum stacking misalignment amount (z1) between the insulating layers s1 and s2, the printing misalignment occurs. It can be easily determined whether there is no stacking deviation or both are within the allowable range. Note that the stacking deviation between the insulating layers s1 and s2 may be inspected according to the overlapping degree of the marks A and C.

FIG. 13 shows a multi-piece wiring board K2 having different forms of the first to third wiring boards K.
As shown on the left side of FIG. 13, a mark (first mark) A is formed on the front surface 4 of the insulating layer s2, and a mark (second mark) C shorter than the mark A is formed on the back surface 3, along the longitudinal direction of both. The difference between the lengths dA and dC is set to twice the maximum printing misalignment amount z2 in the same manner as the above formula 2. The marks A and C are also formed so as to be exposed also on the side surface of the insulating layer s2.
The degree of overlap between the marks A and C in a plan view is printed on the front and back surfaces 4 and 5 of the insulating layer s2 so that there is no printing misalignment or within an allowable range, as in FIGS. A first multi-cavity wiring board having a plurality of relay boards in which the formed lands and connection terminals are surely conducted via via conductors (not shown) penetrating the insulating layer s2. Can do.

Further, as shown on the right side of FIG. 13, the mark C on the front surface 2 is formed on the upper layer side of the insulating layer s2 in which the mark (fifth mark) A and the mark (third mark) C are formed on the front and back surfaces 4 and 5. The second and third multi-cavity wiring boards K2 may be formed by laminating and firing the insulating layer s1 on which the shorter shortest mark (fourth mark) B is formed. That is, the mark (fifth mark) A is longer than the mark (third mark) C and the mark (fourth mark) B. The marks A to C are formed so as to be exposed also on the side surface of the wiring board K2.
Even with the multi-piece wiring board K2 as described above, the overlap between the mark B formed on the surface 2 of the insulating layer s1 and the mark C formed on the surface 4 of the insulating layer s2 is appropriate as shown in FIG. If it is within the range from the partial arrangement state to the maximum stacking misalignment amount (z1) between the insulating layers s1 and s2, it is easy to determine whether there is no printing misalignment and misalignment or both are within the allowable range. Can be determined. Note that the stacking deviation between the insulating layers s1 and s2 may be inspected according to the overlapping degree of the marks A and B.

FIG. 14 is a plan view of a multi-cavity wiring board K3 which is an applied form of the wiring board K. FIG. As shown in FIG. 14, the wiring board K3 has a total of nine wirings in the insulating laminate S composed of the insulating layers s1 and s2, each having three vertical and horizontal sections separated by the predetermined cutting line c indicated by a broken line. A total of four product areas a each consisting of the substrate 1 and the ears m surrounding the substrate 1 are provided in both vertical and horizontal directions. The four product areas a are cut along the planned cutting line c1 indicated by the thick broken line in FIG.
As shown in FIG. 14, in the vicinity of the center of the long side and the short side exposed on the outer surface of each product area a, as in the case of the wiring board K, a mark (third mark) A and a mark (not shown) 4, fifth mark) B and C are within a range in which the maximum printing shift and the maximum stacking shift of FIG. 5 and FIG. 9 are allowable from the proper arrangement without the printing shift and the stacking shift of FIG. Is formed between.

Moreover, in the ear | edge part m between adjacent product areas a and a, the planar view is nearly square (rectangular) near the center of the planned cutting line c1 passing through the middle across the planned cutting line c1. A similar mark (third mark) A and unillustrated marks (fourth and fifth marks) B and C are formed in the same overlapping range as described above.
According to the multi-cavity wiring board K3 as described above, the presence or absence of printing misalignment between the front surface 4 and the rear surface 5 of the insulating layer s2 due to the marks (fourth and fifth marks) B and C exposed on the outer surface. In addition, the presence or absence of misalignment between the insulating layers s1 and s2 and the acceptance or non-existence can be determined by the degree of overlap between the mark A formed on the front surface 2 of the insulating layer s1 and the mark C formed on the back surface 5 of the insulating layer s2. Can be determined. Further, whether or not there is the same printing misalignment and stacking misalignment as well as the pass / fail due to the marks A to C exposed on the cut surface (side surface) for each product area a obtained by cutting along the planned cutting line c1. Can be easily determined.
The arrangement of the marks A to C on the multi-cavity wiring board K3 may be in the form shown on the right side of FIGS.

The multi-cavity wiring boards K, K1 to K3 may be configured as an insulating laminate S in which three or more insulating layers are laminated.
Further, the marks A to C may be formed in one set or two or more sets at arbitrary positions on the outer surface of the multi-cavity wiring boards K and K1 to K3.
Furthermore, the mark may be applied to a multi-piece wiring board composed of a plurality of insulating layers of four or more different lengths in the longitudinal direction.
In addition, the insulating layer is made of, for example, a core substrate made of a BT resin, a resin film or a resin layer, and a multi-piece wiring substrate made by laminating them, and the mark A ˜C can be formed by Cu plating as well as the internal wiring pattern, via conductor, land, and connection terminal.

The top view which shows one form of the wiring board for the 2nd and 3rd multiple picking by this invention. The perspective view which shows the wiring board for multi-piece taking of FIG. FIG. 2 is a partial side view of the multi-cavity wiring board of FIG. 1. Schematic which shows the 1st multi-cavity wiring board in this invention. Schematic which shows the wiring board for multi-pieces from which the position of a mark differs from the above. Schematic which shows the wiring board for multi-piece picking from which the position of the mark differs further from the above. Schematic which shows the 2nd, 3rd multi-cavity wiring board by this invention. Schematic which shows the wiring board for multi-cavity of FIG. Schematic which shows the wiring board for multi-pieces from which the position of a mark differs from the above. Schematic which shows the wiring board for multi-piece picking from which the position of a mark differs further. Schematic which shows the wiring board for multi-piece taking from which arrangement | positioning of a mark differs. Schematic which shows the wiring board for multi-piece taking from which arrangement | positioning of a mark differs further. Schematic which shows the wiring board for multi-piece picking from which arrangement | positioning of a mark differs. The top view which shows the application form of the said multi-cavity wiring board.

Explanation of symbols

A ……………… Mark (1st mark / 3rd mark / 5th mark)
B ………………… Mark (2nd mark / 4th mark / 5th mark)
C …………… Mark (1st mark / 3rd mark / 4th mark / 5th mark)
K, K1 to K3 ... Multi-use wiring board s1, s2 ... Insulating layer 2, 4 ... ... Front surface 3, 5 ... ... Back side dA to dC ... ... Length n ... ………… Center line

Claims (4)

On the front surface and the back surface of the insulating layer, either one of the first mark and the second mark having a rectangular shape in plan view is formed,
The length of the first mark and the second mark exposed on the side surface of the multi-cavity wiring board is such that the first mark is longer than the second mark,
The first mark and the second mark overlap each other in the thickness direction of the multi-cavity wiring board,
A wiring board for multi-piece production characterized by the above. On the front and back surfaces of two insulating layers adjacent to each other on the upper and lower sides of a multi-piece wiring board formed by laminating a plurality of insulating layers, either one of a third mark and a fourth mark that are rectangular in a plan view is provided. Formed,
The length exposed on the side surface of the multi-cavity wiring board is such that the third mark is longer than the fourth mark,
The third mark and the fourth mark overlap each other in the thickness direction of the multi-cavity wiring board,
A wiring board for multi-piece production characterized by the above. A fifth mark having a rectangular shape in plan view is formed on the front or back surface of the insulating layer located between the third mark and the fourth mark,
The length of the fifth mark exposed on the side surface of the multi-cavity wiring board is shorter than the third mark and longer than the fourth mark, or shorter than the third mark and the fourth mark, or , Longer than the third and fourth marks,
The multi-cavity wiring board according to claim 2, wherein: The overlap between the first mark and the second mark, the overlap between the third mark and the fourth mark, or the overlap between the third mark or the fourth mark and the fifth mark is the width direction of the rectangle of each mark. In the range from the form in which the center lines along the line coincide with each other in a plan view, the form in which the short sides of the same end in the longitudinal direction of the rectangle of each mark coincide in the thickness direction of the insulating layer,
The multi-cavity wiring board according to any one of claims 1 to 3, wherein:

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