JP4304056B2 - Level shift circuit - Google Patents

Description

  The present invention relates to a level shift circuit used for an interface between two circuits having different power supply voltages.

  With the recent miniaturization of the process, the power supply voltage of the internal circuit of the semiconductor integrated circuit tends to be lowered due to the problem of device reliability. On the other hand, some elements used in systems such as electronic devices inherit the conventional power supply voltage. In order to provide an interface between these elements having different power supply voltages and the semiconductor integrated circuit, a level shift circuit is generally incorporated in the semiconductor integrated circuit.

  Recently, in order to reduce power consumption among semiconductor integrated circuits, an optimum power supply voltage is supplied to each circuit block. An interface between circuit blocks having different power supply voltages is provided. For this purpose, a level shift circuit is used. In the future, the importance of this level shift circuit is expected to increase further.

  A conventional level shift circuit is described in Patent Document 1, for example. An example of such a conventional level shift circuit is shown in FIG. In the figure, 1, 2 are N-type transistors, 3, 4 are P-type transistors, VDD is a high voltage power supply, VSS is a ground power supply, IN is an input signal, XIN is an inverted input signal, OUT is an output signal, and XOUT is inverted. Output signal. The input signal IN and the inverted input signal XIN are respectively input to the gate electrodes of the N-type transistors 1 and 2, and their source electrodes are connected to the ground power supply VSS. The drain electrodes of the P-type transistors 3 and 4 are connected to the drain electrodes of the N-type transistors 1 and 2, and their source electrodes are connected to the high voltage power supply VDD. The two P-type transistors 3 and 4 have a cross-couple connection in which one gate electrode is connected to the other drain electrode. The inverted output signal XOUT is output from the connection point between the P-type transistor 3 and the N-type transistor 1, and the output signal OUT is output from the connection point between the P-type transistor 4 and the N-type transistor 2.

  Next, the operation of the conventional level shift circuit will be described. As an example, the amplitude level of the input signal IN and the inverted input signal XIN is 1.5V, the power supply potential of the high voltage power supply VDD is 3V, the potential of the ground power supply VSS is 0V, and the amplitude levels of the output signal OUT and the inverted output signal XOUT are 3V. The operation will be described as follows.

  First, as an initial state, it is assumed that the input signal IN is 0V, the inverted input signal XIN is 1.5V, the output signal OUT is 0V, and the inverted output signal XOUT is 3V. At this time, the N-type transistor 1 and the P-type transistor 4 are non-conductive, and the N-type transistor 2 and the P-type transistor 3 are conductive.

  Next, consider a case where the input signal IN changes to 1.5V and the inverted input signal XIN changes to 0V. Due to this change, the N-type transistor 1 changes to a conductive state, and the N-type transistor 2 changes to a non-conductive state. At this time, since the P-type transistor 3 is in a conductive state, the potential of the inverted output signal XOUT decreases to an intermediate value determined by the ratio of the conductive resistance values of the N-type transistor 1 and the P-type transistor 3. When this intermediate value exceeds the threshold voltage of the P-type transistor 4, the P-type transistor 4 transitions to a conductive state and raises the potential of the output signal OUT. When the potential of the output signal OUT rises, the P-type transistor 3 transitions to a non-conduction state, so that the conduction resistance value of the P-type transistor 3 rises and the potential of the inverted output signal XOUT further decreases.

By applying the positive feedback as described above, the output signal OUT changes to 3V and the inverted output signal XOUT changes to 0V, and the operation of shifting the low amplitude level input signal to the large amplitude level output signal is completed. . Therefore, for example, a signal having a low power supply voltage level inside the semiconductor integrated circuit can be shifted to a signal having a high external power supply voltage level.
JP-A-6-209256

  However, in the conventional level shift circuit, it has been found that the problem described below becomes remarkable as the power supply voltage is lowered. That is, in the level shift circuit shown in FIG. 15, the N-type transistors 1 and 2 are high breakdown voltage transistors having a thick gate oxide film so that they can withstand a high voltage. Has a large threshold voltage (for example, 0.5 V). For this reason, when the voltage level (power supply voltage level) of the input signal IN and the inverted input signal XIN decreases to near the threshold voltage of the N-type transistors 1 and 2 (for example, 0.7 V), these signals IN and XIN are gated. The capabilities of the N-type transistors 1 and 2 received by the electrodes are abruptly reduced. As a result, when these signals IN and XIN change from 0V to a predetermined voltage level (0.7V), the operations of the N-type transistors 1 and 2 on the side that transitions to the conductive state are slow, and the level shift circuit operates as a whole. There is a problem that the speed is degraded.

  As described above, since the power supply voltage inside the semiconductor integrated circuit tends to be lowered due to the progress of miniaturization in recent years, if the lowering of the voltage level further progresses, the signal of the lower voltage level is increased in speed. Therefore, it is an important issue whether to shift to a high voltage level signal.

  The present invention solves the above-mentioned conventional problems, and an object of the present invention is to reduce the input signal voltage level in a level shift circuit that shifts an input signal having a low voltage level to an output signal having a high voltage level. However, the level shift of the signal can be performed at high speed, preferably with low power consumption.

  In order to achieve the above object, the present invention focuses on a current mirror circuit that amplifies a current, and a current flowing through the transistor is amplified by a predetermined factor by the current mirror circuit in a transistor in which an input signal is input to a gate electrode. By doing so, the operation speed is increased. Furthermore, in the present invention, when the current mirror circuit is employed as described above, a countermeasure is taken so that a reduction in current consumption is not hindered by a steady current flowing through the current mirror circuit.

  Specifically, the level shift circuit according to claim 1 has a pair of input terminals and an inverting input terminal, and a pair of output nodes and an inverting output node, and an input signal and an inversion are input to the input terminal and the inverting input terminal. An input signal is input, the amplitude level of the input signal and the inverted input signal is shifted to an amplitude level larger than the amplitude level, an output signal having the amplitude level after the shift, and an inverted output signal obtained by inverting the output signal Is transmitted to the output node and the inverting output node, the signal input first N-type transistor having the input terminal connected to the gate electrode, and the inverting input terminal connected to the gate electrode. A second N-type transistor for signal input, a P-type current mirror circuit constituted by a P-type transistor, and an N-type transistor. It has at least one set in which N-type current mirror circuits are cascade-connected, and is arranged between the first N-type transistor and the inverted output node to multiply the current flowing through the first N-type transistor by a predetermined factor. A first current mirror circuit that amplifies and extracts the amplified current from the inverting output node, a P-type current mirror circuit configured by a P-type transistor, and an N-type current mirror circuit configured by an N-type transistor There is at least one cascade-connected group, which is disposed between the second N-type transistor and the output node, amplifies the current flowing through the second N-type transistor by a predetermined factor, and the amplified current is A second current mirror circuit extracted from the output node and connected in parallel to the first N-type transistor, the first current mirror A first N-type transistor for current feedback controlled by a potential at a connection point between a P-type current mirror circuit and an N-type current mirror circuit in the circuit, and the second N-type transistor connected in parallel; And a second N-type transistor for current feedback controlled by a potential at a connection point between the P-type current mirror circuit and the N-type current mirror circuit in the second current mirror circuit.

  According to a second aspect of the present invention, in the level shift circuit according to the first aspect, a gate electrode is connected to the inverting input terminal, and a drain electrode is connected to the P-type current mirror circuit and the N-type in the first current mirror circuit. A third N-type transistor connected to a connection point with the current mirror circuit, a source electrode grounded, a gate electrode connected to the input terminal, and a drain electrode connected to the P-type current in the second current mirror circuit And a fourth N-type transistor connected to a connection point between the mirror circuit and the N-type current mirror circuit and having a source electrode grounded.

  The invention according to claim 3 is the level shift circuit according to claim 1 or 2, wherein the level shift circuit is connected to the first current mirror circuit, and the first current mirror circuit flows after the change of the output signal is finished. A first current cut-off circuit that cuts off a current, and a second current that is connected to the second current mirror circuit and cuts off a current flowing through the second current mirror circuit after the change of the inverted output signal is completed. And a cutoff circuit.

  According to a fourth aspect of the present invention, in the level shift circuit according to the third aspect, the first current cutoff circuit includes a P-type transistor that receives the output signal at a gate electrode, and the second current cutoff circuit. Is configured by a P-type transistor that receives the inverted output signal at its gate electrode.

  The invention according to claim 5 is the level shift circuit according to claim 3 or 4, wherein the level shift circuit is connected in parallel to the P-type current mirror circuit of the first current mirror circuit, and is controlled by the inverted output signal of the inverted output node. And connected in parallel to a first change speed acceleration circuit for increasing the speed at which the inverted output signal changes from L level to H level and a P-type current mirror circuit of the second current mirror circuit, And a second change speed acceleration circuit that increases the speed at which the output signal changes from the L level to the H level.

  According to a sixth aspect of the present invention, in the level shift circuit according to the fifth aspect, the first change speed acceleration circuit is connected in parallel to a P-type current mirror circuit of the first current mirror circuit. And a first buffer circuit whose output side is connected to the gate electrode of the first P-type transistor and is controlled by an inverted output signal of the inverted output node, and the second change rate acceleration The circuit includes a second P-type transistor connected in parallel to the P-type current mirror circuit of the second current mirror circuit, an output side connected to the gate electrode of the second P-type transistor, and the output node And a second buffer circuit controlled by an output signal.

  According to a seventh aspect of the present invention, in the level shift circuit according to the sixth aspect of the present invention, the first change rate acceleration circuit further includes the first buffer circuit after the change of the output signal of the output node is completed. A second control circuit for permitting the operation; and the second change speed promoting circuit further allows the operation of the second buffer circuit after the change of the inverted output signal of the inverted output node is completed. It is characterized by comprising two control circuits.

  According to an eighth aspect of the present invention, in the level shift circuit according to the first, second, third, fourth, sixth, or seventh aspect, the output node and the inverted output node in an initial state where power is supplied. It is characterized in that a stabilization circuit is provided for establishing and stabilizing the potential state at an early stage.

  The invention according to claim 9 is the level shift circuit according to claim 8, wherein the stabilization circuit includes a gate electrode connected to the output node, a drain electrode connected to the inverted output node, and a source electrode grounded. And a second N-type transistor having a gate electrode connected to the inverted output node, a drain electrode connected to the output node, and a source electrode grounded. To do.

  According to a tenth aspect of the present invention, in the level shift circuit according to the first, second, third, fourth, fifth, sixth, seventh, eighth, or ninth aspect, the output signal of the output node and the inverted output signal of the inverted output node At least one of the signals is output externally.

  As described above, in the first to tenth aspects of the present invention, for example, when the input signal at the input terminal changes from the L level to the H level, the first N-type transistor becomes conductive, and current flows through the transistor. This current is amplified by a predetermined factor by the first current mirror circuit. Further, the first N-type transistor for current feedback forms another current mirror circuit together with the N-type transistor constituting the N-type current mirror circuit of the first current mirror circuit. The amplified current is amplified, and the amplified current is re-amplified by the first current mirror circuit, and the amplified current is extracted from the inverting output node. Therefore, the current driving capability for the inverting output node is remarkably improved, the change of the inverting output node to the L level and the change of the output node to the H level are accelerated, and the operation speed of the level shift circuit is improved.

  In particular, in the invention according to claim 2, for example, in a state where the input signal of the input terminal is at the L level, no current flows through the first current mirror circuit, but when the leakage current is large, The current mirror circuit including the first N-type transistor for current feedback amplifies the leakage current and tries to erroneously set the inverting input signal of the inverting input terminal to the L level. Such a malfunction is prevented because the leakage current is drawn to the ground.

  In the third and fourth aspects of the invention, as described above, after the first current mirror circuit amplifies the current by a predetermined factor, the first current mirror circuit is An attempt is made to constantly flow a predetermined amount of amplified current, but when the change of the output signal of the output node to the H level is completed, the first current cut-off circuit operates and the first current mirror circuit is flowing. Since the amplified current is cut off, low power consumption can be effectively achieved.

  In the fifth, sixth and seventh aspects of the invention, for example, when the output signal changes from L level to H level at the output node, the second change speed promoting circuit changes the output signal to H level. Since the speed is promoted, the operation speed can be further improved.

  In addition, in the inventions according to claims 8 and 9, in the initial state where the power supply is started, the input signal and the inverting input signal of the input terminal and the inverting input terminal are in an indefinite state where they are not at a predetermined L or H level. Even in this case, the stabilization circuit operates and the potentials of the output node and the inverted output node are settled to the L or H level at an early stage to be stabilized, so that the transient current flowing until reaching the stable state is effectively reduced. Will do.

  As described above, according to the level shift circuit of the first to tenth aspects of the present invention, the currents flowing through the first and second N-type transistors for taking in the input signal and the inverted input signal are respectively current mirrors. Since the current driving capability is increased by amplifying the circuit by a predetermined factor, the level change of the output signal and the inverted output signal can be increased, and the operation speed of the level shift circuit can be improved.

  In particular, according to the second aspect of the invention, due to the presence of the current mirror circuit including the N-type transistor for current feedback, the current mirror circuit amplifies the leakage current, and the output that should originally be at the H level. Even in a situation where the level of the terminal or the inverted output terminal is set to L level, such an erroneous operation is prevented because the N-type transistor for extracting the leakage current to the ground is arranged.

  Further, according to the third and fourth aspects of the present invention, after the level change of the output signal and the inverted output signal is finished, the predetermined current flowing through the current mirror circuit is forcibly cut off by the current cut-off circuit. It is possible to achieve low power consumption.

  According to the fifth, sixth and seventh aspects of the invention, when the output signal and the inverted output signal change from the L level to the H level, the change rate to the H level is accelerated by the first and second change rates. Since it is promoted by the circuit, it is possible to further improve the operation speed.

  In addition, according to the inventions of claims 8 and 9, even when the input signal and the inverted input signal are in an indefinite state that is not at a predetermined L or H level in an initial state in which power is started to be supplied, Since the potentials of the output signal and the inverted output signal are fixed to the L or H level at an early stage by the stabilization circuit and stabilized, the transient current flowing until reaching the stable state can be effectively reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 shows a level shift circuit according to a first embodiment of the present invention. In the figure, VDD is a high voltage power supply, VSS is a ground power supply, IN is an input terminal, XIN is an inverting input terminal, O is an output node, XO is an inverting output node, OUT is an output terminal connected to the output node O, XOUT is an inverting output terminal connected to the inverting output node XO. The pair of output terminals OUT and the inverted output terminal XOUT do not always need to have one pair, and only one terminal OUT or XOUT may be provided as necessary.

  Reference numeral 1 denotes a first N-type transistor for signal input, and an input signal of the input terminal IN (hereinafter, the same symbol IN as the input terminal IN is used) is input to the gate electrode thereof. . Reference numeral 2 denotes a second N-type transistor for signal input, and an inverted input signal of the inverted input terminal XIN (hereinafter, the same symbol XIN as the inverted input terminal XIN is used) is input to the gate electrode. The The source electrodes of both transistors 1 and 2 are connected to the ground power supply VSS.

  Reference numerals 3 and 4 denote first and second P-type transistors having a source electrode connected to the high-voltage power supply VDD. Between the two P-type transistors 3 and 4, one of the P-type transistors is connected. The gate electrode is a cross-coupled connection connected to the drain electrode of the other P-type transistor. The drain electrode of the first P-type transistor 3 is the inverted output node XO, and the drain electrode of the second P-type transistor 4 is the output node O.

  As a feature of the present invention, there is a first gap between the drain electrode of the first N-type transistor 1 for signal input and the inverted output node XO (that is, the drain electrode of the first P-type transistor 3). One current mirror circuit 10 is arranged. Similarly, a second current mirror circuit 11 is provided between the drain electrode of the second N-type transistor 2 for signal input and the output node O (that is, the drain electrode of the second P-type transistor 4). Be placed.

In the first current mirror circuit 10, a P-type current mirror circuit 10P having two P-type transistors 5a and 5b and an N-type current mirror circuit 10N having two N-type transistors 6a and 6b are connected in cascade. Made up. In the P-type current mirror circuit 10P, the source electrodes of the two P-type transistors 5a and 5b are connected to the high-voltage power supply VDD, and both gate electrodes are connected to each other. The drain electrode is connected to the drain electrode of the first N-type transistor 1 for signal input. In this P-type current mirror circuit 10P, the gate width of one P-type transistor 5a is W1, the gate length is L1, the flowing current is i1, the gate width of the other P-type transistor 5b is W2, and the gate length is L2. If the current is i2, the current i2 flowing through the other P-type transistor 5b is
i2 = i1 * (W2 / L2) / (W1 / L1)
In other words, the current i2 is a predetermined multiple α (= (W2 / L2) / (W1 / L1)) of the current i1. For example, when L1 = L2 = 0.4 μm, W1 = 1 μm, and W2 = 10 μm, the current i2 flowing through the other P-type transistor 5b is 10 times the current i1 flowing through one P-type transistor 5a. This current is output from the drain electrode of the other P-type transistor 5b.

  On the other hand, in the N-type current mirror circuit 10N of the first current mirror circuit 10, the source electrodes of the two N-type transistors 6a and 6b are connected to the ground power supply VSS and both gate electrodes are connected to each other. Further, the drain electrode of one N-type transistor 6a is connected to the drain electrode of the other P-type transistor 5b of the P-type current mirror circuit 10P. This N-type current mirror circuit 10N also flows to the other N-type transistor 6b according to the settings of the gate widths W1 and W2 and the gate lengths L1 and L2 of the one and other N-type transistors 6a and 6b, as described above. The current i2 is a predetermined multiple β (= (W2 / L2) / (W1 / L1)) of the current i1 flowing through one N-type transistor 6a based on the previous equation.

  Similarly, the second current mirror circuit 11 includes a P-type current mirror circuit 11P having two P-type transistors 7a and 7b, and an N-type current mirror circuit 11N having two N-type transistors 8a and 8b. Are connected in cascade. The internal configurations of these P-type and N-type current mirror circuits 11P and 11N are the same as those of the P-type and N-type current mirror circuits 10P and 10N of the first current mirror circuit 10, and thus the description thereof is omitted. To do.

  Further, as a feature of the present invention, a first N-type transistor 60 for current feedback is connected in parallel to the first N-type transistor 1 for signal input. The first N-type transistor 60 for current feedback has a connection point between the P-type current mirror circuit 10P of the first current mirror circuit 10 and the N-type current mirror circuit 10N of the first current mirror circuit 10. Controlled by potential. Similarly, a second N-type transistor 80 for current feedback is connected in parallel to the second N-type transistor 2 for signal input. The second N-type transistor 80 for current feedback has a connection point between the P-type current mirror circuit 11P of the second current mirror circuit 11 and the N-type current mirror circuit 11N of the second current mirror circuit 11. Controlled by potential.

  Further, the first N-type transistor 60 for current feedback constitutes a third current mirror circuit 65 together with the N-type transistor 6a in the N-type current mirror circuit 10N of the first current mirror circuit 10, The current amplified by the P-type current mirror circuit 10P of the first current mirror circuit 10 is fed back to the P-type current mirror circuit 10P of the first current mirror circuit 10 again, and the current amplification is repeatedly executed. To do. Similarly, the second N-type transistor 80 for current feedback constitutes a fourth current mirror circuit 85 together with the N-type transistor 8a in the N-type current mirror circuit 11N of the second current mirror circuit 11, The current amplified by the P-type current mirror circuit 11P of the second current mirror circuit 11 is again fed back to the P-type current mirror circuit 11P of the second current mirror circuit 11, and the current amplification is repeatedly executed. do.

  Further, in the present embodiment, a third N-type transistor 61 and a fourth N-type transistor 81 are arranged. In the third N-type transistor 61, the gate electrode is connected to the inverting input terminal XIN, the source electrode is grounded, and the drain electrode is the gate electrode of the first N-type transistor 60 for current feedback, in other words. Are connected to a connection point between the P-type current mirror circuit 10P and the N-type current mirror circuit 10N in the first current mirror circuit 10. In the fourth N-type transistor 81, the gate electrode is connected to the input terminal IN, the source electrode is grounded, and the drain electrode is the gate electrode of the second N-type transistor 80 for current feedback. For example, the second current mirror circuit 11 is connected to the connection point between the P-type current mirror circuit 11P and the N-type current mirror circuit 11N.

  When the leakage current of the first and second current mirror circuits 10 and 11 is large, the third and fourth N-type transistors 61 and 81 suppress malfunction caused by the leakage current. For example, a description will be given using a state where the input signal IN is 0V and the inverted input signal XIN is 1.5V. In this state, no current flows through the first current mirror circuit 10, but when the leakage current of the P-type transistor 5 b in the P-type current mirror circuit 10 P is large, the third N-type transistor 61. If there is not, the third current mirror circuit 65 composed of the N-type transistor 6a in the N-type current mirror circuit 10N and the first N-type transistor 60 for current feedback amplifies this leakage current. As a result, a current flows through the first current mirror circuit 10 and the operation is not performed correctly. However, since the third N-type transistor 61 draws the leakage current to the ground, no malfunction occurs.

  Next, the operation of the level shift circuit of this embodiment will be described. As an example, the amplitude level of the input signal IN and the inverted input signal XIN is 0.7V, the power supply potential of the high voltage power supply VDD is 3V, the potential of the ground power supply VSS is 0V, and the amplitude levels of the output signal O and the inverted output signal XO are 3V. As such, the operation will be described.

  First, as an initial state, it is assumed that the input signal IN is 0V, the inverted input signal XIN is 0.7V, the output signal O is 0V, and the inverted output signal XO is 3V. At this time, the first N-type transistor 1 for signal input, the fourth N-type transistor 81, and the second P-type transistor 4 are non-conductive. On the other hand, the second N-type transistor 2 for signal input, the third N-type transistor 61, and the first P-type transistor 3 are in a conductive state. Even if a leak current is generated in the P-type transistor 5b in the P-type current mirror circuit 10P, the third N-type transistor 61 is in a conductive state, so that the leak current is passed through the third N-type transistor 61. Flows and no malfunction occurs.

  Next, consider a case where the input signal IN changes to 0.7V and the inverted input signal XIN changes to 0V. Due to this potential change, the first N-type transistor 1 for signal input and the fourth N-type transistor 81 are made conductive, and the second N-type transistor 2 for signal input and the third N-type transistor 61 are non-conductive. Each transitions to a conductive state. At this time, a current flows through the first N-type transistor 1 for signal input, and this current is multiplied by a predetermined factor α (= (W2 / L2) / () by the P-type current mirror circuit 10P of the first current mirror circuit 10. It is amplified to W1 / L1))). This amplified current is further amplified by a predetermined factor β (= (W2 / L2) / (W1 / L1))) by the N-type current mirror circuit 10N because the P-type transistor 3 is in a conductive state, and the total predetermined Amplified current multiplied by α × β is drawn from the inverted output node XO to the ground through the other N-type transistor 6b of the N-type current mirror circuit 10N. Further, the first N-type transistor 60 for current feedback and the N-type transistor 6a in the N-type current mirror circuit 10N also constitute a third current mirror circuit 65. For example, the current mirror circuit 65 also supplies current. When amplified to a predetermined factor β (= (W2 / L2) / (W1 / L1))), this amplified current is amplified again by the first current mirror circuit 10. As described above, the current drawn from the output node XO becomes extremely large in a short time. Therefore, when the voltage of the input signal IN is as low as 0.7 V, the current driving capability of the first N-type transistor 1 for signal input is reduced, and the current flowing through the transistor 1 is very small. Thus, the drive current for the inverting output node XO can be increased to speed up the potential change of the inverting output node XO from the H level to the L level.

  Then, due to the large driving current from the inverting output node XO, the potential of the inverting output node XO is the ratio of the conduction resistance value between the N-type transistor 6b of the N-type current mirror circuit 10N and the first P-type transistor 3. When the time until the intermediate value exceeds the threshold voltage of the second P-type transistor 4 is shortened, the second P-type transistor 4 is brought into a conductive state at an early stage. As the transition proceeds, the potential rise of the output node O also becomes faster. As the potential of the output node O rises, the first P-type transistor 3 quickly transitions to a non-conducting state, so that the conduction resistance value of the first P-type transistor 3 also rises quickly, and the inverted output node XO The potential will drop more quickly. By applying the positive feedback as described above, the potential of the inverting output node XO changes to 0V, the potential of the output node O changes to 3V, and the low amplitude level (0.7V) input signals IN and XIN are changed to the large amplitude level. The operation of shifting to (3V) output signal O and inverted output signal XO is completed.

  The above description has been made by taking as an example the rising change time of the input signal IN. However, the description of the rising change time of the inverting input signal XIN is also the same as described above, and the description thereof is omitted.

  Therefore, in the level shift circuit of this embodiment, even if the voltage of the input signal IN and the inverted input signal XIN is lowered, the current mirror circuits 10 and 11 and the N-type transistors 60 and 80 for current feedback are used. Since the current drive capability with respect to the output node O and the inverted output node XO is increased, the change speed of the output signal O and the inverted output signal XO can be increased to ensure high-speed operation.

  In this embodiment, the output terminal OUT and the inverted output terminal XOUT are connected to the output node O and the inverted output node XO, respectively, and both the output signal O and the inverted output signal XO are externally output. The present invention is not limited to this, and it is of course possible to adopt a configuration in which only one of the output signal O and the inverted output signal XO is externally output.

  In the present embodiment, each of the first and second current mirror circuits 10 and 11 is configured as one set including one P-type current mirror circuit and one N-type current mirror circuit. Of course, it may be provided.

(Second Embodiment)
FIG. 3 shows a level shift circuit according to a second embodiment of the present invention.

  The level shift circuit shown in the figure is an improvement of the level shift circuit of the first embodiment, and reduces the current that constantly flows through the first and second current mirror circuits 10 and 11. It is a thing.

  That is, in the level shift circuit of FIG. 3, two P-type transistors 15 and 16 are further added to the configuration of the level shift circuit of the first embodiment. The one P-type transistor 15 has a source electrode connected to the high voltage power supply VDD, a drain electrode connected to the P-type current mirror circuit 10P of the first current mirror circuit 10, and a gate electrode connected to the output node O. The output signal O is received. Similarly, the other P-type transistor 16 has a source electrode connected to the high voltage power supply VDD, a drain electrode connected to the P-type current mirror circuit 11P of the second current mirror circuit 11, and a gate electrode connected to the inverted output node XO. To receive an inverted output signal XO.

  The one P-type transistor 15 becomes non-conductive at the end of the change of the potential of the output node O from the L level to the H level, and at the time of non-conduction, the high-voltage power supply VDD and the P-type of the first current mirror circuit 10 It functions as a first current cut-off circuit that cuts off the current path between the current mirror circuit 10P and cuts off the current flowing through the first current mirror circuit 10. Similarly, the other P-type transistor 16 becomes non-conductive at the end of the change of the potential of the inverted output node XO from the L level to the H level, and at this non-conductive time, the high voltage power supply VDD and the second current mirror circuit 11 are turned off. The P-type current mirror circuit 11P functions as a second current cut-off circuit that cuts off the current path between the P-type current mirror circuit 11P and cuts off the current flowing through the second current mirror circuit 11.

  Next, the operation of the present embodiment will be described. First, the basic operation will be described with reference to FIG. 2 that does not have the two characteristic P-type transistors 15 and 16 in the present embodiment.

  In FIG. 2, for example, consider a case where the input signal IN is at H level and the inverted input signal XIN is at L level. In this case, the output node O is at the H level, the inverted output node XO is at the L level, the first P-type transistor 3 is in a non-conductive state, and the second P-type transistor 4 is in a conductive state. Since the input signal IN is at the H level, the first N-type transistor 1 for signal input becomes conductive, and the first current mirror circuit 10 receives the signal from one P-type transistor 5a of the P-type current mirror circuit 10P. A current flows through the first N-type transistor 1 for input as shown by a thin line arrow in the figure, and an amplified current flows from the other P-type transistor 5b to one N-type transistor 6a of the N-type current mirror circuit 10N. Flows as indicated by the bold arrows. Since the first P-type transistor 3 is in a non-conductive state, no amplified current flows through the other N-type transistor 6b in the N-type current mirror circuit 10N. On the other hand, the second current mirror circuit 11 does not operate and the amplified current does not flow because the inverted input signal XIN is at the L level and the second N-type transistor 2 for signal input is in a non-conductive state. . Therefore, in the level shift circuit of FIG. 2, the P-type current mirror circuit 10P of the first current mirror circuit 10 causes a steady current to flow unnecessarily during the steady state when the input signal IN is at the H level.

  On the other hand, in the level shift circuit shown in FIG. This will be described in detail below. The case where the input signal IN is at the H level as in the example described above will be described as an example. As shown in FIG. 4, first, when the input signal IN is at the L level before changing to the H level, the output node O is at the L level and the inverted output node XO is at the H level. One P-type transistor 3 is in a conductive state, and the second P-type transistor 4 is in a non-conductive state. The P-type transistor (first current cut-off circuit) 15 is in a conductive state because the output node O is at the L level, and the P-type transistor (second current cut-off circuit) 16 is in the H level. Therefore, it is in a non-conductive state. From this situation, when the input signal IN changes to the H level, the P-type transistor (first current cut-off circuit) 15 and the first P-type transistor 3 are both in a conductive state. As the N-type transistor 1 shifts to the conductive state, the first current mirror circuit 10 operates to amplify the current flowing through the first N-type transistor 1 to a predetermined factor α × β. Therefore, the same operation as the level shift circuit shown in FIG. 1 is ensured. In this situation, the inverting input signal XIN changes from the H level to the L level, and the second P-type transistor 4 and the P-type transistor (second current cutoff circuit) 16 are both in a non-conducting state. The second current mirror circuit 11 does not operate.

  Then, when the change of the input signal IN to the H level and the change of the inverted input signal XIN to the L level are finished, the change of the output node O to the H level is finished, and the P-type transistor (first current cutoff circuit) ) 15 is in a non-conductive state, the current path from the high voltage power supply VDD to the P-type current mirror circuit 10P of the first current mirror circuit 10 is cut off, and the current flowing through the P-type current mirror circuit 10P is cut off. The Similarly, as the change of the output node O to the H level is completed, the first P-type transistor 3 is turned off, so that the N-type current mirror circuit of the first current mirror circuit 10 from the high voltage power supply VDD. The current path to 10N is cut off, and the current flowing through the N-type current mirror circuit 10N is cut off. Therefore, in the present embodiment, it is possible to reliably prevent the P-type current mirror circuit 10P of the first current mirror circuit 10 from flowing a steady current wastefully when the input signal IN is in a steady state of H level. Thus, low power consumption can be achieved.

  When the input signal IN is in a steady state at H level, the inverted input signal XIN is in a steady state at L level, and the inverted output node XO is in a steady state at L level. As shown, when the second P-type transistor 4 and the P-type transistor (second current cutoff circuit) 16 are turned on and the inverting input signal XIN next changes to H level, It is prepared to enable the amplification operation of the mirror circuit 11.

  The case where the input signal IN is in the steady state at the H level has been described above, but the operation when the inverted input signal XIN is in the steady state at the H level is the same as that described above.

  In this embodiment, it goes without saying that only one of the output signal O and the inverted output signal XO may be output externally.

(Third embodiment)
FIG. 8 shows a level shift circuit according to a third embodiment of the present invention.

  The level shift circuit of FIG. 6 is a further improvement of the level shift circuit of the second embodiment shown in FIG. That is, in the level shift circuit shown in FIG. 8, first and second change speed acceleration circuits 20 and 21 are added to the level shift circuit of FIG. As will be described later, the first and second change rate acceleration circuits 20 and 21 accelerate the change rate of the inverted output node XO and the output node O from the L level to the H level.

  The first change speed acceleration circuit 20 includes a first P-type transistor 30 connected in parallel to an input-side P-type transistor 5a constituting the P-type current mirror circuit 10P of the first current mirror circuit 10. And a first buffer circuit 33 including two inverter circuits 31 and 32. The first P-type transistor 30 is set to have a large gate width and a very large current driving capability with respect to the P-type transistor 5a on the input side of the P-type current mirror circuit 10P connected in parallel. In the first buffer circuit 33, one inverter circuit 31 has a P-type transistor 31P and an N-type transistor 31N connected in series between the high-voltage power supply VDD and the ground, and these transistors 31P, 31N An inverted output node XO is connected to both gate electrodes, and the other inverter circuit 32 is connected to the output side (a connection point between the drain electrode of the P-type transistor 31P and the drain electrode of the N-type transistor 31N). The output side of 32 is connected to the gate electrode of the P-type transistor 30.

  Similarly, the second change speed acceleration circuit 21 includes a second P-type transistor 35 connected in parallel to the input-side P-type transistor 7a constituting the P-type current mirror circuit 11P of the second current mirror circuit 11. And a second buffer circuit 38 including two inverter circuits 36 and 37. Since the connection relationship of these elements is the same as that of the first change speed acceleration circuit 20, the description thereof is omitted.

  Next, the operation of the present embodiment will be described. First, in the configuration of FIG. 3 showing the second embodiment, in the output node O and the inverted output node XO, the change from the L level to the H level is slower than the change from the H level to the L level. Explain the tendency to become.

  This tendency will be described with reference to FIG. In FIG. 6, when the input signal IN changes from L level to H level and the inverted input signal XIN changes from H level to L level, the H level of the output node O against the change of the inverted output node XO to L level. This illustrates that the change to

  In FIG. 6, as the input signal IN changes to the H level, the inverted output node XO quickly changes from the H level to the L level by the current amplification action of the first current mirror circuit 10 as described above. Therefore, the second P-type transistor 4 and the P-type transistor (second current cutoff circuit) 16 shift from the non-conductive state shown in FIG. 6 to the conductive state shown in FIG. As a result, a current path from the high-voltage power supply VDD to the P-type current mirror circuit 11P of the second current mirror circuit 11 through the P-type transistor (second current cutoff circuit) 16 is configured. At this time, since the inverting input signal XIN is at the L level and the second N-type transistor 2 is in a non-conductive state, the P-type current mirror circuit 11P of the second current mirror circuit 11 is switched from the high voltage power supply VDD. A current begins to flow through the P-type transistor 7a on the input side so as to charge the parasitic capacitance of the node N (the drain electrode of the P-type transistor 7a and the gate electrodes of both P-type transistors 7a and 7b). Until the voltage rises to the non-conductive potential of both P-type transistors 7a and 7b. The P-type transistor 7a on the input side of the P-type current mirror circuit 11P has a gate width smaller than that of the P-type transistor 7b on the output side in terms of the function of the current mirror circuit, as can be seen from the above formula, and its current drive. Since the capacity is small, the period during which the current continues to flow becomes long. While this current flows, the second current mirror circuit 11 allows an amplified current to flow from the N-type transistor 8b on the output side of the N-type current mirror circuit 11N. Here, in the output node O, the second P-type transistor 4 becomes conductive with the change of the inverted output node XO to the L level, the current is supplied from the high voltage power supply VDD, and the L level to the H level. However, the change to the H level tends to be delayed by the amplified current from the N-type transistor 8b to the ground.

  However, in the present embodiment, such a tendency can be eliminated by the first and second change rate acceleration circuits 20 and 21. This will be described below.

  The case where the input signal IN changes from the L level to the H level and the inverted input signal XIN changes from the H level to the L level as described above will be described. First, as shown in FIG. 9, when the input signal IN is at L level and the inverted input signal XIN is at H level, the output node O is at L level and the inverted output node XO is at H level. For this reason, in the second speed change acceleration circuit 21, the P-type transistor 36P of the inverter circuit 36 is turned on, the N-type transistor 36N is turned off, and the gate potential of the P-type transistor 35 becomes L level. The P-type transistor 35 is in a conductive state.

  Thereafter, as shown in FIG. 10, when the input signal IN changes to the H level and the inverted input signal XIN changes to the L level, the inverting output node XO is set to the L level by the amplification action of the first current mirror circuit 10 as described above. By changing to the level, the second P-type transistor 4 and the P-type transistor (second current cutoff circuit) 16 become conductive. As a result, a high current is supplied to the node N from the high voltage power supply VDD via the P-type transistor (second current cutoff circuit) 16 and the second P-type transistor 35 having a high capacity of the second change speed acceleration circuit 21. Flows to charge the parasitic capacitance of the node N at high speed. As a result, the period until the two P-type transistors 7a and 7b of the P-type current mirror circuit 11P become non-conductive is shortened, and the amplification is performed by the N-type transistor 8b on the output side of the N-type current mirror circuit 11N. The current supply time is also shortened, the time for the output node O to change from the L level to the H level is also shortened, and the rate of change of the output node O to the H level is promoted.

  When the output node O changes to the H level in this way, as shown in FIG. 11, in the second change speed acceleration circuit 21, the P-type transistor 36P of the inverter circuit 36 is brought into a non-conductive state, and the N-type transistor 36N Becomes conductive, the potential of the gate electrode of the second P-type transistor 35 becomes H level, and the second P-type transistor 35 becomes non-conductive. This prepares for the next change of the inverted input signal XIN to the H level.

  The case where the output node O changes to the H level has been described above as an example, but the same applies to the case where the inverted output node XO changes to the H level.

  Therefore, in the present embodiment, it is possible to effectively shorten the change time from the L level to the H level of the output node O and the inverted output node XO.

  In this embodiment, it goes without saying that only one of the output node O and the inverted output node XO may be output to the outside. Needless to say, the first and second buffer circuits 33 and 38 may be simply wired if a sufficient delay occurs.

(Fourth embodiment)
FIG. 12 shows a level shift circuit according to a fourth embodiment of the present invention.

  The level shift circuit shown in the figure is a further improvement of the third embodiment. Specifically, the first and second change speed acceleration circuits 20 and 21 of the level shift circuit shown in FIG. 8 are further improved.

  That is, in the level shift circuit of FIG. 12, the first control circuit 40 is added inside the first change speed acceleration circuit 20. The first control circuit 40 includes an inverter 40a connected to the output node O, and a P-type transistor 40b receiving the output of the inverter 40a at a gate electrode. The source electrode of the P-type transistor 40b is a high voltage power supply. The drain electrode is connected to VDD, and the drain electrode is connected to the source electrode of the P-type transistor 31P of the inverter circuit 31 constituting the first buffer circuit 33. Therefore, after the signal of the output node O, that is, the output signal O changes from the L level to the H level, the first control circuit 40 turns on the P-type transistor 40a and supplies the high voltage power supply VDD to the first voltage source VDD. And the operation of the buffer circuit 33 is allowed.

  On the other hand, a second control circuit 41 is added inside the second change rate acceleration circuit 21. The second control circuit 41 includes an inverter 41a connected to the inverting output node XO, and a P-type transistor 41b that receives the output of the inverter 41a at its gate electrode. The source electrode of the P-type transistor 41b has a high voltage. The drain electrode is connected to the power supply VDD, and the drain electrode is connected to the source electrode of the P-type transistor 36P of the inverter circuit 36 constituting the second buffer circuit 38. Accordingly, in the second control circuit 41, after the inverted output signal XO changes from the L level to the H level, the P-type transistor 41a becomes conductive and connects the high voltage power supply VDD to the second buffer circuit 38. Then, the operation of the buffer circuit 38 is allowed.

  The fourth embodiment has the following operational effects as compared to the third embodiment. That is, in the third embodiment, as shown in FIG. 10, the P-type transistor 16 is turned on by the change of the inverting output node XO from the H level to the L level, and the second voltage source VDD is turned on. A large current is supplied to the parasitic capacitance of the node N through the high-capacity P-type transistor 35 of the change speed promoting circuit 21. At this time, the change of the inverted output node XO from the H level to the L level is the first level. The first P-type transistor 30 is propagated to the gate electrode of the first P-type transistor 30 after a predetermined delay time through the first buffer circuit 33 of the change rate acceleration circuit 20 of the first P-type transistor 30. In this case, when the delay time of the first buffer circuit 33 is short, the first P-type transistor 30 of the first change speed acceleration circuit 20 is set before the potential of the inverting output node XO is fixed at the L level. Is conducted, and a large current from the high voltage power supply VDD charges the drain electrode of the first N-type transistor 1 via the first P-type transistor 30, so that the inverting output node XO is changed from the H level accordingly. It takes time to determine the L level, and a delay occurs in determining the L level. This problem can be solved by increasing the delay time of the first buffer circuit 33. However, if it is set too large, the cycle of the input signal IN is limited to this delay time and the cycle of the input signal IN is set longer. Need to do.

  In contrast, in the present embodiment, the first control circuit 40 allows the operation of the first buffer circuit 33 of the first change speed acceleration circuit 20 only after the potential of the output node O changes to the H level. Therefore, the conduction of the first P-type transistor 30 of the first change speed acceleration circuit 20 can be controlled by both the change of the output node O to the H level and the change of the inverted output node XO to the L level. Such a delay in determining the inverted output node XO to the L level can be effectively suppressed. As described above, it is possible to suppress a delay in determining the output node O to the L level.

  In this embodiment, it goes without saying that only one of the output node O and the inverted output node XO may be output to the outside.

(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described.

  FIG. 13 shows the level shift circuit of this embodiment. The level shift circuit shown in the figure is obtained by adding a stabilization circuit 50 to the level shift circuit shown in FIG.

  The stabilization circuit 50 includes first and second N-type transistors 50a and 50b. The first N-type transistor 50a has a gate electrode connected to the output node O, a drain electrode connected to the inverted output node XO, and a source electrode grounded. On the other hand, in the second N-type transistor 50b, the gate electrode is connected to the inverted output node XO, the drain electrode is connected to the output node O, and the source electrode is grounded.

  In the level shift circuit shown in FIG. 3, in the initial state where the high voltage power supply VDD starts to be supplied to the level shift circuit, when both the input signal IN and the inverted input signal XIN are in the potential indefinite state, The second N-type transistors 1 and 2 and the two P-type transistors 3 and 4 are all in a conductive state, and the N-type current mirror circuits 10N and 11N of the N-type current mirror circuits 10N and 11N are turned on from the high voltage power supply VDD. Then, a through current flows to the ground, and the potentials of the output node O and the inverted output node XO are also indefinite. This through current continues in a transient manner until the input signal IN and the inverted input signal XIN are fixed at a predetermined L or H level.

  However, in the present embodiment, for example, when the potential of the inverting output node XO is higher than the potential of the output node O, the second N-type transistor 50b of the stabilization circuit 50 increases the conduction tendency and the second The non-conducting tendency of the P-type transistor 4 is strengthened, thereby further reducing the potential of the output node O. Further, as the potential of the output node O decreases, the first N-type transistor 50a of the stabilization circuit 50 increases the non-conduction tendency and the conduction tendency of the first P-type transistor 3 also increases. Further increase the potential of XO. As a result of such positive feedback, the output node O is fixed at the L level and the inverted output node XO is determined at the H level at an early stage.

  Therefore, in the present embodiment, even when the input signal IN and the inverted input signal XIN are indefinite in the initial state, the potentials of the output node O and the inverted output node XO can be determined at the L or H level at an early stage, It is possible to effectively reduce the transient through current flowing until the determination.

(Modification)
FIG. 14 shows a modification of the level shift circuit of the fifth embodiment.

  In the fifth embodiment, the stabilization circuit 50 is added to the level shift circuit of FIG. 3, but in this embodiment, the level shift circuit of the fourth embodiment shown in FIG. The stabilization circuit 50 is added. Other configurations are the same as those in FIG.

  In each of the first to fifth embodiments, the level shift circuit has been described as having the P-type transistors 3 and 4. However, the present invention is not limited to this, and other various configurations are possible. The present invention is applicable to a level shift circuit, and it is sufficient to include at least first and second N-type transistors 1 and 2 for signal input.

  As described above, according to the present invention, even when the input signal is a low voltage, the current drive capability is enhanced by using the current mirror circuit, so that level conversion can be performed at high speed and with low power consumption. It is useful as a level shift circuit used in an LSI that requires operation.

It is a figure which shows the structure of the level shift circuit of the 1st Embodiment of this invention. It is a figure which shows operation | movement of the same level shift circuit. It is a figure which shows the structure of the level shift circuit of the 2nd Embodiment of this invention. In the same level shift circuit, it is a figure which shows the operation | movement at the time of the transition when an input signal changes to H level and an inverting input signal changes to L level. It is a figure which shows operation | movement when the change to the H level of an input signal and the change to the L level of an inverting input signal are complete | finished in the same level shift circuit. In the same level shift circuit, it is a figure which shows the operation | movement at the time of the transition when an input signal changes to H level and an inverting input signal changes to L level. It is explanatory drawing which illustrated that the change from the L level of an output node to H level shows a delay tendency in the same level shift circuit. It is a figure which shows the structure of the level shift circuit of the 3rd Embodiment of this invention. FIG. 10 is a diagram illustrating an operation when an input signal is at an L level and an inverted input signal is at an H level in the same level shift circuit. In the same level shift circuit, it is a figure which shows the operation | movement at the time of the transition in which an input signal changes from L level to H level, and an inverting input signal changes from H level to L level. It is a figure which shows operation | movement when the change to the H level of an input signal and the change to the L level of an inverting input signal are complete | finished in the same level shift circuit. It is a figure which shows the structure of the level shift circuit of the 4th Embodiment of this invention. It is a figure which shows the structure of the level shift circuit of the 5th Embodiment of this invention. It is a figure which shows the structure of the level shift circuit of the modification of the 5th Embodiment of this invention. It is a figure which shows the structure of the conventional level shift circuit.

Explanation of symbols

IN input terminal XIN Inverted input terminal O Output node XO Inverted output node 1 First N-type transistor 2 for signal input Second N-type transistor 10 for signal input First current mirror circuit 11 Second current mirror circuit 10P, 11P P-type current mirror circuit 10N, 11N N-type current mirror circuit 15 P-type transistor (first current cutoff circuit)
16 P-type transistor (second current cutoff circuit)
20 first change speed acceleration circuit 21 second change speed acceleration circuit 30 first P-type transistor 33 first buffer circuit 35 second P-type transistor 38 second buffer circuit 40 first control circuit 41 first 2 control circuit 50 stabilization circuit 50a first N-type transistor 50b second N-type transistor 60 first N-type transistor 61 for current feedback third N-type transistor 65 third current mirror circuit 80 current feedback Second N-type transistor 81 fourth N-type transistor 85 fourth current mirror circuit

Claims (10)

A pair of input terminals and an inverting input terminal, and a pair of output nodes and an inverting output node;
An input signal and an inverted input signal are input to the input terminal and the inverted input terminal, and the amplitude level of the input signal and the inverted input signal is shifted to an amplitude level larger than the amplitude level, and has an amplitude level after the shift. A level shift circuit for transmitting an output signal and an inverted output signal obtained by inverting the output signal to the output node and the inverted output node;
A first N-type transistor for signal input, the input terminal of which is connected to a gate electrode;
A second N-type transistor for signal input in which the inverting input terminal is connected to a gate electrode;
It has at least one set in which a P-type current mirror circuit constituted by P-type transistors and an N-type current mirror circuit constituted by N-type transistors are connected in cascade, and the first N-type transistor and the inverting output node And a first current mirror circuit that amplifies the current flowing through the first N-type transistor by a predetermined factor and draws the amplified current from the inverting output node;
There is at least one set in which a P-type current mirror circuit constituted by a P-type transistor and an N-type current mirror circuit constituted by an N-type transistor are connected in cascade, and the second N-type transistor, the output node, And a second current mirror circuit that amplifies the current flowing through the second N-type transistor by a predetermined factor and draws the amplified current from the output node;
A first current feedback is connected in parallel to the first N-type transistor and controlled by the potential at the connection point between the P-type current mirror circuit and the N-type current mirror circuit in the first current mirror circuit. An N-type transistor;
A second current feedback loop connected in parallel to the second N-type transistor and controlled by the potential at the connection point between the P-type current mirror circuit and the N-type current mirror circuit in the second current mirror circuit. A level shift circuit comprising an N-type transistor. The level shift circuit according to claim 1, wherein
A gate electrode is connected to the inverting input terminal, a drain electrode is connected to a connection point between the P-type current mirror circuit and the N-type current mirror circuit in the first current mirror circuit, and a source electrode is grounded. N-type transistors of
A gate electrode is connected to the input terminal, a drain electrode is connected to a connection point between the P-type current mirror circuit and the N-type current mirror circuit in the second current mirror circuit, and a source electrode is grounded. A level shift circuit comprising: an N-type transistor. In the level shift circuit according to claim 1 or 2,
A first current cut-off circuit connected to the first current mirror circuit and for cutting off a current flowing through the first current mirror circuit after the change of the output signal;
A level shifter comprising: a second current cut-off circuit connected to the second current mirror circuit and cut off a current flowing through the second current mirror circuit after the change of the inverted output signal is completed. circuit. The level shift circuit according to claim 3, wherein
The first current cut-off circuit is configured by a P-type transistor that receives the output signal at a gate electrode,
The level shift circuit, wherein the second current cut-off circuit includes a P-type transistor that receives the inverted output signal at a gate electrode. In the level shift circuit according to claim 3 or 4,
A first connected to the P-type current mirror circuit of the first current mirror circuit in parallel and controlled by the inverted output signal of the inverted output node to increase the speed at which the inverted output signal changes from the L level to the H level. A change speed acceleration circuit of
A second change speed connected in parallel to the P-type current mirror circuit of the second current mirror circuit and controlled by the output signal of the output node to increase the speed at which the output signal changes from L level to H level. A level shift circuit comprising an acceleration circuit. The level shift circuit according to claim 5, wherein
The first change speed acceleration circuit includes:
A first P-type transistor connected in parallel to a P-type current mirror circuit of the first current mirror circuit;
An output side connected to a gate electrode of the first P-type transistor, and a first buffer circuit controlled by an inverted output signal of the inverted output node;
The second rate of change acceleration circuit is
A second P-type transistor connected in parallel to the P-type current mirror circuit of the second current mirror circuit;
A level shift circuit comprising: a second buffer circuit having an output side connected to a gate electrode of the second P-type transistor and controlled by an output signal of the output node. The level shift circuit according to claim 6, wherein
The first change rate acceleration circuit further includes:
A first control circuit for allowing the operation of the first buffer circuit after the change of the output signal of the output node is completed;
The second change rate acceleration circuit further includes:
A level shift circuit, comprising: a second control circuit that allows the operation of the second buffer circuit after the change of the inverted output signal of the inverted output node is completed. The level shift circuit according to claim 1, 2, 3, 4, 5, 6, or 7.
A level shift circuit, comprising: a stabilization circuit that quickly establishes and stabilizes the potential states of the output node and the inverted output node in an initial state where power is supplied. The level shift circuit according to claim 8, wherein
The stabilization circuit includes:
A first N-type transistor having a gate electrode connected to the output node, a drain electrode connected to the inverted output node, and a source electrode grounded;
A level shift circuit, comprising: a second N-type transistor having a gate electrode connected to the inverted output node, a drain electrode connected to the output node, and a source electrode grounded. The level shift circuit according to claim 1, 2, 3, 4, 5, 6, 7, 8, or 9.
At least one of the output signal of the output node and the inverted output signal of the inverted output node is output to the outside.

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