JP4289868B2 - 半導体メモリカード、その制御方法及び半導体メモリカード用インターフェース装置 - Google Patents

半導体メモリカード、その制御方法及び半導体メモリカード用インターフェース装置 Download PDF

Info

Publication number
JP4289868B2
JP4289868B2 JP2002321695A JP2002321695A JP4289868B2 JP 4289868 B2 JP4289868 B2 JP 4289868B2 JP 2002321695 A JP2002321695 A JP 2002321695A JP 2002321695 A JP2002321695 A JP 2002321695A JP 4289868 B2 JP4289868 B2 JP 4289868B2
Authority
JP
Japan
Prior art keywords
output
input
clock
data
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2002321695A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003223623A (ja
JP2003223623A5 (enExample
Inventor
秀樹 河合
穣 中村
智紹 泉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2002321695A priority Critical patent/JP4289868B2/ja
Publication of JP2003223623A publication Critical patent/JP2003223623A/ja
Publication of JP2003223623A5 publication Critical patent/JP2003223623A5/ja
Application granted granted Critical
Publication of JP4289868B2 publication Critical patent/JP4289868B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

JP2002321695A 2001-11-05 2002-11-05 半導体メモリカード、その制御方法及び半導体メモリカード用インターフェース装置 Expired - Lifetime JP4289868B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002321695A JP4289868B2 (ja) 2001-11-05 2002-11-05 半導体メモリカード、その制御方法及び半導体メモリカード用インターフェース装置

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2001339201 2001-11-05
JP2001-339201 2001-11-05
JP2002321695A JP4289868B2 (ja) 2001-11-05 2002-11-05 半導体メモリカード、その制御方法及び半導体メモリカード用インターフェース装置

Publications (3)

Publication Number Publication Date
JP2003223623A JP2003223623A (ja) 2003-08-08
JP2003223623A5 JP2003223623A5 (enExample) 2006-01-05
JP4289868B2 true JP4289868B2 (ja) 2009-07-01

Family

ID=27759062

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002321695A Expired - Lifetime JP4289868B2 (ja) 2001-11-05 2002-11-05 半導体メモリカード、その制御方法及び半導体メモリカード用インターフェース装置

Country Status (1)

Country Link
JP (1) JP4289868B2 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7900007B2 (en) 2004-07-08 2011-03-01 Panasonic Corporation Host device, storage device, and method for accessing storage device
WO2006006388A1 (ja) * 2004-07-08 2006-01-19 Matsushita Electric Industrial Co., Ltd. ホスト機器、記憶装置、及び記憶装置へのアクセス方法
JP4892852B2 (ja) * 2005-03-29 2012-03-07 富士通セミコンダクター株式会社 シリアルインターフェースの制御方法
US7464193B2 (en) * 2005-08-29 2008-12-09 Sandisk Il Ltd. Device and method for configuring a flash memory controller
US7912439B2 (en) 2005-11-25 2011-03-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and operating method thereof
JP5072330B2 (ja) * 2005-11-25 2012-11-14 株式会社半導体エネルギー研究所 半導体装置
JP4910391B2 (ja) * 2005-12-26 2012-04-04 セイコーエプソン株式会社 情報処理装置
KR101177555B1 (ko) * 2006-02-01 2012-08-27 삼성전자주식회사 메모리 카드, 메모리 카드의 데이터 구동 방법, 그리고메모리 카드 시스템
JP5031304B2 (ja) * 2006-09-11 2012-09-19 キヤノン株式会社 情報処理装置
JPWO2008093606A1 (ja) 2007-01-30 2010-05-20 パナソニック株式会社 不揮発性記憶装置、不揮発性記憶システム、及びアクセス装置

Also Published As

Publication number Publication date
JP2003223623A (ja) 2003-08-08

Similar Documents

Publication Publication Date Title
US6842395B2 (en) Semiconductor memory card, method of controlling the same and interface apparatus for semiconductor memory card
JP3521233B2 (ja) Ｓｍｉｉ規格による装置間のデータ転送中継装置及びその方法
JP3990570B2 (ja) プログラマブルロジックデバイス回路に結合されるクロックデータリカバリ回路
US6940782B2 (en) Memory system and control method for the same
US8301932B2 (en) Synchronising between clock domains
US8520464B2 (en) Interface circuit and semiconductor device incorporating same
JP4289868B2 (ja) 半導体メモリカード、その制御方法及び半導体メモリカード用インターフェース装置
KR20190084755A (ko) 모바일 장치 및 그것의 인터페이싱 방법
WO2018173623A1 (ja) １線式シリアルデータ伝送回路及び１線式シリアルデータ伝送方法
US20180284835A1 (en) Separate clock synchronous architecture
JP2000200482A (ja) デ―タ入出力回路及びインタフェ―ス方式
JP3593104B2 (ja) クロック切替回路
US6754112B2 (en) Integrated circuit devices having delay circuits for controlling setup/delay times of data signals that are provided to memory devices
JP2002318638A (ja) 情報処理システム及び半導体集積回路装置
KR102811264B1 (ko) 이미지 장치 및 그 구동 방법
US7965582B2 (en) Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus
US20220200610A1 (en) Clocking system and a method of clock synchronization
KR100408397B1 (ko) 데이터 지연시간을 외부에서 조절할 수 있는 반도체메모리장치 및 이를 구비하는 메모리모듈
KR20030088324A (ko) 지연동기루프를 구비하는 반도체 메모리 장치 및 반도체메모리 장치에서의 데이터의 출력방법
JP2007312321A (ja) シリアル・パラレル変換用の半導体集積回路
US20080201499A1 (en) Asynchronous Data Buffer
JP2004185175A (ja) 拡張用ｆｉｆｏ回路及び送受信装置
JPH08237235A (ja) ディジタル通信システム
JP2004228844A (ja) 半導体集積回路
JP2000261510A (ja) 送信装置、受信装置

Legal Events

Date Code Title Description
RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20050525

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20051104

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20051104

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20061129

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20071018

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080722

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080917

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090303

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090331

R150 Certificate of patent or registration of utility model

Ref document number: 4289868

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120410

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130410

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130410

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140410

Year of fee payment: 5