JP4288573B2 - Semiconductor wafer chip forming method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a manufacturing technique of a semiconductor sensor and a semiconductor actuator (collectively referred to as “semiconductor device”) having a thin diaphragm or beam formed by etching a part of a semiconductor wafer such as a silicon wafer. Related to chip technology.
[0002]
[Prior art]
Semiconductor devices using semiconductor wafers, particularly silicon wafers, are becoming smaller and more accurate every day. Some of them utilize a diaphragm formed by etching a part of a semiconductor to make it thin or leaving a thin film formed on the semiconductor. Such a structure is used for a pressure sensor, a gas sensor, a micro valve, and the like. There is also an acceleration sensor that uses a semiconductor processed into a thin beam.
A semiconductor device having such a structure can be obtained by manufacturing a wafer in which a large number of semiconductor devices are integrated by a wafer process, and forming the wafer into chips at the final stage. However, since a thin diaphragm or the like is formed on this wafer, the dicing method used in the case of a normal wafer cannot be used when forming a wafer into chips. The reason is that a diaphragm etc. will be damaged by the water sprayed in the case of dicing.
[0003]
As a method for forming a chip without damaging a semiconductor wafer having a thin part such as a diaphragm, an ultrasonic cutter is used, or an ultrasonic cutter is used in which an etching groove is previously formed on a dividing line by dry etching or wet etching. A method is disclosed in Patent Document 1. Further, Patent Document 2 discloses a method of forming a chip-forming groove at the same time when etching a part of a semiconductor wafer to form a thin portion, and making a chip using this chip-forming groove. Yes. In the method disclosed in Patent Document 2, anisotropic etching which is wet etching is used.
[0004]
FIG. 3 shows a state in a process related to chip formation in the wafer process in order to explain an example of such a chip formation method. FIG. 3A is a cross section showing the silicon wafer 1 before processing. 4B is a cross-sectional view showing a state in which a silicon oxide film 2 is formed as a thin film diaphragm 21, FIG. 3C is a cross-sectional view showing a state in which an aluminum film 3 is formed as an etching mask, and FIG. 3 is a cross-sectional view showing a state of patterning 3, and FIG. 5E is a cross-sectional view showing a state after plasma etching.
A silicon oxide film 2 to be a thin film diaphragm 21 is formed on one surface of the silicon wafer 1 [FIG. 3A] [FIG. 3B], and the silicon wafer 1 is selected by plasma etching on the opposite surface. Thus, an aluminum film 3 serving as an etching mask for etching is produced [FIG. 3C]. The aluminum film 3 is patterned by photolithography to become a patterned aluminum film 3a from which portions of the aluminum film corresponding to the diaphragm pattern 31 and the chip-forming groove pattern 32 have been removed [FIG. 3 (d)]. . Using this patterned aluminum film 3a as an etching mask, plasma etching is performed until there is no more silicon in the portion of the diaphragm pattern 31 having a large area, and the thin film diaphragm 21 is formed in this portion. At the same time, the silicon in the chip-forming groove pattern 32 is also etched, but due to the size effect, the entire silicon thickness is not etched due to the size effect, and a part of it remains for chip formation. A groove 11 is formed [FIG. 3 (e)]. The silicon remaining under the chip-forming groove 11 can be handled as a wafer, and the wafer is cut into chips by cleaving at the chip-forming groove 11 portion.
[0005]
The balance between ease of chip formation and ease of handling as a wafer is determined by the original thickness of the wafer and the thickness of silicon remaining under the chip formation groove 11 (remaining thickness). On the other hand, since the remaining thickness is determined by the relative relationship between the size of the diaphragm pattern 31 and the width of the chip-forming groove pattern 32, the width of the chip-forming groove pattern 32 is determined in accordance with the optimum value of the remaining thickness.
However, the conventional method of forming the chip-forming groove 11 by etching the dicing line has the feature that it can be formed into a chip without using the dicing method, but the chip-forming groove 11 is formed on the outer periphery of the wafer. Since the thin portion exists, there is a problem that the wafer is easily damaged.
[0006]
On the other hand, it is not a chip of a semiconductor wafer having a thin part, but in order to obtain a thin chip, after the wafer is polished and thinned in the final step of the wafer process, a separation groove is formed in an area excluding the outer periphery of the wafer. A method of forming a chip by dicing is disclosed in Patent Document 3. By not forming grooves on the outer periphery of the wafer, the mechanical strength of the wafer is ensured.
[0007]
[Patent Document 1]
Japanese Patent Laid-Open No. 7-240392 [Patent Document 2]
JP-A-6-216244 [Patent Document 3]
JP-A-5-198671 [0008]
[Problems to be solved by the invention]
The object of the present invention is to manufacture a semiconductor wafer in which a thin part is formed by plasma etching and it is difficult to apply a dicing method to chip formation, and the possibility of damaging the wafer when handling the wafer is low. It is an object of the present invention to provide a method capable of increasing the number of semiconductor devices that can be taken without increasing the number of steps.
[0009]
[Means for Solving the Problems]
The invention of claim 1 is a semiconductor wafer in which a semiconductor wafer, which is an assembly of a plurality of semiconductor devices having thin portions such as a thin film diaphragm formed by plasma etching, is divided into individual semiconductor devices using a chip-forming groove. In the chip forming method, a chip forming groove is formed in a region excluding the outer peripheral portion of the wafer at the same time as the plasma etching.
At the same time as the plasma etching for forming a thin portion such as a thin film diaphragm, a chip-forming groove is formed in the region excluding the outer peripheral portion of the wafer. Therefore, it is necessary to add a step for forming the chip-forming groove. In addition, since the outer peripheral portion of the wafer has the original thickness, the strength of the outer peripheral portion of the wafer that is highly likely to be damaged during handling can be secured, and a wafer that is not easily damaged can be obtained. Note that microcracks are not generated in the processed portion by plasma etching, and the processed corner portion is a curved surface and does not become sharply pointed, so stress concentration hardly occurs. Due to these effects, even if a chip groove having the same width and depth is formed in the same region of the semiconductor wafer, the wafer having the chip groove formed by plasma etching is formed by the dicing method. It is less likely to be damaged in later handling than the wafer on which the film is formed.
[0010]
The invention of claim 1, further a shape of the terminal portion of the chip groove, a shallow enough to reduce the width and depth approaches the end.
When the shape of the terminal portion of the chip-forming groove becomes narrower and shallower as it approaches the terminal end, the chip-forming groove has the same width and the same depth as the terminal portion. As compared with the above, the strength of the wafer is increased, and the wafer is more difficult to break. In other words, if the wafers have the same strength, the end of the chip groove can be brought closer to the outer edge, and the number of semiconductor devices that can be taken from a single wafer can be increased. Become.
[0011]
According to a second aspect of the present invention, in the first aspect of the invention, the shape in the width direction that becomes narrower as the end is approached is an isosceles triangle having the end as an apex.
If the shape in the width direction that narrows toward the end is an isosceles triangle with the end as the apex, the end of the chip-forming groove is uniformly reduced in width as it approaches the end. The depth also decreases monotonously, making it the shape where stress concentration is most unlikely to occur.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
The semiconductor wafer chip forming method according to the present invention forms a chip forming groove at the same time when a thin portion such as a diaphragm is formed by plasma etching, and does not form the chip forming groove on the outer peripheral portion of the semiconductor wafer. Thus, the strength reduction of the outer peripheral portion of the semiconductor wafer is eliminated, and the semiconductor wafer after forming the chip-forming groove is prevented from being easily damaged.
In the following, embodiments of the semiconductor wafer chip forming method according to the present invention will be described in more detail using reference examples and examples.
[0013]
[ Reference example]
FIG. 1 shows the appearance of a semiconductor wafer (hereinafter simply referred to as “wafer”) 1 for explaining a reference example. FIG. 1A is a plan view showing the entire wafer 1 and FIG. 1B is an enlarged plan view showing an enlarged portion. FIG. 2C is a sectional view taken along the line AA.
The chip-forming groove 11a of this reference example is not formed on the outer peripheral portion of 5 to 10 mm from the outer edge of the wafer 1, as shown in FIG.
Since the chip-forming groove 11a is formed in the same process as the chip-forming groove 11 described with reference to FIG. 3 in the section “Prior Art”, detailed description of the process is omitted, and different points are described. Only explained.
[0014]
The chip forming groove 11a differs from the chip forming groove 11 in that the chip forming groove 11 in FIG. 3 is formed up to the outer edge of the wafer 1, whereas the chip forming groove 11a in this reference example is shown in FIG. As shown in FIG. 1, it is not formed on the outer peripheral portion of the wafer 1. That is, when the aluminum film is patterned, the aluminum film is patterned using a mask in which the chip-forming groove pattern is not formed on the outer peripheral portion of the wafer 1.
When a semiconductor is etched by plasma etching, unlike a machining process such as dicing, microcracks are not left in the processed part, and the processed corner part is curved and not sharply pointed. Mechanical strength can be maintained, making it difficult to break during handling.
[0015]
Based on the above method, a silicon wafer with a diameter of 100 mm and a thickness of 400 μm, a 2.5 mm square semiconductor sensor having a thin film diaphragm with a diameter of 0.5 mm in the center, and a 25 μm-wide groove for chip formation are placed on the outer periphery of the wafer at 8 mm. When the semiconductor sensor was manufactured by arranging it in the region excluding the wafer, the wafer was not damaged.
According to this reference example, since the groove for chip formation can be formed at the same time in the plasma etching process for forming a thin film diaphragm or the like, no additional process is required and no additional man-hours are required.
[Real施例]
Figure 2 shows the appearance of the wafer 1 for describing the real施例, (a) is a plan view showing an entire wafer 1, (b) is an enlarged plan view showing an enlarged portion, (c) its AA cross It corresponds to FIG. 1 of the reference example.
[0016]
This embodiment is characterized by the shape of the terminal portion of the chip-forming groove. That is, in the chip-forming groove 11b of this embodiment, as shown in FIG. 2, the shape of the terminal end portion 111b is an isosceles triangle with the shape in the width direction having the end as an apex. If the shape in the width direction is set in this way, the depth of the groove becomes shallower as it approaches the end corresponding to the width. When the chip-forming groove 11b of this embodiment is compared with the chip-forming groove 11a of the reference example, the thickness of the semiconductor remaining under the terminal portion 111b of the chip-forming groove 11b is the case of the chip-forming groove 11a. As the mechanical strength is increased, the chip-forming groove 11b is larger than the chip-forming groove 11a, and damage during handling is further reduced than in the reference example. This means that if the wafer has the same strength, the width of the outer peripheral portion where the chip-forming groove is not formed can be made narrower, and the number of semiconductor devices that can be taken from the wafer can be increased.
[0017]
In the above reference examples and examples, the case of a semiconductor sensor provided with a thin film diaphragm has been described. However, the present invention relates to a semiconductor sensor using a thin semiconductor film as a diaphragm, or a semiconductor sensor provided with a thin film or a thin semiconductor beam. The present invention is applicable to all semiconductor devices such as semiconductor actuators manufactured by etching a semiconductor by plasma etching.
[0018]
【The invention's effect】
According to the first aspect of the present invention, since the groove for chip formation is formed in the region excluding the outer peripheral portion of the wafer at the same time as the plasma etching for forming the thin portion such as the thin film diaphragm, the chip formation groove is formed. No additional process is required, and the outer peripheral portion of the wafer has the original thickness, so that the strength of the outer peripheral portion of the wafer, which is likely to be damaged during handling, can be secured, and the wafer is not easily damaged. Can be obtained. Note that microcracks are not generated in the processed portion by plasma etching, and the processed corner portion is a curved surface and does not become sharply pointed, so stress concentration hardly occurs. Due to these effects, even if a chip-forming groove having the same width and depth is formed in the same region of the wafer, the wafer for which the chip-forming groove is formed by plasma etching is formed by the dicing method. The formed wafer is less likely to be damaged by later handling.
[0019]
Therefore, according to the present invention, as a method of forming a semiconductor wafer in which a thin portion is formed by plasma etching and it is difficult to apply the dicing method to chip formation, the possibility of damaging the wafer during handling of the wafer is low. In addition, it is possible to provide a method that does not require an increase in manufacturing steps.
In the invention of claim 1, further a shape of the end portion of the groove for chips, a shallow enough to reduce the width and depth approaches the end. When the shape of the terminal portion of the chip-forming groove becomes narrower and shallower as it approaches the terminal end, the chip-forming groove has the same width and the same depth as the terminal portion. As compared with the above, the strength of the wafer is increased, and the wafer is more difficult to break. In other words, if the wafers have the same strength, the end of the chip groove can be brought closer to the outer edge, and the number of semiconductor devices that can be taken from a single wafer can be increased. Become.
[0020]
Therefore, according to the present invention, as a method of forming a semiconductor wafer in which a thin portion is formed by plasma etching and it is difficult to apply the dicing method to chip formation, the possibility of damaging the wafer during handling of the wafer is low. Therefore, it is possible to provide a method that can increase the number of semiconductor devices that can be taken without increasing the number of manufacturing steps.
In the invention of claim 2 , the shape in the width direction that becomes narrower as it approaches the end is an isosceles triangle having the end as a vertex. If the shape of the end is an isosceles triangle with the end as the apex, the width of the end of the groove for chip formation is reduced uniformly as it approaches the end, and the depth also decreases monotonously. However, the shape is such that stress concentration is least likely to occur. Therefore, according to the present invention, damage to the wafer is less likely to occur.
[Brief description of the drawings]
FIG. 1 shows a wafer appearance for explaining a reference example of a semiconductor wafer chip forming method according to the present invention, (a) is a plan view showing the whole wafer, (b) is an enlarged plan view showing an enlarged portion, c) shows a wafer appearance for explaining the actual施例chip method of a semiconductor wafer according to the AA cross-sectional view Figure 2 the present invention, (a) is a plan view showing an entire wafer, (b) is an enlarged FIG. 3C is a cross-sectional view taken along line AA of the semiconductor sensor according to the present invention. FIG. 3 shows a part of the state of the wafer during the wafer process of the semiconductor sensor targeted by the present invention. (B) is a sectional view showing a state in which a silicon oxide film is formed on the lower surface, (c) is a sectional view showing a state in which an aluminum film is formed on the upper surface, and (d) is a state in which the aluminum film is patterned. (E) is a plasma etch. Sectional view showing a ring state EXPLANATION OF REFERENCE NUMERALS
1 Silicon wafer
11, 11a, 11b Chip groove
111a, 111b Chip end 2 for siliconization Silicon oxide film
21 Thin film diaphragm 3 Aluminum film
3a patterned aluminum film
31 Diaphragm pattern 32 Chip pattern groove pattern

Claims (2)

A semiconductor wafer chip forming method for dividing a semiconductor wafer, which is an assembly of a plurality of semiconductor devices having thin portions such as thin film diaphragms formed by plasma etching, into individual semiconductor devices using a chip forming groove. ,
Simultaneously in the same step as the plasma etching, a chip-forming groove is formed in a region excluding the outer peripheral portion of the semiconductor wafer, and the shape of the terminal portion of the chip- forming groove is reduced in width and depth as approaching the terminal. Shallow ,
A method for making a semiconductor wafer into a chip. The shape in the width direction, which narrows toward the end, is an isosceles triangle with the end as an apex ,
The semiconductor wafer chip forming method according to claim 1.

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