JP4281674B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- JP4281674B2 JP4281674B2 JP2004336970A JP2004336970A JP4281674B2 JP 4281674 B2 JP4281674 B2 JP 4281674B2 JP 2004336970 A JP2004336970 A JP 2004336970A JP 2004336970 A JP2004336970 A JP 2004336970A JP 4281674 B2 JP4281674 B2 JP 4281674B2
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Description
本発明は、金属膜配線に銅(Cu)などを用いた半導体装置の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor device using copper (Cu) or the like for metal film wiring.
一般に、低抵抗で高いエレクトロマイグレーション(EM)耐性を有するCu配線(金属膜配線)は、高集積化し微細化されたLSI配線用の高信頼性材料として期待されている。
微細加工の難しいCu配線を作製する有効な手法の一つに、あらかじめ溝・ビア加工を施した下地にCu膜の埋め込みを行うダマシン法がある。ダマシン法を用いてCu膜の埋め込みを行う手法として、現在実用化されている技術が、電解めっきである。
In general, Cu wiring (metal film wiring) having low resistance and high electromigration (EM) resistance is expected as a highly reliable material for highly integrated and miniaturized LSI wiring.
One effective method for producing a Cu wiring that is difficult to finely process is a damascene method in which a Cu film is embedded in a base that has been previously processed with grooves and vias. As a technique for embedding a Cu film using the damascene method, a technique that is currently in practical use is electrolytic plating.
図3に電解めっきを用いたダマシンCu配線の形成プロセスの一例を示す。このプロセスでは、まず、あらかじめ溝・ビア加工を施した下地基板301(含む下地配線302)(図3−1)を、不活性雰囲気(ArもしくはN2)にて200〜350℃のアニール処理を行い、加工面(溝・ビアの側壁ならびに底面)に吸着している水分等を除去する。
次に、前記下地基板301(含む下地配線102)の下層配線表面にできた高抵抗層303(主として酸化銅)を除去する目的で、イオン化させたArを基板バイアスで引き込んで物理的除去を行う(図3−2)。次にバリアメタル304(TaN,TiN、WN等)の成膜を行ってから、電解めっき用シード層305としてCuの成膜を行なう(図3−3)。
さらに、電解めっきによりCuの埋め込み成膜を行い、めっき層306を形成する(図3−4)。
最後に、CMPにより上部の余分なCu層およびバリアメタルを除去し、平坦化を行う(図3−5)。以上の工程で、Cu配線の形成を行う。
FIG. 3 shows an example of a damascene Cu wiring formation process using electrolytic plating. In this process, first, the base substrate 301 (including the base wiring 302) (FIG. 3-1) that has been previously processed with grooves and vias is annealed at 200 to 350 ° C. in an inert atmosphere (Ar or N 2 ). To remove moisture adsorbed on the processing surface (side walls and bottom surfaces of grooves and vias).
Next, for the purpose of removing the high-resistance layer 303 (mainly copper oxide) formed on the lower wiring surface of the base substrate 301 (including the base wiring 102), the ionized Ar is drawn with a substrate bias and physically removed. (Fig. 3-2). Next, after forming a barrier metal 304 (TaN, TiN, WN, etc.), Cu is formed as a
Further, Cu-embedded film formation is performed by electrolytic plating to form a plating layer 306 (FIG. 3-4).
Finally, the excess Cu layer and barrier metal at the top are removed by CMP and planarization is performed (FIGS. 3-5). Cu wiring is formed through the above steps.
このようにして、あらかじめ溝・ビア加工を施した下地に、電解めっきにより、Cu膜の埋め込みが行なわれているが、今後のデバイスにおいては、絶縁膜が低誘電率膜、特に誘電率を下げるために、空孔を有する低誘電率膜の使用が検討されている。 In this way, the Cu film is buried by electrolytic plating on the ground / grooved base in advance, but in future devices, the insulating film will lower the dielectric constant, especially the dielectric constant. Therefore, use of a low dielectric constant film having pores has been studied.
例えば、上述に示した、特許文献の如く、低誘電率絶縁膜特に空孔を有する低誘電率絶縁膜上にバリアメタルを成膜する場合、下層配線表面にできた高抵抗層をArイオンで物理的に除去すると、あらかじめ溝・ビア加工を施した間口部分がArイオンによりたたかれて広がってしまい(図3−2)、隣り合う配線間がショートしてしまうという問題がある。また、ビア底の高抵抗層を除去する際に、ArイオンでたたかれたCu成分が、ビア側壁に付着し、後のプロセス温度において、Cuが、絶縁膜中を拡散し、配線間のリーク電流が増大し、配線の性能を悪化させる原因となる。
また、Arイオンにより、低誘電率膜にダメージが入り、配線間容量の増加、膜の収縮率の問題が生じる。
For example, when a barrier metal is formed on a low dielectric constant insulating film, particularly a low dielectric constant insulating film having holes, as shown in the above-mentioned patent document, the high resistance layer formed on the lower wiring surface is formed of Ar ions. If it is physically removed, the gap portion that has been previously processed with grooves and vias is struck and spread by Ar ions (FIG. 3-2), and there is a problem that adjacent wirings are short-circuited. Further, when the high resistance layer at the bottom of the via is removed, the Cu component struck by Ar ions adheres to the via sidewall, and Cu diffuses in the insulating film at a later process temperature, and between the wirings. Leakage current increases, causing deterioration of wiring performance.
Further, Ar ions damage the low dielectric constant film, resulting in an increase in inter-wiring capacitance and film shrinkage.
これを解決するために、水素もしくはアンモニアガスを含むガスをプラズマ励起させてCu表面の残渣物を還元除去する方法が考えられたが、特に、層間膜にLow−k材料を用いた場合においては、このプラズマ処理により、膜がダメージを受け、配線溝ならびにビア側壁の形状がボウイングするため、後のCu埋設が困難となり、配線ならびに配線同士を繋ぐビア内部にボイドを形成し、導通不良や配線の信頼性を劣化させてしまう。また、膜がダメージを受けることにより、Low−k膜が変質し、誘電率が上昇してしまう問題がある。 In order to solve this, there has been considered a method of reducing and removing residues on the Cu surface by plasma-exciting a gas containing hydrogen or ammonia gas. In particular, in the case where a low-k material is used for the interlayer film. Because of this plasma treatment, the film is damaged and the shape of the wiring trench and via sidewall bows, making subsequent Cu embedding difficult, forming voids inside the vias that connect the wires and wires, and causing poor conduction and wiring. Will deteriorate the reliability. In addition, when the film is damaged, the low-k film is degenerated and the dielectric constant is increased.
以上説明したように、従来の方法では、配線ならびに配線同士を繋ぐビア内部にボイドを形成し、導通不良や配線の信頼性が乏しく、膜がダメージを受けることにより、Low−k膜が変質し、誘電率が上昇してしまうという問題があった。 As described above, in the conventional method, voids are formed inside the wiring and vias connecting the wirings, the conduction failure and the reliability of the wiring are poor, the film is damaged, and the Low-k film is altered. There was a problem that the dielectric constant would increase.
本発明は上記問題を解決するためになされたもので、空孔を有する低誘電率絶縁膜上にバリアメタルを成膜する前におけるビア底の高抵抗層の除去手段として、プラズマを用いない新規な半導体装置の製造方法を提供することにある。 The present invention has been made to solve the above-described problem, and is a novel technique that does not use plasma as means for removing a high resistance layer at the bottom of a via before forming a barrier metal on a low dielectric constant insulating film having holes. Another object of the present invention is to provide a method for manufacturing a semiconductor device.
本発明は、層間膜に非誘電率の値が3未満の低誘電率膜を用いた金属膜配線を含む半導体装置の製造方法において、
前記金属膜配線と前記層間膜の間に形成されるバリアメタルを成膜する前に、250℃に温調された水素、アンモニア、CO、H 2 S、HCl、SO 2 、ヒドラジンのうち少なくとも1種からなる還元性を有するガスもしくはこの還元性を有するガスを含む混合ガスを供給しながら、前記半導体装置を載置するステージの温度を150℃以上200℃未満として熱還元処理を行うことを特徴とする。
The present invention relates to a method of manufacturing a semiconductor device including a metal film wiring using a low dielectric constant film having a non-dielectric constant of less than 3 as an interlayer film.
Before forming a barrier metal formed between the metal film wiring and the interlayer film, at least one of hydrogen, ammonia, CO, H 2 S, HCl, SO 2 and hydrazine adjusted to 250 ° C. A thermal reduction treatment is performed by setting a temperature of a stage on which the semiconductor device is mounted to 150 ° C. or higher and lower than 200 ° C. while supplying a reducing gas composed of seeds or a mixed gas containing the reducing gas. And
また、本発明の方法において、前記還元処理に用いるガスは、還元性を有するガスと、不活性ガスの混合ガスであって、前記不活性ガスはヘリウム、窒素、ネオン、アルゴン、クリプトン、キセノンのうちのいずれかであることが望ましい。 In the method of the present invention, the gas used for the reduction treatment is a mixed gas of a reducing gas and an inert gas, and the inert gas is helium, nitrogen, neon, argon, krypton, or xenon. One of them is desirable.
さらに、本発明の方法において、前記還元性を有するガスもしくは還元性を有するガスを含む混合ガスの温調を、ガス導入配管を温調することにより行うことが望ましい。 Furthermore, in the method of the present invention, it is desirable to adjust the temperature of the reducing gas or the mixed gas containing the reducing gas by adjusting the temperature of the gas introduction pipe.
本発明において、プラズマを用いないでプレクリーン処理を行うことにより、特に層間膜にLow−k材料を用いた際においても、膜にダメージを与えることが無いために、誘電率の上昇が抑えられる。
また、膜がエッチングされないため、配線溝やビアホールを加工した形状が保たれ、後のバリアメタル・シードCu・めっき成長においても、配線やビア内部にボイド無くCuを埋め込むことが可能となる。
In the present invention, by performing the preclean process without using plasma, even when a low-k material is used for the interlayer film, the film is not damaged, so that the increase in dielectric constant can be suppressed. .
Further, since the film is not etched, the shape obtained by processing the wiring groove and via hole is maintained, and Cu can be embedded in the wiring and via without voids in the subsequent barrier metal / seed Cu / plating growth.
本発明の実施形態につき、実施例を基に、図1及び2を用いて詳細に説明する。 An embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 based on examples.
(実施例1)
まず、PVD装置を用いて、あらかじめ比誘電率の値が2.2のポーラスMSQ膜(低誘電率絶縁膜)102上に溝・ビア加工を施した基板(下地基板)101を、350℃に加熱したヒーターステージ上に載置し、NH3を導入してチャンバー内圧力を666.5Pa(5Torr)に保ち、下層配線103表面の高抵抗層104除去の目的で、120秒間の還元処理を行った。
次に、真空を保持したまま、バリアメタル105として、TaN(例えば10nm)およびTa(例えば15nm)をPVD法にて成膜した。
さらに、真空を保持したまま、電解めっき用シード層106として、Cu(例えば100nm)をPVD法にて成膜を行った。その後、電解めっきによりCuの埋め込み成膜を行い、めっき層107を形成した。
最後に、CMPにより上部の余分なCu層を除去し、平坦化を行った。
(Example 1)
First, using a PVD apparatus, a substrate (underlying substrate) 101 having grooves and vias formed on a porous MSQ film (low dielectric constant insulating film) 102 having a relative dielectric constant of 2.2 in advance is set to 350 ° C. It is placed on a heated heater stage, NH 3 is introduced, the pressure in the chamber is kept at 666.5 Pa (5 Torr), and a reduction process is performed for 120 seconds for the purpose of removing the
Next, while maintaining the vacuum, TaN (for example, 10 nm) and Ta (for example, 15 nm) were formed as the
Furthermore, Cu (for example, 100 nm) was deposited by PVD as the
Finally, the upper excess Cu layer was removed by CMP and planarization was performed.
以上から形成されたCuデュアルダマシン配線の形状を確認したところ、あらかじめ溝・ビア加工した間口の形状を変化させることなく、且つ、高抵抗層の除去が確認できた。
次に、ヒーターステージ温度200℃、250℃、300℃、400℃、450℃についても同様に実験した。形状は、全水準ともに変化が見られなかったものの、温度200℃の場合、処理時間を300秒に延長しても、完全に高抵抗層を除去することができなかった。なお、250℃では処理時間200秒で、400℃では60秒で、450℃では45秒で、それぞれ高抵抗層を完全に除去することができた。
As a result of confirming the shape of the Cu dual damascene wiring formed as described above, it was confirmed that the high resistance layer was removed without changing the shape of the slot / via formed in advance.
Next, a similar experiment was conducted for heater stage temperatures of 200 ° C., 250 ° C., 300 ° C., 400 ° C., and 450 ° C. Although the shape did not change at all levels, when the temperature was 200 ° C., the high resistance layer could not be completely removed even if the treatment time was extended to 300 seconds. The high resistance layer could be completely removed at 250 ° C. with a treatment time of 200 seconds, 400 ° C. with 60 seconds, and 450 ° C. with 45 seconds.
(実施例2)
上記実施例1と同様の実験を、あらかじめ還元性ガスの配管のまわりをスパイラルの電熱線で取り巻き、250℃に温調した還元性ガスをチャンバー内に導入して圧力666.5Pa(5Torr)に保ち還元処理を行った。その結果、前記実施例1において高抵抗層除去の効果が見られなかったヒーターステージ温度200℃においても、100秒で完全に除去することができ、その他の温度、たとえば250℃では60秒で高抵抗層を除去することができ、還元効率が向上した。
(Example 2)
The same experiment as in Example 1 above was conducted by surrounding the reducing gas pipe with a spiral heating wire in advance, and introducing the reducing gas whose temperature was adjusted to 250 ° C. into the chamber to a pressure of 666.5 Pa (5 Torr). A reduction treatment was performed. As a result, even at the heater stage temperature of 200 ° C. where the effect of removing the high resistance layer was not observed in the first embodiment, it can be completely removed in 100 seconds, and at other temperatures, for example, 250 ° C., it can be increased in 60 seconds. The resistance layer could be removed, and the reduction efficiency was improved.
従って、デュアルダマシン配線の形状を変えることなく、且つMSQ膜にダメージを与えることなく、ビア底の高抵抗層を除去するためには、還元性ガスの温調を行わない場合には、ヒーターステージ温度として、250℃≦ヒーターステージ温度≦450℃をもちいることが望ましく、還元性ガスの温調を100℃〜400℃にしてチャンバーに導入した場合のヒーターステージ温度は、さらに低い150℃〜250℃でも十分効果が得られる。配線信頼性向上の観点では、プロセスの低温化が重要であり、還元性ガスの温調を行うことで、ステージ温度が低くても還元効果が得られるという点で、温調を行っての還元処理をおこなうことがより望ましい。 Therefore, in order to remove the high resistance layer at the bottom of the via without changing the shape of the dual damascene wiring and without damaging the MSQ film, the heater stage is used when the temperature of the reducing gas is not adjusted. As the temperature, it is desirable to use 250 ° C. ≦ heater stage temperature ≦ 450 ° C. The heater stage temperature when the temperature of the reducing gas is 100 ° C. to 400 ° C. and introduced into the chamber is 150 ° C. to 250 ° C. A sufficient effect can be obtained even at ℃. From the viewpoint of improving wiring reliability, it is important to lower the temperature of the process. By reducing the temperature of the reducing gas, a reduction effect can be obtained even if the stage temperature is low. It is more desirable to perform processing.
なお、本実施例に用いた熱還元処理チャンバーの構造を図2に示す。まず、チャンバー201には、抵抗加熱方式のステージ202で、温度は500℃までコントロールすることができ、ここにウエハーをおいて、処理を行う。チャンバー内へは、ArとNH3のガスライン203がつながっており、圧力はチャンバー201と排気ライン204の間に取り付けられたボールバルブ205の開閉度を制御することにより、13.33Pa(100mTorr)から2666Pa(20Torr)の範囲で制御が可能である。なお、アイドル時に真空度を保つため、ターボ分子ポンプ206からも排気が可能であるが、処理時には、ゲートバルブ207を閉じて処理を行う。
FIG. 2 shows the structure of the thermal reduction treatment chamber used in this example. First, in the
上述した本実施形態によれば、高信頼なCu−lowK配線を作製することが可能となりULSIデバイスの高集積化に貢献することができる。
According to the above-described embodiment, it is possible to manufacture a highly reliable Cu-lowK wiring, which can contribute to higher integration of ULSI devices.
101 基板(下地基板)
102 ポーラスMSQ(低誘電率絶縁膜)
103 下層配線(金属膜配線)
104 高抵抗層
105 バリアメタル
106 電解めっき用シード層
107 めっき層
201 処理チャンバー
202 ステージ
203 ガスライン
204 排気ライン
205 ボールバルブ
206 ターボ分子ポンプ
207 ゲートバルブ
101 Substrate (underlying substrate)
102 Porous MSQ (Low dielectric constant insulating film)
103 Lower layer wiring (metal film wiring)
104
Claims (3)
前記金属膜配線と前記層間膜の間に形成されるバリアメタルを成膜する前に、250℃に温調された水素、アンモニア、CO、H 2 S、HCl、SO 2 、ヒドラジンのうち少なくとも1種からなる還元性を有するガスもしくはこの還元性を有するガスを含む混合ガスを供給しながら、前記半導体装置を載置するステージの温度を150℃以上200℃未満として熱還元処理を行うことを特徴とする半導体装置の製造方法。 In a method for manufacturing a semiconductor device including a metal film wiring using a low dielectric constant film having a non-dielectric constant of less than 3 as an interlayer film,
Before forming a barrier metal formed between the metal film wiring and the interlayer film, at least one of hydrogen, ammonia, CO, H 2 S, HCl, SO 2 and hydrazine adjusted to 250 ° C. A thermal reduction treatment is performed by setting a temperature of a stage on which the semiconductor device is mounted to 150 ° C. or higher and lower than 200 ° C. while supplying a reducing gas composed of seeds or a mixed gas containing the reducing gas. A method for manufacturing a semiconductor device.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the temperature of the reducing gas or the mixed gas containing the reducing gas is controlled by adjusting the temperature of a gas introduction pipe.
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