JP4281674B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device using copper (Cu) or the like for metal film wiring.

In general, Cu wiring (metal film wiring) having low resistance and high electromigration (EM) resistance is expected as a highly reliable material for highly integrated and miniaturized LSI wiring.
One effective method for producing a Cu wiring that is difficult to finely process is a damascene method in which a Cu film is embedded in a base that has been previously processed with grooves and vias. As a technique for embedding a Cu film using the damascene method, a technique that is currently in practical use is electrolytic plating.

FIG. 3 shows an example of a damascene Cu wiring formation process using electrolytic plating. In this process, first, the base substrate 301 (including the base wiring 302) (FIG. 3-1) that has been previously processed with grooves and vias is annealed at 200 to 350 ° C. in an inert atmosphere (Ar or N ₂ ). To remove moisture adsorbed on the processing surface (side walls and bottom surfaces of grooves and vias).
Next, for the purpose of removing the high-resistance layer 303 (mainly copper oxide) formed on the lower wiring surface of the base substrate 301 (including the base wiring 102), the ionized Ar is drawn with a substrate bias and physically removed. (Fig. 3-2). Next, after forming a barrier metal 304 (TaN, TiN, WN, etc.), Cu is formed as a seed layer 305 for electrolytic plating (FIG. 3-3).
Further, Cu-embedded film formation is performed by electrolytic plating to form a plating layer 306 (FIG. 3-4).
Finally, the excess Cu layer and barrier metal at the top are removed by CMP and planarization is performed (FIGS. 3-5). Cu wiring is formed through the above steps.

  In this way, the Cu film is buried by electrolytic plating on the ground / grooved base in advance, but in future devices, the insulating film will lower the dielectric constant, especially the dielectric constant. Therefore, use of a low dielectric constant film having pores has been studied.

Japanese Patent Laid-Open No. 11-16912

For example, when a barrier metal is formed on a low dielectric constant insulating film, particularly a low dielectric constant insulating film having holes, as shown in the above-mentioned patent document, the high resistance layer formed on the lower wiring surface is formed of Ar ions. If it is physically removed, the gap portion that has been previously processed with grooves and vias is struck and spread by Ar ions (FIG. 3-2), and there is a problem that adjacent wirings are short-circuited. Further, when the high resistance layer at the bottom of the via is removed, the Cu component struck by Ar ions adheres to the via sidewall, and Cu diffuses in the insulating film at a later process temperature, and between the wirings. Leakage current increases, causing deterioration of wiring performance.
Further, Ar ions damage the low dielectric constant film, resulting in an increase in inter-wiring capacitance and film shrinkage.

  In order to solve this, there has been considered a method of reducing and removing residues on the Cu surface by plasma-exciting a gas containing hydrogen or ammonia gas. In particular, in the case where a low-k material is used for the interlayer film. Because of this plasma treatment, the film is damaged and the shape of the wiring trench and via sidewall bows, making subsequent Cu embedding difficult, forming voids inside the vias that connect the wires and wires, and causing poor conduction and wiring. Will deteriorate the reliability. In addition, when the film is damaged, the low-k film is degenerated and the dielectric constant is increased.

  As described above, in the conventional method, voids are formed inside the wiring and vias connecting the wirings, the conduction failure and the reliability of the wiring are poor, the film is damaged, and the Low-k film is altered. There was a problem that the dielectric constant would increase.

  The present invention has been made to solve the above-described problem, and is a novel technique that does not use plasma as means for removing a high resistance layer at the bottom of a via before forming a barrier metal on a low dielectric constant insulating film having holes. Another object of the present invention is to provide a method for manufacturing a semiconductor device.

The present invention relates to a method of manufacturing a semiconductor device including a metal film wiring using a low dielectric constant film having a non-dielectric constant of less than 3 as an interlayer film.
Before forming a barrier metal formed between the metal film wiring and the interlayer film, at least one of hydrogen, ammonia, CO, H ₂ S, HCl, SO ₂ and hydrazine adjusted to 250 ° C. A thermal reduction treatment is performed by setting a temperature of a stage on which the semiconductor device is mounted to 150 ° C. or higher and lower than 200 ° C. while supplying a reducing gas composed of seeds or a mixed gas containing the reducing gas. And

  In the method of the present invention, the gas used for the reduction treatment is a mixed gas of a reducing gas and an inert gas, and the inert gas is helium, nitrogen, neon, argon, krypton, or xenon. One of them is desirable.

  Furthermore, in the method of the present invention, it is desirable to adjust the temperature of the reducing gas or the mixed gas containing the reducing gas by adjusting the temperature of the gas introduction pipe.

In the present invention, by performing the preclean process without using plasma, even when a low-k material is used for the interlayer film, the film is not damaged, so that the increase in dielectric constant can be suppressed. .
Further, since the film is not etched, the shape obtained by processing the wiring groove and via hole is maintained, and Cu can be embedded in the wiring and via without voids in the subsequent barrier metal / seed Cu / plating growth.

  An embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 based on examples.

(Example 1)
First, using a PVD apparatus, a substrate (underlying substrate) 101 having grooves and vias formed on a porous MSQ film (low dielectric constant insulating film) 102 having a relative dielectric constant of 2.2 in advance is set to 350 ° C. It is placed on a heated heater stage, NH ₃ is introduced, the pressure in the chamber is kept at 666.5 Pa (5 Torr), and a reduction process is performed for 120 seconds for the purpose of removing the high resistance layer 104 on the surface of the lower layer wiring 103. It was.
Next, while maintaining the vacuum, TaN (for example, 10 nm) and Ta (for example, 15 nm) were formed as the barrier metal 105 by the PVD method.
Furthermore, Cu (for example, 100 nm) was deposited by PVD as the electroplating seed layer 106 while maintaining the vacuum. Thereafter, Cu-embedded film formation was performed by electrolytic plating to form a plating layer 107.
Finally, the upper excess Cu layer was removed by CMP and planarization was performed.

As a result of confirming the shape of the Cu dual damascene wiring formed as described above, it was confirmed that the high resistance layer was removed without changing the shape of the slot / via formed in advance.
Next, a similar experiment was conducted for heater stage temperatures of 200 ° C., 250 ° C., 300 ° C., 400 ° C., and 450 ° C. Although the shape did not change at all levels, when the temperature was 200 ° C., the high resistance layer could not be completely removed even if the treatment time was extended to 300 seconds. The high resistance layer could be completely removed at 250 ° C. with a treatment time of 200 seconds, 400 ° C. with 60 seconds, and 450 ° C. with 45 seconds.

(Example 2)
The same experiment as in Example 1 above was conducted by surrounding the reducing gas pipe with a spiral heating wire in advance, and introducing the reducing gas whose temperature was adjusted to 250 ° C. into the chamber to a pressure of 666.5 Pa (5 Torr). A reduction treatment was performed. As a result, even at the heater stage temperature of 200 ° C. where the effect of removing the high resistance layer was not observed in the first embodiment, it can be completely removed in 100 seconds, and at other temperatures, for example, 250 ° C., it can be increased in 60 seconds. The resistance layer could be removed, and the reduction efficiency was improved.

  Therefore, in order to remove the high resistance layer at the bottom of the via without changing the shape of the dual damascene wiring and without damaging the MSQ film, the heater stage is used when the temperature of the reducing gas is not adjusted. As the temperature, it is desirable to use 250 ° C. ≦ heater stage temperature ≦ 450 ° C. The heater stage temperature when the temperature of the reducing gas is 100 ° C. to 400 ° C. and introduced into the chamber is 150 ° C. to 250 ° C. A sufficient effect can be obtained even at ℃. From the viewpoint of improving wiring reliability, it is important to lower the temperature of the process. By reducing the temperature of the reducing gas, a reduction effect can be obtained even if the stage temperature is low. It is more desirable to perform processing.

FIG. 2 shows the structure of the thermal reduction treatment chamber used in this example. First, in the chamber 201, the temperature can be controlled up to 500 ° C. by a resistance heating type stage 202, and a wafer is placed here to perform processing. A gas line 203 of Ar and NH ₃ is connected to the inside of the chamber, and the pressure controls the opening / closing degree of a ball valve 205 attached between the chamber 201 and the exhaust line 204, thereby allowing 13.33 Pa (100 mTorr). To 2666 Pa (20 Torr). In order to maintain the degree of vacuum during idling, the turbo molecular pump 206 can also be evacuated, but during processing, the gate valve 207 is closed to perform processing.

According to the above-described embodiment, it is possible to manufacture a highly reliable Cu-lowK wiring, which can contribute to higher integration of ULSI devices.

Process drawing for demonstrating embodiment of this invention The figure which shows the structure of the thermal reduction process chamber used for embodiment of this invention Process diagram for explaining a conventional Cu wiring film forming method by a damascene method

Explanation of symbols

101 Substrate (underlying substrate)
102 Porous MSQ (Low dielectric constant insulating film)
103 Lower layer wiring (metal film wiring)
104 High resistance layer 105 Barrier metal 106 Electrode plating seed layer 107 Plating layer 201 Processing chamber 202 Stage 203 Gas line 204 Exhaust line 205 Ball valve 206 Turbo molecular pump 207 Gate valve

Claims (3)

In a method for manufacturing a semiconductor device including a metal film wiring using a low dielectric constant film having a non-dielectric constant of less than 3 as an interlayer film,
Before forming a barrier metal formed between the metal film wiring and the interlayer film, at least one of hydrogen, ammonia, CO, H ₂ S, HCl, SO ₂ and hydrazine adjusted to 250 ° C. A thermal reduction treatment is performed by setting a temperature of a stage on which the semiconductor device is mounted to 150 ° C. or higher and lower than 200 ° C. while supplying a reducing gas composed of seeds or a mixed gas containing the reducing gas. A method for manufacturing a semiconductor device. The gas used for the reduction treatment is a mixed gas of a reducing gas and an inert gas, and the inert gas is any one of helium, nitrogen, neon, argon, krypton, and xenon. The method of manufacturing a semiconductor device according to claim 1, wherein: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the temperature of the reducing gas or the mixed gas containing the reducing gas is controlled by adjusting the temperature of a gas introduction pipe.

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