CN106531688A - Preparation method for through silicon via - Google Patents
Preparation method for through silicon via Download PDFInfo
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- CN106531688A CN106531688A CN201611085114.6A CN201611085114A CN106531688A CN 106531688 A CN106531688 A CN 106531688A CN 201611085114 A CN201611085114 A CN 201611085114A CN 106531688 A CN106531688 A CN 106531688A
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- metal level
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- hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to the technical field of a semiconductor, particularly to a preparation method for a through silicon via. The preparation method comprises the steps of preparing a dielectric layer which comprises a through hole and has low dielectric constant on the upper surface of a composite structure which is already subjected to a patterning process; forming a metal layer with first thickness by adopting electroplating at a first temperature to fill the through hole and cover the upper surface of the dielectric layer; partially removing the metal layer to enable the metal layer to have second thickness which is less than the first thickness; performing a thermal annealing process on the metal layer by adopting a second temperature which is greater than the first temperature to enable crystal particles in the metal layers to be stable during being heated; partially removing the thermally-annealed metal layer to expose the upper surface of the dielectric layer and the upper surface of the metal layer in the through hole; and depositing a protective layer on the exposed dielectric layer and the upper surface of the metal layer by adopting the second temperature, wherein the formed through silicon via can form the stable metal layer in the through hole of the dielectric layer, so as to avoid formation of a lug boss on the surface of the protective layer in order to form the through silicon via with more excellent performance.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of preparation method of silicon perforation.
Background technology
In existing semiconductor microelectronic field, can usually adopt silicon hole technology in three dimensional integrated circuits to stacking core
Piece is interconnected.As silicon hole technology can make interconnection line of the chip between the density maximum, chip that three-dimensional is stacked
Most short, overall dimensions are minimum, can be effectively realized this 3D chip laminates, produce that structure is more complicated, performance is more powerful, more
Have cost-efficient chip, become most noticeable a kind of technology in current Electronic Encapsulating Technology.
But, the silicon hole that existing silicon hole technology is formed often forms a protective layer (such as in layer on surface of metal
On copper surface), if metal level annealing is not thoroughly, metal level is easy in last part technology be affected to cause crystal grain to become by high temperature
Greatly, so that projection is formed in protective layer, may also cause protective layer and rupture is produced in process of lapping when serious.
The content of the invention
For the problems referred to above, the present invention proposes a kind of preparation method of silicon perforation, including：
Step S1, there is provided one through patterning process semiconductors coupling structure；
Step S2, preparing in the upper surface of the semiconductors coupling structure includes with low-k the one of a through hole
Dielectric layer；
Step S3, adopts one first temperature to electroplate to form the metal level with a first thickness to fill the through hole simultaneously
And cover the upper surface of the dielectric layer；
Step S4, partly removes the metal level so that the metal level has one second less than the first thickness
Thickness；
Step S5, carries out thermal anneal process to the metal level using the second temperature higher than first temperature,
So that the crystal grain in the metal level metal level is by thermally-stabilised；
Step S6, part remove the metal level after thermal annealing, by the upper surface of the dielectric layer and described logical
The upper surface exposure of the metal level in hole；
Step S7, is deposited using upper surface of the second temperature in the dielectric layer and the metal level for exposing
One protective layer.
Above-mentioned preparation method, wherein, the scope of first temperature is between 180 DEG C～220 DEG C.
Above-mentioned preparation method, wherein, the scope of the second temperature is between 380 DEG C～420 DEG C.
Above-mentioned preparation method, wherein, the second temperature is 400 DEG C.
Above-mentioned preparation method, wherein, in step S3, the metal level is removed using cmp part.
Above-mentioned preparation method, wherein, in step S5, the metal level is removed using cmp part.
Above-mentioned preparation method, wherein, prepare to form the metal level using copper metal.
Above-mentioned preparation method, wherein, the persistent period of the plating is between 100s～140s.
Above-mentioned preparation method, wherein, the protective layer is silicon nitride layer.
Above-mentioned preparation method, wherein, the protective layer is formed using chemical vapor deposition method.
Beneficial effect：A kind of preparation method of silicon perforation proposed by the present invention can form stable in the through hole of dielectric layer
Metal level, so as to avoid forming projection in protective layer, with the more excellent silicon perforation of forming properties.
Description of the drawings
Fig. 1 is the schematic flow sheet of the preparation method of silicon perforation in one embodiment of the invention；
Fig. 2～5 are the structural representation that formed in each step for formed in one embodiment of the invention silicon perforation.
Specific embodiment
With reference to the accompanying drawings and examples the present invention is further described.
In a preferred embodiment, as shown in Figure 1, it is proposed that a kind of preparation method of silicon perforation, the silicon for being formed
The structure of perforation be able to can include as shown in Fig. 2～Fig. 5：
Step S1, there is provided one through patterning process semiconductors coupling structure (not showing in accompanying drawing)；
Step S2, prepares Jie with low-k for including a through hole 11 in the upper surface of semiconductors coupling structure
Matter layer 10；
Step S3, adopts one first temperature to electroplate to form the metal level 20 with a first thickness to fill through hole 11 simultaneously
And the upper surface of blanket dielectric layer 10；
Step S4, part remove metal level 20 so that metal level 20 has the second thickness less than first thickness；
Step S5, carries out thermal anneal process to metal level 20 using the second temperature higher than the first temperature so that metal level
Crystal grain in 20 is by thermally-stabilised；
Step S6, part remove the metal level 30 after thermal annealing, by the gold in the upper surface and through hole of dielectric layer 10
The upper surface exposure of category layer 30；
Step S7, deposits a protective layer using upper surface of the second temperature in the dielectric layer 10 and metal level 30 for exposing
40。
Specifically, semiconductors coupling structure can be wafer of the superiors through patterning process, so that the wafer
The superiors, the metal connecting line filled in the dielectric layer at the top of such as wafer can pass through the present invention formed silicon hole and other
Structural conductive connects；In step S3, after part removes metal level 20, metal level 20 should still blanket dielectric layer 10, so as to
Enough ensure that subsequent step is carried out after thermal anneal process to metal level 20, the metal level 30 of formation being capable of blanket dielectric layer 10；Formed
Metal level 30 crystal grain due to being become big and stable by abundant thermal annealing so that the metal level 30 in through hole 11 will not be received
The temperature of last part technology affects.
In a preferred embodiment, the scope of the first temperature can be between 180 DEG C～220 DEG C；It is further preferable that
It can be 200 DEG C.
In a preferred embodiment, the scope of second temperature can be between 380 DEG C～420 DEG C.
In above-described embodiment, it is preferable that second temperature is 400 DEG C.
In a preferred embodiment, in step S3, metal level 20 can be removed using cmp part.
In a preferred embodiment, in step S5, metal level 30 can be removed using cmp part.
In a preferred embodiment, can prepare to form metal level 20 using copper metal.
In a preferred embodiment, the persistent period of plating can be between 100s～140s；It is further preferable that can
Think 120s.
In a preferred embodiment, protective layer 40 can be silicon nitride layer.
In a preferred embodiment, protective layer 40 can be formed using chemical vapor deposition method.
In sum, a kind of preparation method of silicon perforation proposed by the present invention can form stable in the through hole of dielectric layer
Metal level, so as to avoid forming projection in protective layer, with the more excellent silicon perforation of forming properties.
By explanation and accompanying drawing, the exemplary embodiments of the ad hoc structure of specific embodiment are given, based on essence of the invention
God, can also make other conversions.Although foregoing invention proposes existing preferred embodiment, however, these contents are not intended as
Limitation.
For a person skilled in the art, after reading described above, various changes and modifications undoubtedly will be evident that.
Therefore, appending claims should regard whole variations and modifications of the true intention and scope that cover the present invention as.In power
In the range of sharp claim, any and all scope of equal value and content, are all considered as still belonging to the intent and scope of the invention.
Claims (10)
1. a kind of preparation method of silicon perforation, it is characterised in that include：
Step S1, there is provided semiconductor composite construction；
Step S2, prepares the medium with low-k for including a through hole in the upper surface of the semiconductors coupling structure
Layer；
Step S3, adopts one first temperature to electroplate to form the metal level with a first thickness to fill the through hole and cover
Cover the upper surface of the dielectric layer；
Step S4, partly removes the metal level so that the metal level has the second thickness less than the first thickness；
Step S5, carries out thermal anneal process to the metal level using the second temperature higher than first temperature so that
Crystal grain in the metal level is by thermally-stabilised；
Step S6, part remove the metal level after thermal annealing, by the upper surface of the dielectric layer and the through hole
The metal level upper surface exposure；
Step S7, deposits a guarantor using upper surface of the second temperature in the dielectric layer and the metal level for exposing
Sheath.
2. preparation method according to claim 1, it is characterised in that the scope of first temperature is at 180 DEG C～220 DEG C
Between.
3. preparation method according to claim 1, it is characterised in that the scope of the second temperature is at 380 DEG C～420 DEG C
Between.
4. preparation method according to claim 3, it is characterised in that the second temperature is 400 DEG C.
5. preparation method according to claim 1, it is characterised in that in step S3, using cmp portion
Divide and remove the metal level.
6. preparation method according to claim 1, it is characterised in that in step S5, using cmp portion
Divide and remove the second metal layer.
7. preparation method according to claim 1, it is characterised in that prepare to form the metal level using copper metal.
8. preparation method according to claim 1, it is characterised in that the persistent period of the plating 100s～140s it
Between.
9. preparation method according to claim 1, it is characterised in that the protective layer is silicon nitride layer.
10. preparation method according to claim 1, it is characterised in that the guarantor is formed using chemical vapor deposition method
Sheath.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611085114.6A CN106531688A (en) | 2016-11-30 | 2016-11-30 | Preparation method for through silicon via |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611085114.6A CN106531688A (en) | 2016-11-30 | 2016-11-30 | Preparation method for through silicon via |
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| Publication Number | Publication Date |
|---|---|
| CN106531688A true CN106531688A (en) | 2017-03-22 |
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ID=58354434
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611085114.6A Pending CN106531688A (en) | 2016-11-30 | 2016-11-30 | Preparation method for through silicon via |
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| Country | Link |
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| CN (1) | CN106531688A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1428838A (en) * | 2001-12-24 | 2003-07-09 | 矽统科技股份有限公司 | Double-insert process using oxidative wire layer as dielectric barrier |
| JP2006147899A (en) * | 2004-11-22 | 2006-06-08 | Seiko Epson Corp | Process for fabricating semiconductor device |
| CN104143527A (en) * | 2013-05-09 | 2014-11-12 | 中芯国际集成电路制造(上海)有限公司 | Conductive plug and TSV forming method |
-
2016
- 2016-11-30 CN CN201611085114.6A patent/CN106531688A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1428838A (en) * | 2001-12-24 | 2003-07-09 | 矽统科技股份有限公司 | Double-insert process using oxidative wire layer as dielectric barrier |
| JP2006147899A (en) * | 2004-11-22 | 2006-06-08 | Seiko Epson Corp | Process for fabricating semiconductor device |
| CN104143527A (en) * | 2013-05-09 | 2014-11-12 | 中芯国际集成电路制造(上海)有限公司 | Conductive plug and TSV forming method |
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Application publication date: 20170322 |
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| RJ01 | Rejection of invention patent application after publication |