JP2006147922A - Apparatus for fabricating semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a novel apparatus for fabricating a semiconductor device without using plasma as a means for removing a high resistance layer on the bottom of a via before a barrier metal is deposited on a low dielectric constant insulating film having a void. <P>SOLUTION: In the apparatus for fabricating a semiconductor device including a metal film interconnect line 103 employing a low dielectric constant film 102 having a relative dielectric constant of less than 3 as an interlayer film, gas is introduced by regulating the temperature of piping of reducing gas having a chamber when thermal reduction processing is carried out with the reducing gas or mixture gas containing the reducing gas before a barrier metal is deposited between the metal film interconnect line 103 and the interlayer film. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an apparatus for manufacturing a semiconductor device using copper (Cu) or the like for metal film wiring.

In general, Cu wiring (metal film wiring) having low resistance and high electromigration (EM) resistance is expected as a highly reliable material for highly integrated and miniaturized LSI wiring.
One effective method for producing a Cu wiring that is difficult to finely process is a damascene method in which a Cu film is embedded in a base that has been previously processed with grooves and vias. As a technique for embedding a Cu film using the damascene method, a technique that is currently in practical use is electrolytic plating.

FIG. 4 shows an example of a damascene Cu wiring formation process using electrolytic plating. In this process, first, the base substrate 401 (including the base wiring 402) (FIG. 4-1) that has been previously processed with grooves and vias is annealed at 200 to 350 ° C. in an inert atmosphere (Ar or N ₂ ). To remove moisture adsorbed on the processing surface (side walls and bottom surfaces of grooves and vias).
Next, for the purpose of removing the high resistance layer 403 (mainly copper oxide) formed on the lower wiring surface of the base substrate 401 (including the base wiring 402), the ionized Ar is drawn with a substrate bias and physically removed. (Fig. 4-2). Next, after forming a barrier metal 404 (TaN, TiN, WN, etc.), Cu is formed as a seed layer 405 for electrolytic plating (FIG. 4-3).
Further, Cu-embedded film formation is performed by electrolytic plating to form a plating layer 406 (FIG. 4-4).
Finally, the upper Cu layer and the barrier metal are removed by CMP, and planarization is performed (FIGS. 4-5). Cu wiring is formed through the above steps.

  In this way, the Cu film is buried by electrolytic plating on the ground / grooved base in advance, but in future devices, the insulating film will lower the dielectric constant, especially the dielectric constant. Therefore, use of a low dielectric constant film having pores has been studied.

Japanese Patent Laid-Open No. 11-16912

For example, as described above, when a barrier metal is formed on a low dielectric constant insulating film, particularly a low dielectric constant insulating film having vacancies as in the patent document, the high resistance layer formed on the lower wiring surface is formed of Ar ions. If it is physically removed, the gap portion that has been subjected to groove / via processing in advance is spread by being hit by Ar ions (FIG. 4-2), and there is a problem that adjacent wirings are short-circuited. Further, when the high resistance layer at the bottom of the via is removed, the Cu component struck by Ar ions adheres to the via side wall, and Cu diffuses in the insulating film at a later process temperature, and between the wirings. Leakage current increases, causing deterioration of wiring performance.
Further, Ar ions damage the low dielectric constant film, resulting in an increase in inter-wiring capacitance and a film shrinkage problem.

  In order to solve this, there has been considered a method of reducing and removing residues on the Cu surface by plasma-exciting a gas containing hydrogen or ammonia gas. In particular, in the case where a low-k material is used for the interlayer film. Because of this plasma treatment, the film is damaged and the shape of the wiring trench and via sidewall bows, making subsequent Cu embedding difficult, forming voids inside the vias that connect the wires and wires, and causing poor conduction and wiring. Will deteriorate the reliability. In addition, when the film is damaged, the low-k film is degenerated and the dielectric constant is increased.

  As described above, in the conventional method, voids are formed inside the wiring and vias connecting the wirings, the conduction failure and the reliability of the wiring are poor, the film is damaged, and the Low-k film is altered. There was a problem that the dielectric constant would increase.

  The present invention has been made to solve the above-described problem, and a semiconductor that does not use plasma as a means for removing a high resistance layer at the bottom of a via before forming a barrier metal on a low dielectric constant insulating film having holes. An object of the present invention is to provide an apparatus for manufacturing an apparatus, that is, a manufacturing apparatus in which gas piping having a reducing property for gas introduction is temperature-controlled.

  The present invention is an apparatus for manufacturing a semiconductor device including a metal film wiring using a low dielectric constant film having a relative dielectric constant of less than 3 as an interlayer film, and formed between the metal film wiring and the interlayer film Before the barrier metal film is formed, a thermal reduction treatment is performed with a reducing gas or a mixed gas containing a reducing gas, and the temperature of the piping of the reducing gas is controlled by a chamber. In a semiconductor device manufacturing apparatus characterized by introducing gas

  The reducing gas used in the present invention is characterized in that a heated gas is supplied by providing a buffer tank equipped with a heater heating mechanism in a gas line.

  The reducing gas used in the present invention is provided with a spiral gas line portion having a pipe diameter of ¼ inch or less, and a heated mechanism is provided to the portion to supply heated gas. It is characterized by that.

  In the present invention, it is desirable to adjust the temperature of the heated gas in the range of 100 to 400 degrees.

Furthermore, it is desirable that the gas used for the thermal reduction treatment has a reducing action and includes at least one of hydrogen, ammonia, CO, H ₂ S, HCl, SO ₂ , and hydrazine.

  The gas that can be introduced used in the present invention is a mixed gas of a reducing gas and an inert gas, and the inert gas is any one of helium, nitrogen, neon, argon, krypton, and xenon. It is desirable.

In the present invention, by performing the pre-clean treatment without using plasma, even when a low-k material is used for the interlayer film, the film is not damaged, so that an increase in dielectric constant can be suppressed.
Further, since the film is not etched, the processed shape of the wiring groove and via hole is maintained, and Cu can be embedded in the wiring and via without voids in the later barrier metal / seed Cu / plating growth.

Embodiments of the present invention will be described in detail with reference to FIGS. 1 to 3 based on examples.
Example 1
First, using a PVD apparatus, a substrate (underlying substrate) 101 having grooves and vias formed on a porous MSQ film (low dielectric constant insulating film) 102 having a relative dielectric constant of 2.2 in advance is set to 350 ° C. The sample was placed on a heated heater stage, NH3 was introduced to keep the pressure in the chamber at 666.5 Pa (5 Torr), and reduction treatment was performed for 120 seconds for the purpose of removing the high resistance layer 104 on the surface of the lower layer wiring 103. .
Next, while maintaining the vacuum, TaN (for example, 10 nm) and Ta (for example, 15 nm) were formed as the barrier metal 105 by the PVD method.
Furthermore, Cu (for example, 100 nm) was deposited by PVD as the electroplating seed layer 106 while maintaining the vacuum. Thereafter, Cu-embedded film formation was performed by electrolytic plating to form a plating layer 107.
Finally, the upper excess Cu layer was removed by CMP and planarization was performed.

  As a result of confirming the shape of the Cu dual damascene wiring formed as described above, it was confirmed that the high resistance layer was removed without changing the shape of the slot / via formed in advance.

  Next, a similar experiment was conducted for heater stage temperatures of 200 ° C., 250 ° C., 300 ° C., 400 ° C., and 450 ° C. Although the shape did not change at all levels, when the temperature was 200 ° C., the high resistance layer could not be completely removed even if the treatment time was extended to 300 seconds. The high resistance layer could be completely removed at 250 ° C. with a treatment time of 200 seconds, 400 ° C. with 60 seconds, and 450 ° C. with 45 seconds.

(Example 2)
First, a 1/4 inch spiral pipe (301 in FIG. 3) shown in FIG. 3 is connected in the middle of the NH ₃ gas pipe used for the reduction treatment. In the same manner as in Example 1, NH ₃ gas was introduced into the chamber, and the pressure was kept at 666.5 Pa (5 Torr) for reduction treatment.
Then, even at the heater stage temperature of 200 ° C. where the effect of removing the high resistance layer was not observed in the first embodiment, it can be completely removed in 100 seconds, and at other temperatures, for example, 250 ° C., high resistance in 60 seconds. The layer could be removed and the reduction efficiency was improved.

  Therefore, in order to remove the high resistance layer at the bottom of the via without changing the shape of the dual damascene wiring and without damaging the MSQ film, the heater stage temperature is not adjusted when the temperature of the reducing gas is not adjusted. It is desirable to use 250 ° C. ≦ heater stage temperature ≦ 450 ° C. In addition, the heater stage temperature when the temperature of the reducing gas is adjusted to 100 ° C. to 400 ° C. and introduced into the chamber is sufficiently effective even at a lower temperature of 150 ° C. to 250 ° C. From the viewpoint of improving wiring reliability, it is important to lower the temperature of the process. By reducing the temperature of the reducing gas, a reduction effect can be obtained even if the stage temperature is low. It is more desirable to perform processing.

  FIG. 2 shows the structure of the thermal reduction treatment chamber used in this example. First, in the chamber 201, the temperature can be controlled up to 500 ° C. by a resistance heating type stage 202, and a wafer is placed here to perform processing. A gas line 303 of Ar and NH 3 is connected into the chamber, and the pressure is controlled from 13.33 Pa (100 mTorr) by controlling the degree of opening and closing of the ball valve 205 attached between the chamber 301 and the exhaust line 304. Control is possible within the range of 2666 Pa (20 Torr). In order to maintain the degree of vacuum during idling, the turbo molecular pump 206 can also be evacuated, but during processing, the gate valve 207 is closed to perform processing.

  According to this embodiment described above, it is possible to produce a highly reliable Cu-lowK wiring, which can contribute to higher integration of ULSI devices.

Process drawing for demonstrating the Example of this invention The figure which shows the spiral-shaped piping used for the Example of this invention The figure which shows the structure of the thermal reduction process chamber used for the Example of this invention. Process diagram for explaining a conventional Cu wiring film forming method by a damascene method

Explanation of symbols

101 Substrate (underlying substrate)
102 Porous MSQ (Low dielectric constant insulating film)
103 Lower layer wiring (metal film wiring)
104 High resistance layer 105 Barrier metal 106 Electrode plating seed layer 107 Plating layer 201 Processing chamber 202 Stage 203 Gas line 204 Exhaust line 205 Ball valve 206 Turbo molecular pump 207 Gate valve

Claims (6)

  An apparatus for manufacturing a semiconductor device including a metal film wiring using a low dielectric constant film having a relative dielectric constant of less than 3 for an interlayer film, the barrier metal formed between the metal film wiring and the interlayer film Before the film is formed, the reducing gas or the mixed gas containing the reducing gas is subjected to the thermal reduction treatment, and the gas is introduced by adjusting the temperature of the piping of the reducing gas having a chamber. An apparatus for manufacturing a semiconductor device.   2. The apparatus for manufacturing a semiconductor device according to claim 1, wherein the reducing gas is supplied by providing a gas tank provided with a buffer tank having a heater heating mechanism.   The reducing gas is provided with a spiral gas line portion having a pipe diameter of ¼ inch or less and a heating mechanism provided in the portion to supply the heated gas. Item 2. A semiconductor device manufacturing apparatus according to Item 1.   2. The semiconductor device manufacturing apparatus according to claim 1, wherein the temperature of the heated gas is controlled in a range of 100 to 400 degrees. The gas used for the thermal reduction treatment has a reducing action, and includes at least one of hydrogen, ammonia, CO, H ₂ S, HCl, SO ₂ , and hydrazine. 1. A semiconductor device manufacturing apparatus according to 1. The gas that can be introduced is a mixed gas of a reducing gas and an inert gas, and the inert gas is any one of helium, nitrogen, neon, argon, krypton, and xenon. The apparatus for manufacturing a semiconductor device according to claim 1.

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