JP4272606B2 - SRAM device - Google Patents

Description

  The present invention relates to a static random access memory (SRAM) device capable of high-density mounting of memory cells.

  A CMOS SRAM device having a 6-transistor configuration is known. This is a basic circuit having a PMOS load transistor and an NMOS drive transistor constituting an inverter and an NMOS access transistor for connecting the output of the inverter to a bit line, and the input / output of the inverter is cross-coupled to the basic circuit. In this way, two sets of basic circuits coupled to each other are provided.

  The SRAM device described in Japanese Patent Laid-Open No. 9-270468, that is, the first prior art, has a conventional vertical structure having an N well region in the upper half of one memory cell region and a P well region in the lower half. Each set of PMOS load transistors is arranged in the N well region located in the center of the memory cell region, and the first P well region is arranged in the left P well region so that the access can be speeded up and the cell area can be reduced as compared with the type cell structure. A lateral cell structure technique in which one set of NMOS drive transistors and NMOS access transistors are arranged in the right P well region, respectively, is employed. Here, the running direction of the bit line is defined as the vertical direction, and the running direction of the word line is defined as the horizontal direction. Japanese Patent Laid-Open No. 10-178110 discloses a similar technique.

  On the other hand, the SRAM device described in Japanese Patent Application Laid-Open No. 2001-257275, that is, the second prior art, is premised on single-ended read and differential write operations, and in a six-transistor SRAM memory cell, The cell width is reduced by making the gate width of one set of NMOS drive transistors smaller than the gate width of the other set of NMOS drive transistors.

  The cell current flowing from the bit line to the source line in the six-transistor SRAM memory cell is determined by the channel widths of the NMOS drive transistor and the NMOS access transistor. A small cell current means a large amplification delay of the bit line. However, the first conventional technique is based on the premise that the sizes of the constituent transistors are symmetrical between the two sets of basic circuits, and the cell current is increased so as to reduce the bit line amplification delay, thereby further increasing the operation speed. In order to realize this, it is necessary to increase the size of all the six transistors, and there is a problem that leads to a large increase in the cell area. Further, in the second prior art, each set of NMOS access transistors has the same gate width, so that there is a problem that the current drive capability of the NMOS drive transistor having a large gate width cannot be fully utilized. It was.

  It is an object of the present invention to provide a new and improved SRAM device.

In the first SRAM device according to the present invention, the current drive capability of the constituent transistors is asymmetric between the two sets of basic circuits, and the source of the set with the lower current drive capability of the two sets of basic circuits during the read operation. Means for setting the potential level of the line to a potential level higher than that of the other set of source lines is provided. Thereby, while ensuring a large cell current in one set, it is possible to prevent destruction of stored data due to a potential rise due to the cell current during the read operation.

  The second SRAM device according to the present invention is characterized in that the gate oxide film thickness of the constituent transistors is asymmetric between the two sets of basic circuits. Thereby, it is possible to reduce the gate leakage current during standby of the SRAM device while securing a large cell current in one set.

  In the third SRAM device according to the present invention, the bit line connected to one of the two basic circuits is used for writing only, and the other bit line is used for both reading and writing. The current driving capability of at least one transistor of the pair of transistors connected to the bit line is set lower than that of the corresponding transistor of the other set, and each access transistor of one set is set to one transistor during a read operation. Only the transistor is activated, and both transistors are activated during the write operation. As a result, single-ended read and differential write operations can be realized.

In the fourth SRAM device according to the present invention, in each of the two sets of basic circuits, the drive transistor and the access transistor are formed in the same continuous and unfolded rectangular activation region. . As a result, the stress in the activated region is relieved, and the occurrence of defects is prevented in advance.

  In general, according to the present invention, a new and improved SRAM device can be provided.

  FIG. 1 shows a configuration example of an SRAM device according to the present invention. In FIG. 1, MP0 and MP1 are PMOS load transistors, MN0 and MN1 are NMOS drive transistors, and MN2 and MN3 are NMOS access transistors. MP0, MN0, and MN2 constitute a first set of basic circuits. MP0 and MN0 constitute one inverter (left inverter LINV), and MN2 connects the output of this inverter to a write-only bit line (write bit line) WBL. The gate of MN2 is connected to a write-only word line (write word line) WLWT, and the source of MN0 is connected to the first source line Vss1. MP1, MN1 and MN3 constitute a second set of basic circuits. MP1 and MN1 constitute one inverter (right inverter RINV), and the output (intermediate node Vm) of this inverter is connected to a bit line (read bit line) RBL that MN3 reads and writes. The gate of MN3 is connected to a read / write word line (read word line) WLR, and the source of MN1 is connected to a second source line Vss2. The first set of basic circuits and the second set of basic circuits are coupled to each other so that the input and output of both inverters are cross-coupled, and the sources of MP0 and MP1 are commonly connected to the positive power supply line Vcc. Icell in the figure is a cell current flowing from RBL to Vss2 through MN3 and MN1.

  FIG. 2 shows an example of the size and threshold voltage of each transistor in FIG. As shown in FIG. 2, the gate width (channel width) of MN1 and MN3 is twice the gate width (channel width) of the other four transistors. That is, the gate widths of MN1 and MN3 are equal to each other, and the gate width is larger than the gate widths of MN0 and MN2. MN1 and MN3 have a low threshold voltage (0.4V), and the other four transistors have a high threshold voltage (0.5V). In the write operation, the write driver circuit of the peripheral circuit forcibly pulls the bit line connected to the node side where “L” is to be written to the ground level, so that the transistor of the memory cell does not need a large size. Therefore, the first set transistor connected to WBL can be written sufficiently even with a half size of the second set transistor.

  The inversion threshold level of each set of inverters is determined by the ratio of the current drive capability between the load transistor and the drive transistor. According to FIG. 2, the gate width ratio between MP0 and MN0 is 1.0 (= 0.2 μm / 0.2 μm), and the gate width ratio between MP1 and MN1 is 0.5 (= 0.2 μm / 0). .4 μm), and the gate width ratio has a difference of 50%. As a result, the inversion threshold level of the left inverter LINV is 0.3 Vcc, that of the right inverter RINV is 0.15 Vcc, and these inversion threshold levels have a difference of 50%.

  The example of FIG. 2 is characterized in that in order to increase the cell current Icell flowing through MN1 and MN3, the gate widths of these transistors (MN1 and MN3) are set equal to each other and large. However, if the size of both these transistors is increased, the potential of the Vm node when MN3 is turned on during the read operation changes greatly from the “L” level to the “H” level. It is necessary to shift the inversion threshold level of the left inverter LINV to a high level so that the left inverter LINV that receives the input of the left inverter LINV does not inadvertently invert. For this reason, as described above, a 50% difference is made in the channel width ratio between the load transistor and the drive transistor between the two sets of basic circuits, thereby preventing erroneous inversion of the left inverter LINV.

  Further, according to FIG. 2, the following effects can be expected by setting the threshold voltages of the constituent transistors asymmetrically between two sets of basic circuits. That is, among the six transistors, only the second set that requires higher current drive capability is set to a low threshold voltage, and the threshold voltage of the first set is set to a high value, so that all transistors having a low threshold voltage are used. Compared to the case, the cell leakage current can be reduced to half.

  The channel width ratio between the load transistor and the drive transistor may be different by 15% or more between the two sets of basic circuits. Moreover, the inversion threshold level of an inverter should just differ 30% or more between two sets of basic circuits.

  FIG. 3 shows another example of the threshold voltage of each transistor in FIG. As shown in FIG. 3, the threshold voltages of MP0, MN0, and MN2 are each set to 0.5V, and the threshold voltages of MP1, MN1, and MN3 are each set to 0.2V. That is, the right inverter RINV that requires high speed is configured with a transistor that realizes a large drive current by lowering the threshold voltage (at the expense of increased leakage current), and the left inverter LINV that allows low speed has a threshold voltage. The transistor is made up of a transistor having a small leakage current. As a result, it is possible to reduce the leakage current during standby by half compared to the case where all transistors having a low threshold voltage are used.

  As shown in FIG. 4, the thickness of the gate oxide film can be set asymmetrically between the two sets of basic circuits. The leakage current described with reference to FIG. 3 is an off-leakage current between the source and drain of the transistor, but the gate leakage current becomes significant in a miniaturized transistor. Therefore, as shown in FIG. 4, the thicknesses of the gate oxide films MP0, MN0, and MN2 are each set to 2.6 nm, and the thicknesses of the gate oxide films MP1, MN1, and MN3 are each set to 1.6 nm. That is, the right inverter RINV that requires high speed is composed of a transistor that realizes a large drive current by reducing the thickness of the gate oxide film (at the expense of an increase in gate leakage current), and a left inverter that allows low speed. LINV is composed of a transistor having a small gate leakage current by increasing the thickness of the gate oxide film. As a result, the gate leakage current during standby can be reduced by half compared to the case where transistors with all thin gate oxide films are used.

  FIG. 5 shows an example of the layout of the SRAM device of FIG. In FIG. 5, WP0, WP1, and WN0 to WN3 represent gate widths of the respective transistors, and SH0 and SH1 represent shared contacts for realizing cross-coupling of the transistors. The illustrated layout adopts the technique of the horizontal cell structure described above, and the first set and the second set are arranged independently on the left and right sides, and the width is changed with a constant height between the first set and the second set. I am doing so. In the figure, WP represents the width of the area occupied by MP0 and MP1, WNL represents the width of the area occupied by MN0 and MN2, and WNR represents the width of the area occupied by MN1 and MN3. These widths can be determined independently of each other. In WP, WPL represents the width of the region occupied by MP0, and WPR represents the width of the region occupied by MP1. These widths can also be determined independently of each other. Note that a vertical cell structure may be employed to change the channel length of the transistor between the groups.

  FIG. 6 shows another layout example of the SRAM device of FIG. According to FIG. 5, for example, since there is a bulge in the source region of MN1, the activation region in the right P well is bent in an L shape. On the other hand, according to FIG. 6, since MN1 and MN3 are formed in a rectangular activated region having the same channel width and the same continuous and straight long side (no bending), As a result of alleviating the stress in the active region, the occurrence of defects is prevented in advance. The same applies to the activation regions of the left P well and the central N well.

  An example of the read / write operation of the SRAM device of FIG. 1 will be described with reference to FIG. As described above, only WLR is activated at the time of reading, and both WLWT and WLR are simultaneously activated at the time of writing.

  During the read operation, by raising the potential of Vss1 by about 0.2V, even if Vm rises by 0.4V, the first set of drive transistors MN0 whose gates are connected to this Vm node will not turn on. ing.

  When it is desired to write “L” to the node opposite to Vm, writing is performed via the half-size MN2, but basically if the current drive capability of the driver circuit is sufficiently higher than the current drive capability of MP0. , Writing is possible. In this embodiment, in order to realize higher-speed writing on that, the potential of Vss2 is floated by about 0.2V. This configuration enables high-speed writing even when the size is small. Conversely, when “L” is written on the Vm node side, writing is performed via the large-sized MN3, so that high-speed writing is possible without control of Vss2. Of course, if Vss1 is floated by 0.2V, writing can be performed at higher speed.

  FIG. 8 shows that a large cell current Icell can be obtained with the SRAM device of FIG. Basically, the ability to extract the charge of the bit line is determined by the sizes of MN1 and MN3 connected in series. Conventionally, in order to keep the potential of the Vm node as low as about 0.1 V, the channel width of MN3 has to be set smaller than the channel width of MN1. In terms of layout, MN3 is laid out narrower than the gate width of MN1, and a wide portion and a narrow portion of the gate are generated in the P well region, and a useless space is created in the narrow portion. However, according to the present embodiment, since Vm can be allowed to 0.4V, it is possible to increase the gate width of MN3 by using a wasted space that has been made conventionally (see FIG. 5). If WN1 = WN3 is realized in this way, a cell current of 160 μA can be realized. This is more than three times that of the conventional cell current of 50 μA. This is very effective when the cell current needs to be increased even if the sizes of MN3 and MN1 are made as close as possible, or rather MN3 is increased.

  As described above, according to the SRAM device of FIG. 1, quantitatively speaking, the cell area can be reduced to 80% of the conventional value, the cell leakage current can be reduced to half of the conventional value, and the cell current can be more than three times the conventional value. can get.

  Note that the gate width of MP1 in FIG. 1 can be increased to the same size as the gate widths of MN1 and MN3. As a result, the size ratio of the three transistors is the same between the first set and the second set. FIG. 9 shows the relationship between the input and output voltages of each set of inverters in this case. According to FIG. 9, it can be seen that a sufficiently large butterfly opening area (a rectangular area indicated by a broken line in the figure) can be secured. In terms of direct current, the same is true even if the transistor size ratio differs four times between the first and second sets.

It is a circuit diagram which shows the structural example of the SRAM apparatus based on this invention. It is a figure which shows an example of the size and threshold voltage of each transistor in FIG. It is a figure which shows the other example of the threshold voltage of each transistor in FIG. It is a figure which shows the example of the gate oxide film thickness of each transistor in FIG. FIG. 2 is a plan view showing an example of a layout of the SRAM device of FIG. 1. FIG. 7 is a plan view showing another example of the layout of the SRAM device of FIG. 1. FIG. 3 is a diagram for explaining an example of read / write operations of the SRAM device of FIG. 1. FIG. 2 is a diagram showing that a large cell current can be obtained with the SRAM device of FIG. 1. FIG. 3 is a diagram illustrating a relationship between input / output voltages of inverters in each group when the size ratio of three transistors is the same between the first group and the second group of inverters in the SRAM device of FIG. 1;

Explanation of symbols

Icell Cell current LINV Left inverter MN0, MN1 Drive transistor MN2, MN3 Access transistor MP0, MP1 Load transistor RBL Read bit line RINV Right inverter SH0, SH1 Shared contact Vcc Positive power supply line Vm Intermediate node voltage Vss1 First source line Vss2 Second Source line WBL Write bit line WLR Read word line WLWT Write word lines WN0 to WN3, WP0, WP1 Transistor gate widths WNL, WNR, WP, WPL, WPR Transistor occupied width

Claims (5)

A basic circuit having a load transistor and a drive transistor constituting an inverter, a source line connected to the drive transistor, and an access transistor for connecting an output of the inverter to a bit line, and the basic circuit as the inverter It has two sets of basic circuits coupled to each other by connecting so that the input and output of
The current drive capability of the constituent transistors is asymmetric between the two sets of basic circuits,
A means for setting the potential level of the source line with the lower current driving capability among the two sets of basic circuits to a higher potential level than that of the other set during the read operation is further provided. A characteristic SRAM device. The SRAM device according to claim 1 ,
The SRAM device, wherein the channel widths of the drive transistor and the access transistor are substantially the same in each of the two sets of basic circuits. The SRAM device according to claim 1,
An SRAM device characterized in that a gate oxide film thickness of a constituent transistor is asymmetric between the two sets of basic circuits. The SRAM device according to claim 1,
Of the two sets of basic circuits, the bit line connected to one set is used exclusively for writing, and the other bit line is used for both reading and writing,
Among the transistors in the set connected to the write-only bit line, the current driving capability of at least one transistor is set lower than the corresponding transistor in the other set,
An SRAM device, wherein each set of access transistors is configured such that only one transistor is activated during a read operation and both transistors are activated during a write operation. The SRAM device according to claim 1,
An SRAM device, wherein in each of the two sets of basic circuits, a drive transistor and an access transistor are formed in the same continuous and unbent rectangular active region.

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