JPH04219696A - Static semiconductor memory - Google Patents

Abstract

PURPOSE:To attain high integration by making the occupancy area of memory cells small with regard to static semiconductor memory. CONSTITUTION:This memory is used in a flip-flop circuit in which asymmetrical inverters having mutually different input/output characteristic constitute the memory cells 10. And, the main memory node 16 of the flip-flop circuit is connected to a single bit line BL via an access transistor 15. In order to differenciate the input/output characteristics, in an impactor which drives a supplemental node 17 which is not connected to the bit line, an element such as TFT13 can be arranged. Through a reduction in the number of bulk MOS transistor elements, a reduction in the memory cell size is attained. Also, by making the inverter asymmetrical, a need to enlarge a memory cell ratio is eliminated, and a low voltage for a power source voltage and the relaxation of the limitation of a cell size is attained.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static semiconductor memory capable of achieving high integration.

0002

2. Description of the Related Art In a static semiconductor memory, a memory cell is composed of a flip-flop circuit and an access transistor. High resistance load type and CMOS type are known as memory cell configurations. In the case of a high-resistance load type cell, a resistor can be stacked on top of a transistor, which is advantageous in improving the degree of integration, but it has the disadvantage of lacking stability in data retention. Furthermore, in the case of a CMOS type cell, data retention stability is superior to that of a high resistance load type cell, but there is a drawback that the area occupied on the substrate is increased. Therefore, while maintaining a high degree of integration, CMOS
In order to take advantage of the characteristics of a type cell, a technology has been proposed in which a cell is constructed using a TFT (thin film transistor) as a load. For example, in a 4MSRAM, a polysilicon thin film transistor is used as a cell.

[0003] In addition, the applicant previously filed the patent application No.
The specification and drawings of No. 168588 describe a static semiconductor memory having a CMOS type cell, in which one bit line is connected to one input/output terminal of a flip-flop circuit via the access transistor. Are listed. Normally, by changing the structure in which a pair of bit lines are connected to the structure in which only one bit line is connected, high integration of memory cells can be achieved without making the bit lines thinner.

0004

[Problems to be Solved by the Invention] However, when achieving higher integration in static semiconductor memory, it is not possible to use only the above-mentioned example using polysilicon thin film transistors or a structure in which only one bit line is connected to a memory cell. However, it has not been possible to achieve a sufficiently high degree of integration, and there is a need to form memory cells with as small an area as possible on a silicon substrate. SUMMARY OF THE INVENTION In view of the above-mentioned technical problems, the present invention aims to provide a static semiconductor memory having memory cells occupying a smaller area.

[0005]

[Means for Solving the Problems] In order to achieve the above object, a static semiconductor memory of the present invention has a memory cell configured by a flip-flop circuit consisting of a pair of inverters having mutually different input/output characteristics and an access transistor. , a single bit line is connected to one data input/output terminal of the flip-flop circuit via the access transistor. As an example of a combination of a pair of inverters having different input/output characteristics, one inverter may be an nMO
In the case where the S transistor is used as the drive transistor, the other inverter can be configured to include a thin film transistor. It is also possible to combine other resistive elements such as polysilicon resistors and other active elements. An output terminal of an inverter having a high driving capability may be connected to the input/output terminal on the side to which the bit line is connected via the access transistor.

[0006]

[Operation] In the static semiconductor memory of the present invention, in addition to the configuration in which only one bit line is connected to each memory cell, which enables high integration, the flip-flop circuit of the memory cell is also connected to a pair of asymmetrical bit lines. Consists of an inverter. Therefore, by taking advantage of this asymmetry, the type and size of transistors constituting each inverter can be selected so as to achieve reduction in cell size. For example, instead of a normal MOS transistor, a thin film transistor may be used in the inverter on the side that does not drive the load. As a result, the present invention achieves even higher integration.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described with reference to the drawings. [First Embodiment] This embodiment is an example of a static semiconductor memory in which a plurality of memory cells are arranged to form a flip-flop circuit from a pair of asymmetrical inverters, and one inverter of the flip-flop circuit is equipped with a thin film transistor. This is an example using . First, the circuit configuration of the memory cell is shown in FIG. As shown in FIG. 1, the memory cell 10 includes an nMOS transistor 11 and a resistor 12.
One inverter is formed using a p-type channel TFT 13, which is a polysilicon thin film transistor, and a resistor 1.
4 forms the other inverter. The source of the nMOS transistor 11 of one inverter is grounded, and its drain is connected to one terminal of the resistor 12. The other terminal of the resistor 12 is supplied with the power supply voltage Vcc. The source of the p-type channel TFT 13 of the other inverter is supplied with the power supply voltage Vcc, and its drain is connected to one terminal of the resistor 14. A ground voltage is applied to the other terminal of the resistor 14. The gate of the nMOS transistor 11 is connected to the drain of a p-type channel TFT 13 to which one terminal of a resistor 14 is connected. The gate of the p-type channel TFT 13 is connected to the drain of the nMOS transistor 11 to which one terminal of the resistor 12 is connected. This TFT1
nMOS transistor 11 in which the gates of 3 and 3 are connected
The drain of the memory cell functions as the main storage node 16 of the memory cell. This main storage node 16 is connected to the bit line BL via an access transistor (word transistor) 15 made of an nMOS transistor. The drain of the p-type channel TFT 13 functions as an auxiliary storage node 17, but unlike a normal memory, it is not connected to a bit line. Only one bit line BL is arranged for each memory cell column. The gate of access transistor 15 is connected to word line WL for row selection.

Next, the operation of the asymmetric memory cell of this embodiment will be explained. The characteristic point behind this is that since the memory cell 10 of this embodiment is connected only to a single bit line, the side that drives the load such as the bit line, that is, the side that drives the main memory node 16, The inverter has a high driving capacity, and the inverter that simply drives only the auxiliary storage node 17 has a low driving capacity and operates asymmetrically. In the following, three cases will be explained in order: reading, data holding, and writing.

First, during reading, the asymmetric memory cell of this embodiment has input/output characteristics according to the butterfly plot shown in FIG. In FIG. 2, a curve fM and a curve fS are drawn, where the curve fM shows the input/output characteristics of the inverter on the nMOS transistor 11 side, and the curve fS shows the input/output characteristics of the inverter consisting of the p-type channel type TFT 13 and the resistor 14. Show characteristics. In FIG. 2, the horizontal axis is the auxiliary memory node 17
The vertical axis is the level Vs of the main memory node 16, and the vertical axis is the level Vm of the main memory node 16.

On the nMOS transistor 11 side, since the access transistor 15 is turned on during reading, the access transistor 15 becomes the main current source of the inverter on the nMOS transistor 11 side. In this sense, the resistance 12 can be ignored during reading. In the curve fM, the level Vs of the auxiliary storage node 17 which is the input level
When the output level Vm of the main memory node 16 is as high as the power supply voltage Vcc, the level Vm of the main memory node 16 is as low as the resistance voltage division of the nMOS transistor 11 with respect to the access transistor 15 and the bit line load, but when the input level Vs is As the output level Vm decreases, the output level Vm increases, and nM
When the input level Vs becomes lower than the threshold voltage Vthd of the OS transistor 11, the level Vm of the main memory node 16 becomes equal to the power supply voltage Vcc−threshold voltage (VthW +Δ
VthW). nMOS transistor 11
is turned off, the level of the main memory node 16 is pulled up, but the voltage of the word line WL is lower than the power supply voltage V.
If cc, the threshold voltage of the access transistor 15 (
The voltage is stabilized in a state where the voltage has dropped from the power supply voltage Vcc by an amount (VthW + ΔVthW ).

Regarding the curve fS, TFT 13 and resistor 1
The level Vm of the main memory node 16, which is the input level of the inverter consisting of
cc-threshold voltage Vthp, the level Vs of the auxiliary storage node 16 (output level of the inverter) is close to the ground level, and the level Vs is close to the threshold voltage Vthp of the p-type channel TFT 13. suddenly transitions to near the power supply voltage Vcc. Then, at a point where the level Vm of the main memory node 16 exceeds the threshold voltage Vthp (to the negative side), the level Vs changes to the power supply voltage Vcc.
It is assumed that the value of

The inverter on the nMOS transistor 11 side needs to drive the bit line BL, which is a relatively heavy load, during reading. For this reason, it is necessary to adopt an nMOS transistor having a high current drive capability and adopt the input/output characteristics shown by the curve fM. However, the inverter consisting of the TFT 13 and the resistor 14 is not connected to the bit line and merely drives the auxiliary memory node 17. Therefore, it is possible to sufficiently operate the inverter using the p-type channel TFT 13, which is a thin film transistor. Furthermore, whether or not the flip-flop circuit operates reliably depends on whether or not there are two stable points in the butterfly plot as shown in FIG. Generally, if there are two stable points in the butterfly plot, it is sufficient that the two inverters have characteristics such that their input/output characteristic curves intersect. Referring to FIG. 2 according to this embodiment, the curve f at point P0
M intersects with the curve fS. Therefore, it can be seen that the flip-flop circuit can reliably perform the read operation, and the stable point P
1, P2 is obtained. For comparison, consider the butterfly plot (not shown) of a conventional flip-flop circuit with a symmetrical inverter. Although the beta ratio, which is the ratio of driving capabilities, is set large, in the flip-flop circuit consisting of the asymmetric inverter of this embodiment, there is no need to set a large ratio, and the logic of the inverter that drives the auxiliary memory node 17 is simply All that is required is to adjust the threshold voltage so that it intersects the characteristic curve of the inverter that drives the main memory node 16. The advantage of not having to take such a large ratio, as will be described later, is that it eliminates the factors that limit the transistor size related to the cell size, which greatly contributes to higher integration.

Next, when data is retained, the access transistor 15 is turned off, and the nMOS transistor 11, p-type channel TFT 13, and resistor 12 are substantially
, 14 only. Since the inverter side consisting of the TFT 13 and the resistor 14 has the same circuit configuration as that at the time of reading described above, the curve fS in FIG. 2 also applies to the time of data retention. However, in the inverter on the nMOS transistor 11 side, the access transistor 15
is off, so the curve fM in Figure 2 does not apply, and
The load mainly consists of a resistor 12 and an nMOS transistor 1.
An input/output characteristic that falls sharply at a threshold voltage Vthd of about 1 is obtained. As a result, the input/output characteristics during data retention of this embodiment are similar to those of a conventional flip-flop consisting of a symmetrical inverter, whereas a portion of the input/output characteristics of a conventional flip-flop consisting of a symmetric inverter
It can be considered that the curve fS is substituted on the inverter side of No. 13, and it can be considered that the circuit operates almost in the same way as a conventional symmetrical circuit only when this data is held.

Finally, at the time of writing, this embodiment combines inverters with asymmetric input/output characteristics, and further requires writing using a single bit line, which requires a writing technique that is particularly different from the conventional one. That is, in the conventional example using a bit line pair, writing is performed by dropping one bit line to the ground level, but in this embodiment, "1" and "" are written by disrupting the balance of the butterfly plot shown in FIG. 0'' is written. Figures 3 and 4
3A and 4B are diagrams illustrating the write operation of the semiconductor memory of this embodiment. FIG.
3 and 4, the vertical axis is the level Vm of the main memory node 16, and the horizontal axis is the level Vs of the auxiliary memory node 17.

When writing "1", as shown in FIG. 3, the curve fMW1 of the inverter on the nMOS transistor 11 side becomes the curve fSW1 of the inverter on the TFT 13 side.
The curve fMW1 is entirely shifted to the higher level side compared to the curve fM at the time of reading (FIG. 2) without intersecting with the curve fM. As a result, nMOS transistor 1
The inverter on the 1st side has a constant output level Vm of TFT.
TFT13 becomes higher than the threshold voltage Vthp of TFT13.
That is, the level Vs of the auxiliary storage node 17 is
4 to ground level. As a result, nMO
The S transistor 11 is constantly turned off, and the only stable point is the point PW1 on the high level side.

When writing "0", as shown in FIG. 4, the input/output characteristics of the inverter on the TFT 13 side do not change, and the curve fSW0 of the inverter on the TFT 13 side
is the same as the curve fS (FIG. 2). However, in order to avoid crossing this curve fSW0, the output level Vm of the curve fMW0 of the inverter on the nMOS transistor 11 side is set to take a value close to the ground level, regardless of the level Vs of the auxiliary storage node 17. As a result, the p-type channel TFT 13 is constantly turned on, and the stable point PW0 is close to the ground level.

As shown in FIGS. 3 and 4, during writing, the semiconductor memory of this embodiment is operated so as to shift the balance of each characteristic of the asymmetric inverter to perform necessary writing. Specifically, the levels of the bit line BL and word line WL are changed between reading and writing, and the power supply voltage Vcc supplied to each inverter is changed.
may be made different between writing and reading.

The semiconductor memory of this embodiment having the above-described structure does not need to increase the beta ratio (cell ratio) of the drive transistor and the access transistor, so it is possible to improve low voltage operation and the degree of freedom in transistor size. It will be possible. In other words, the minimum operational power supply voltage Vccmin is the threshold voltage Vthd of the drive transistor and the threshold voltage (Vt
It is given from the sum of hw+ΔVthw),
Since there is no need to increase the ratio, it is possible to set the threshold voltage (Vthw+ΔVthw) of the access transistor small. Therefore, the minimum power supply voltage Vccm
in can be made small. Further, by setting the threshold voltage (Vthw+ΔVthw) of the access transistor small, it is not necessary to increase the gate length of the access transistor, and it is not necessary to increase the gate width of the drive transistor. Therefore, it is possible to reduce the size of the memory cell and increase the capacity. Furthermore, in the semiconductor memory of this embodiment, the MOS transistors other than the TFT used in the memory cell are the access transistor 15 and the nMOS transistor 11, and the number of MOS transistors formed on the surface of the semiconductor substrate such as a silicon substrate is 1. Two memory cells are enough. Since the resistors 12, 14 and the TFT 13 may be constructed using a single layer or a multilayer polysilicon layer, the size of the memory cell can be significantly reduced.

[Second Embodiment] This embodiment is a modification of the first embodiment, and has the configuration shown in FIG. As shown in FIG. 5, in the memory cell 20 of the semiconductor memory of this embodiment, one inverter is formed by an nMOS transistor 21 and a resistor 22, and the other inverter is formed by a resistor 23 and an n-type channel TFT 24 which is a polysilicon thin film transistor. is formed. nMOS transistor 21
A ground voltage is supplied to the sources of the and n-channel TFTs 24, respectively. The main memory node 26, which is the drain of the nMOS transistor 21, has one source/drain of the access transistor 25 and an n-channel T
The gate of FT24 is connected, and one end of resistor 22 is also connected. The gate of the nMOS transistor 21 and one end of the resistor 23 are connected to the auxiliary storage node 27 which is the drain of the n-type channel TFT 24 . No access transistor is connected to this auxiliary storage node 27. The other ends of the resistors 22 and 23 are connected to the power supply voltage Vc.
c is supplied. The other source and drain of access transistor 25 are connected to bit line BL used for data transfer. Further, the gate of the access transistor 25 is connected to a word line WL for row selection.

The present embodiment having such a circuit configuration is different from the first embodiment in that it has an inverter using an n-type channel TFT 24 instead of an inverter using a p-type channel TFT. It's different. but,
nMOS transistor 21 on the side that drives the bit line BL
The input/output characteristics of the inverter on the side and the inverter on the n-type channel TFT 24 side are asymmetrical, similar to those shown in FIG. Also in this embodiment, due to the asymmetry, there is no need to increase the ratio between the drive transistor and the access transistor. As a result, it becomes possible to lower the power supply voltage Vcc and reduce the cell size, and since only two bulk MOS transistors are required to be formed on the chip, it becomes possible to significantly reduce the cell size.

[Third Embodiment] This embodiment is a modification of the first embodiment, and has the configuration shown in FIG. 6. As shown in FIG. 6, in the memory cell 30 of the semiconductor memory of this embodiment, one inverter is formed by an nMOS transistor 31 and a resistor 32, and a p-type channel TFT 33 and an n-type channel TFT 34 are both polysilicon thin film transistors. The other inverter is formed of a CMOS inverter consisting of. nMOS transistor 31
A ground voltage is supplied to the sources of the TFT 34 and the n-type channel TFT 34, respectively. The main memory node 36, which is the drain of the nMOS transistor 31, has one source/drain of the access transistor 35 and the TFTs 33, 34.
The gate of the resistor 32 is connected to the resistor 32, and one end of the resistor 32 is also connected to the gate of the resistor 32. A supplementary memory node 37 which is the drain of TFTs 33 and 34
The gate of the nMOS transistor 31 is connected to . A power supply voltage Vcc is supplied to the source of the p-type channel TFT 33 and the other end of the resistor 32. Auxiliary memory node 3
No access transistor is connected to 7. The other source and drain of access transistor 35 are connected to bit line BL used for data transfer, and its gate is connected to word line WL for row selection.

The present embodiment having such a circuit configuration is different from the first embodiment in that a p-type channel TFT is used instead of a resistive load type inverter using a p-type channel TFT.
CMO using FT33 and n-type channel TFT34
Although the second embodiment differs in that it includes an S inverter, the inverter on the nMOS transistor 31 side that drives the bit line BL and the CMOS inverter of the TFT have asymmetrical input/output characteristics as in the first embodiment. Therefore, there is no need to increase the ratio between the drive transistor and the access transistor, making it possible to lower the power supply voltage Vcc and reduce the cell size.Furthermore, the number of bulk MOS transistors to be formed on the chip can be reduced to two. This makes it possible to significantly reduce the cell size.

[Fourth Embodiment] This embodiment is a modification of the first embodiment, and has the configuration shown in FIG. As shown in FIG. 7, in the memory cell 40 of the semiconductor memory of this embodiment, one inverter is formed by an nMOS transistor 41 and a p-type channel TFT 42 which is a polysilicon thin film transistor for load, and a p-type channel TFT 43 is further formed. CM consisting of and n-type channel TFT44
The other inverter is formed by the OS inverter. nMOS transistor 41 and n-type channel TF
A ground voltage is supplied to each source of T44. The main memory node 46, which is the drain of the nMOS transistor 41, is connected to one source and drain of the access transistor 45, the gates of TFTs 43 and 44, and the drain of the TFT 42. TFT43,
The auxiliary memory node 47, which is the drain of 44, has an nMOS
The gates of transistor 41 and TFT 42 are connected. A power supply voltage Vcc is supplied to the sources of the p-type channel TFTs 42, 42. No access transistor is connected to auxiliary storage node 47. The other source and drain of access transistor 45 are connected to bit line BL used for data transfer, and its gate is connected to word line WL for row selection.

In this embodiment with such a circuit configuration, compared to the third embodiment, the resistance element is a p-type channel TFT.
However, the inverter on the nMOS transistor 41 side that drives the bit line BL and the CMOS inverter on the TFT side have asymmetrical input/output characteristics, as in the first embodiment. be done. Therefore,
Since there is no need to increase the ratio between the drive transistor and the access transistor, it is possible to lower the power supply voltage Vcc and reduce the cell size.Furthermore, only two bulk MOS transistors are required to be formed on the chip. , it becomes possible to significantly reduce the cell size.

[Fifth Embodiment] This embodiment is a modification of the first embodiment, and has the configuration shown in FIG. As shown in FIG. 8, in the memory cell 50 of the semiconductor memory of this embodiment, one inverter is formed by an nMOS transistor 51 and a p-type channel TFT 52 which is a polysilicon thin film transistor for load, and an asymmetric input to this inverter is formed. The inverter having output characteristics is composed of a p-type channel TFT 53 and a resistor 54, as in the first embodiment. The main memory node 56, which is the drain of the nMOS transistor 51 whose source is supplied with the ground voltage, is connected to one source/drain of the access transistor 55 and T
The gate of FT53 is connected, and the drain of TFT52 is also connected. A power supply voltage Vcc is supplied to the sources of the load TFTs 52 and 53. TFT5 for that load
The gates of the nMOS transistor 51 and the TFT 52 are connected to the auxiliary storage node 57, which is the drain of the transistor 3, and one end of the resistor 54 is also connected thereto. This supplementary memory node 5
No access transistor is connected to the resistor 54.
Ground voltage is supplied to the other end. The other source and drain of access transistor 55 are connected to bit line BL used for data transfer, and its gate is connected to word line WL for row selection.

The present embodiment with such a circuit configuration is different from the first embodiment in that the load resistance element is replaced with a p-type channel TFT 52, and the bit line BL is similarly driven. The input/output characteristics of the inverter on the nMOS transistor 51 side and the CMOS inverter on the TFT 53 and resistor 54 side are asymmetric. Therefore, there is no need to increase the ratio between the drive transistor and the access transistor, making it possible to lower the power supply voltage Vcc and reduce the cell size.Furthermore, the number of bulk MOS transistors to be formed on the chip can be reduced to two. This makes it possible to significantly reduce the cell size.

[Sixth Embodiment] This embodiment is a modification of the first embodiment, and has the configuration shown in FIG. As shown in FIG. 9, the memory cell 60 of the semiconductor memory of this embodiment includes an nMOS transistor 61 and a pMOS transistor 6.
2 forms one inverter, and the inverter with input/output characteristics asymmetrical to this inverter is pMO
It consists of an S transistor 63 and a resistor 64. The main memory node 66, which is the drain of the nMOS transistor 61 whose source is supplied with the ground voltage, has an access transistor 6
5 and the gate of the pMOS transistor 63 are both connected to the pMOS transistor 6.
2 drains are connected. A power supply voltage Vcc is supplied to the sources of the load PMOS transistors 62 and 63. The nMOS transistor 6 is connected to the auxiliary storage node 67 which is the drain of the pMOS transistor 63 for the load.
1 and the gates of the PMOS transistor 62 are connected, and one end of the resistor 64 is also connected. No access transistor is connected to this auxiliary memory node 67, and the resistor 6
A ground voltage is supplied to the other end of 4. The other source and drain of access transistor 65 are connected to bit line BL used for data transfer, and its gate is connected to word line WL for row selection.

The present embodiment with such a circuit configuration has a structure in which no TFT is used compared to the first embodiment, but the input/output characteristics of the pair of inverters are asymmetrical, and the drive transistor and Since there is no need to increase the ratio of the access transistor, it is possible to lower the power supply voltage Vcc and reduce the cell size.

[Seventh Embodiment] This embodiment is a modification of the first embodiment, and has the configuration shown in FIG. Figure 10
As shown in the figure, the memory cell 7 of the semiconductor memory of this embodiment
0, one inverter is formed by an nMOS transistor 71 and a resistor 72, and an inverter having input/output characteristics asymmetrical to this inverter is composed of a pMOS transistor 73 and a resistor 74. The main memory node 76, which is the drain of the nMOS transistor 71 whose source is supplied with the ground voltage, is connected to one source/drain of the access transistor 75, the gate of the pMOS transistor 73, and one end of the resistor 72. . The source of the load PMOS transistor 73 and the other end of the resistor 72 are supplied with the power supply voltage Vcc. p for that load
A supplementary memory node 77, which is the drain of the MOS transistor 73, is connected to the gate of the nMOS transistor 71 and to one end of a resistor 74. No access transistor is connected to this auxiliary storage node 77, and the ground voltage is supplied to the other end of the resistor 74. The other source and drain of access transistor 75 are connected to bit line BL used for data transfer, and its gate is connected to word line WL for row selection.

Similar to the sixth embodiment, this embodiment of the circuit configuration has a structure in which no TFT is used, but the input/output characteristics of the pair of inverters are asymmetric,
Since it is not necessary to increase the ratio between the drive transistor and the access transistor, it is possible to lower the power supply voltage Vcc and reduce the cell size.

[0031]

Effects of the Invention As described above, in the static semiconductor memory of the present invention, only one bit line is connected to each memory cell, which enables high integration, and the flip-flop circuit of the memory cell has an input Inverters with different output characteristics are used. Therefore, it is not necessary to increase the ratio of the drive transistor and the access transistor as in the conventional example, so it is possible to lower the power supply voltage Vcc and reduce the cell size.Furthermore, it is possible to obtain an inverter with different input/output characteristics. When thin film transistors are used as a structure, the number of bulk MOS transistors to be formed on a chip can also be reduced, making it possible to significantly reduce the cell size.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a memory cell of a first embodiment of a static semiconductor memory of the present invention.

FIG. 2 is a diagram showing the input/output characteristics of each inverter forming the flip-flop circuit during reading of the memory cell of the first embodiment.

FIG. 3 is a diagram showing the input/output characteristics of each inverter of the flip-flop circuit when writing "1" into the memory cell of the first embodiment.

FIG. 4 is a diagram showing the input/output characteristics of each inverter of the flip-flop circuit when writing "0" into the memory cell of the first embodiment.

FIG. 5 is a circuit diagram of a memory cell of a second embodiment of the static semiconductor memory of the present invention.

FIG. 6 is a circuit diagram of a memory cell of a third embodiment of the static semiconductor memory of the present invention.

FIG. 7 is a circuit diagram of a memory cell of a fourth embodiment of the static semiconductor memory of the present invention.

FIG. 8 is a circuit diagram of a memory cell of a fifth embodiment of the static semiconductor memory of the present invention.

FIG. 9 is a circuit diagram of a memory cell of a sixth embodiment of the static semiconductor memory of the present invention.

FIG. 10: Seventh static semiconductor memory of the present invention.
FIG. 2 is a circuit diagram of a memory cell according to an embodiment of the present invention.

[Explanation of symbols]

11, 21, 31, 41, 51, 61, 71...nMOS
Transistors 12, 14, 22, 23, 32, 54, 64, 72, 7
4... Resistors 13, 33, 42, 43, 52, 53... P-type channel TFT 24, 34, 44... N-type channel TFT 15, 25
, 35, 45, 55, 65, 75... Access transistor 16, 26, 36, 46, 56, 66, 76... Main memory node 17, 27, 37, 47, 57, 67, 77... Auxiliary memory node

Claims (1)

[Claims] 1. A memory cell is constituted by a flip-flop circuit consisting of a pair of inverters having different input/output characteristics, and an access transistor, and one data input/output terminal of the flip-flop circuit is connected to one data input/output terminal of the flip-flop circuit via the access transistor. A static semiconductor memory characterized by connected bit lines.