JP4268436B2 - Substrate foreign matter inspection apparatus and display panel manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a substrate foreign matter inspection apparatus and a display panel manufacturing method, and more particularly, inspecting a foreign body inspection of a glass substrate such as an LCD (liquid crystal display device) or a PDP (plasma display device) by compressing inspection data. The present invention relates to a glass substrate foreign matter inspection apparatus capable of improving efficiency.
[0002]
[Prior art]
Mask substrates (glass substrates) and silicon wafers used in the manufacture of semiconductor ICs, glass plates used in LCD panels and PDP panels, etc., have defects such as foreign substances adhering to the surface and wrinkles on the surface itself (hereinafter referred to as this In the specification, foreign matter) is detected by a foreign matter inspection device. This keeps the product quality above a certain level.
In particular, in LCD panels and PDP panels, a large number of TFT elements and electrodes are formed as display cells in a matrix on the surface corresponding to the display cells. If there is a defect such as a scratch on the surface of the glass substrate of the material, the formation of TFT elements and electrodes is not good, and therefore the quality of the substrate is deteriorated, so the presence or absence of a defect is inspected by a foreign substance inspection apparatus. The defects existing on the surface (surface defects) are inconvenient for forming TFT elements and electrodes.
Usually, since this type of glass substrate has a rectangular shape, a raster scan is performed in the X direction (substrate longitudinal direction) by a polygon mirror or the like, and the substrate is moved in the Y direction (substrate short direction). Scanning is performed to check the glass substrate for foreign matter.
Patent Documents 1 to 3 and the like can be cited as this type of known foreign matter inspection apparatus.
[0003]
[Patent Document 1]
JP-A-5-052762 [Patent Document 2]
Japanese Patent Laid-Open No. 7-005407 [Patent Document 3]
JP-A-9-258197 [0004]
[Problems to be solved by the invention]
In recent years, both the LCD panel and the PDP panel have been increased in size, and the number of display cells tends to increase. Therefore, when the foreign matter inspection of the substrate is performed for the display cell, the data amount of the detected defect is increasing. Furthermore, the display cell itself is also miniaturized, and there is a demand for inspection in units of cells smaller than actual display cells in high-accuracy foreign matter inspection.
As a result, the inspection efficiency is lowered, the inspection result data is increased in series, and the storage capacity of the inspection data of the data processing apparatus is increased. As a result, the processing load increases, and there is a problem that the inspection processing takes time. For example, a glass substrate of a PDP panel of about 800 mm × 950 mm requires a storage capacity for defect data exceeding 100 Mbytes per glass substrate at present.
The present invention has been made in view of the above, and it is an object of the present invention to provide a foreign substance inspection apparatus for a substrate that can improve inspection efficiency by compressing inspection data.
[0005]
[Means for Solving the Problems]
Particle inspection device for the substrate of the invention for achieving the above object, in the foreign matter inspection device for the substrate to detect for defects in the detection area according to a predetermined detection areas set on the substrate by scanning the board,
A memory having a predetermined storage capacity for sequentially storing the detection values of the detection area with the scanning position of the substrate as a relative address, a coordinate storage means for storing a reference coordinate position serving as a reference for converting the relative address into the scanning position of the substrate, and a reference Coordinate data generating means for generating the coordinate data composed of the reference coordinate position and the bit pattern data by expanding the position of the relative address where the detection value exists with respect to the coordinate position as a bit pattern, and stored in the coordinate data and the memory and receiving the data of the detected values for calculating the coordinates of the scanning position of the substrate for each detection value calculation means and the Bei Eteite, further wherein a relative address, n bytes × m bits (where n is 1 or more Integer, m is an integer of 2 or more), and the reference coordinate position has m corresponding to each relative address on the m-bit side. The pattern corresponds to the relative address on the n-byte side, and the coordinate data generation unit detects the maximum in each block by dividing the relative address on the n-byte side into P blocks (P is an integer of 2 or more). Generates bit pattern data indicating the coordinate position of the relative address on the n-byte side where the value exists, and transfers only the maximum detected value of the block among the detected values stored in the memory. It is drawn .
[0006]
DETAILED DESCRIPTION OF THE INVENTION
Thus, in the present invention, defects are sequentially detected corresponding to the detection areas set on the substrate, and the detection values of the detection areas have relative addresses corresponding to the scanning positions of the detection areas. A reference coordinate position serving as a reference for converting the relative address into the scanning position of the substrate is stored in the memory sequentially.
Then, the inspection data is compressed by developing the relative address position where the detection value exists with the reference coordinate position as a reference to a bit pattern and generating the coordinate data composed of the reference coordinate position and the bit pattern data.
As a result, the coordinate data of each defect detection position need not be generated in correspondence with the defect, so that the amount of processing data to be stored can be reduced and the data transfer amount can also be reduced.
Since the data value of the absolute coordinate corresponding to the scanning position becomes larger as the detection area is made finer, the time for reading and writing the absolute coordinate data corresponding to the scanning position becomes longer. In this respect, the calculation for calculating the original scanning coordinate value from the reference coordinate position and the bit pattern data is a processing routine according to a specific rule, and can be performed in a shorter time than that.
As a result, the inspection data can be compressed, the storage capacity of defective data on the data processing apparatus side can be reduced, and the inspection efficiency can be improved.
[0007]
【Example】
FIG. 1 is a block diagram of a glass substrate inspection apparatus according to an embodiment of a substrate foreign matter inspection apparatus to which the present invention is applied, FIG. 2 is an explanatory diagram of a defect data memory thereof, and FIG. 3 is a data transfer protocol of defect data. It is explanatory drawing of a format.
As shown in FIG. 1, a glass plate surface foreign object detection device 10 includes a light projecting system 2 and a light receiving system 3 on an upper part of a table of a glass substrate 1 which is an inspection object such as an LCD panel substrate or a PDP panel substrate. Is provided. The light projecting system 2 has a laser light source 12a that generates an S-polarized laser beam T _A (s) by a semiconductor laser element and a laser light source 12b that generates a P-polarized laser beam T _B (p).
The light irradiation control circuit 11 alternately drives these laser light sources 12a and 12b, and alternately generates an S-polarized laser beam T _A (s) and a P-polarized laser beam T _B (p), respectively. The light irradiation control circuit 11 is controlled by the data processing device 20, and performs the drive control and the rotation control of the polygon mirror 14 according to this control. The P-polarized laser beam T _B (p) has a power k times (= 2 to 4 times) that of the laser beam T _A (s).
[0008]
The laser beams T _A (s) and T _B (p) are irradiated to the mirror 17 through one collimating lens 13, the polygon mirror 14, and the lens 15, respectively. Each laser beam is collimated, angularly swept and focused in common by these optical systems. As a result, a light spot (inspection area) is formed on the surface (pixel formation surface) of the glass substrate 1, and each scans the surface. The focused laser beam T _B (p) is redirected by the two mirrors 16a and 16b and projected onto the surface of the glass substrate at a projection angle (elevation angle) of about 20 °. The laser beam T _A (s) is redirected by the mirror 17 and projected at a projection angle (elevation angle) of about 70 °, and scans on the same straight line as the laser beam T _A (s) on the surface of the glass substrate 1. . For such scanning, the alternating drive periods of the laser light sources 12 a and 12 b and the rotation speed of the polygon mirror 14 are synchronized by the control of the light irradiation control circuit 11.
[0009]
Scattered light from the foreign matter at the time of each laser beam irradiation obtained by this scanning is received by the light receiving system 3 that forms a light receiving angle (elevation angle) of about 10 ° with respect to the surface of the glass substrate 1. Then, the light is condensed by the optical fiber bundle 31, and the condensed light is given to the photoelectric conversion element 32. Thereby, the received light is converted into an electrical signal. As a result, a detection voltage corresponding to the amount of received light is output from the photoelectric conversion element 32 such as a PMT (photomultiplier). Preamplifier 33 the detected voltage as a detection voltage R _B and the detection voltage R _A in accordance with the timing of the drive control of the laser light source of the light irradiation control circuit 11, an amplifier 34 for generating a detection signal to remove noise according to the threshold Vth The A / D conversion circuit (A / D) 4 performs sampling. The sample timing of A / D 4 is performed corresponding to the detection area (detection cell) set on the glass substrate 1 upon receiving the clock CLK from the clock generation circuit 9, and is similar to the light irradiation control circuit 11. It is controlled by the data processor 20.
Here, the S-polarized laser beam T _A (s) and the P-polarized laser beam T _B (p) are alternately generated, but instead of such polarized light, a single laser beam is irradiated. It may be used as In this case, the detection voltage is one.
Since the detected voltage two also respective signal processing when the detection voltage of the one in the case of the R _A and the detection voltage R _B are the same, the following describes the detection voltage as one.
[0010]
The detected voltage value converted by the A / D 4 corresponding to each laser beam irradiation is stored in the defect data memory 5 in accordance with the clock CLK.
The defective data memory 5 has a two-dimensional relative address storage position corresponding to the scanning position, and receives the clock CLK from the clock generation circuit 9.
As shown in FIG. 2, the relative address has a relative x coordinate of 16 bits (= 2 bytes) × relative y coordinate of 5 bits (5 columns), and the detection value of each detection area is stored at each address position by these address designations. To do. The storage of these address positions is relative to the scanning position of the glass substrate 1 and corresponds to each block obtained by dividing the glass substrate 1 into blocks corresponding to the scanning areas.
The defective data memory 5 is composed of memories 5a and 5b having a two-bank structure, where a memory having a storage capacity corresponding to each block and accessed by the two-dimensional relative address is one bank.
When defective data (detected value) is stored up to the last address of one of the memories 5a and 5b, the memory is switched to the other memory and used alternately. The memory 5 sends a bank switching signal C to the controller 6 and the bit pattern coordinate data generation circuit 8 when the banks of the memories 5a and 5b are switched.
The detection value stored in the defect data memory 5 is read by the controller 6 together with the bit pattern coordinate data and transferred to the data processing device 20.
The data processing device 20 includes an MPU 21, a memory 22, a CRT display 23, an interface, and the like, which are mutually connected by a bus.
The memory 22 stores a defect coordinate calculation program 22a and a foreign matter map display program 22b. The data processing device 20 calculates an absolute coordinate position corresponding to the scanning position of the glass substrate 1 from the bit pattern coordinate data of the defect data memory 5 in correspondence with each detected value, and uses the detected defect as a foreign matter map to the CRT display 23. To display.
[0011]
Here, each bit of A / D 4 is sent to the defective data memory 5 and input to the detected data thinning signal generation circuit 7. When the detected number is 8 or more, the detection data thinning signal generation circuit 7 generates a thinning signal M.
The detection data thinning signal generation circuit 7 generates an OR circuit 7a that receives the output of the A / D 4 in parallel, and when the OR circuit 7a is not all bits “0”, generates a defect detection bit “1” and sets the counter 7b. Increment according to the clock CLK from the clock generation circuit 9. The counter 7 b generates a count-up signal as a thinning signal M when the count value reaches 8, and sends it to the defective data memory 5. The thinning signal M is input to the defective data memory 5 and stored therein as a 1-bit flag. Then, the counter 7b is cleared to “0” in 16 clocks.
The counter 7b is cleared when the detection value for one column of the relative x coordinate in the defect data memory 5 of FIG. 2 is completed, and the process proceeds to the next column count. Further, the value of the counter 7 b is reset by the controller 6 after the controller 6 transfers the data in the defective data memory 5 to the data processing device 20.
The bit pattern coordinate data generation circuit 8 assigns each address position of the relative x coordinate in each relative y coordinate of the bank memories 5a and 5b of the defect data memory 5 as a bit pattern, and uses the position of the relative x coordinate 0 as the most significant bit. A bit pattern indicating a coordinate position with a detected value of the defect is generated.
Further, an absolute XY coordinate position (scanning position) corresponding to the relative address of the head position (0, i) (where i = 0 to 4) of each relative y coordinate is generated, and this and the coordinate data of the bit pattern. Coordinate data consisting of
Further, the bit pattern coordinate data generation circuit 8 generates the coordinate data only when there is a defect detection value in one column of the bank memories 5a and 5b of the defect data memory 5. When there is no detection value, the bit pattern coordinate data generation circuit 8 On the other hand, it operates without transfer data.
[0012]
More specifically, the bit pattern coordinate data generation circuit 8 includes a head coordinate generation circuit 8a, a relative x coordinate pattern generation circuit 8b, and a detection data thinning circuit 8c. The start coordinate generation circuit 8a uses a relative address of 16 × 5 bits in the defect data memory 5 as a relative xy coordinate, each relative y coordinate starts, and an absolute XY coordinate of the defect data at the start position (coordinate of the scanning position of the substrate) ) Is generated. The head coordinate generation circuit 8a generates bit pattern data representing 16 bits of the relative x coordinate position from the head relative coordinate as a bit position of 2-byte data when a defect detection value exists. The detection data thinning circuit 8c divides the 16-bit data of the relative x-coordinate into five blocks when the thinning signal M is generated with reference to the defect data memory 5, and the maximum detection value of each block (See FIG. 2B) is selected as the defect detection value, and the relative x coordinate pattern generation circuit 8b generates a bit pattern corresponding to the selected defect position.
The thinning signal M is stored in the defect data memory 5 with LSB as “1”.
[0013]
Hereinafter, the relationship between the defect data memory 5 and the bit pattern coordinate data generation circuit 8 will be described in detail with reference to FIG.
In FIG. 2, the vertical is the relative y coordinate and the horizontal is the relative x coordinate. LSB is a bit of the thinning signal M. At each coordinate position, a detection value is stored as a numerical value according to the size of the defect.
The leading coordinate generation circuit 8a receives absolute coordinates (X0, Y0) indicating the scanning position corresponding to the relative xy coordinates (0, 0) of the defect data memory 5 from the light irradiation control circuit 11 corresponding to the scanning position. It is latched and stored in the register 81 in response to the memory switching signal C. Then, relative coordinates (0, 0), (0, 1), (0, 2),... (0) from the absolute coordinate value (X0, Y0) of the register 81 to the first to fifth columns in FIG. , 4) are calculated as head coordinate values and stored in the registers 82, respectively.
For example, if the latched absolute coordinate is (X0, Y0) at present, the coordinate of the scanning position is (X0, Y0) at the beginning of the relative coordinate (0, 0). (0,1) is (X0, Y0 + 1), (0,2) is (X0, Y0 + 2)... (0,4) is (X0, Y0 + 4).
[0014]
The relative x coordinate pattern generation circuit 8b has no defect data at the coordinate position where the top of the first column of the defect data memory 5 is (0, 0). Does not generate a pattern. At this time, the controller 6 does not enter the transfer operation.
Since there are five pieces of defect data at the coordinate position where the top of the second column of the defect data memory 5 is (0, 1), the bit pattern of the relative x coordinate is the upper bit as hexadecimal data in units of 4 bits. Data of “ 1010 0000 0100 0100” is generated from the side. Note that the data of the thinning signal M is assigned to the LSB, and the number of defective data is less than 8 in the second column, so this is “0”. In other words, the thinning signal M is not generated at this time. Therefore, there is no detection value selection operation of the detection data thinning circuit 8c, and all the detection values stored in the respective relative addresses are read by the controller 6, and the coordinate data generated together with the read detection values is subjected to data processing. It is transferred to the device 20.
[0015]
At the relative coordinate position where the top of the third column of the defect data memory 5 is (0, 2), since there are nine defect data, a thinning signal M is generated and the LSB of this column of the defect data memory 5 is It is “1”. Therefore, the detection data thinning circuit 8c operates to select the maximum value of each block. Here, the entire pattern data of the relative x-coordinate is composed of 2 bytes. Among them, the coordinate data for the defect is 15 bits, so each block is divided into 5 in units of 3 bits.
Therefore, as shown in FIG. 2B, when the maximum value data of each block is taken from the upper bit side, in the third column, there are four “50”, “125”, “200”, “150”. , 9 pieces of detection data are thinned out to 4 pieces. As a result, the bit pattern of the relative x coordinate generated by the relative x coordinate pattern generation circuit 8b becomes “0010 0001 0001 0101” according to the selected defect data. Note that LSB is “1” because of the thinning signal M.
[0016]
The coordinate data of the defect data generated by the bit pattern coordinate data generation circuit 8 in this way is taken out under the control of the controller 6, and each detection value is read from the defect data memory 5 according to the bit pattern via the controller 6. The Then, it is transferred together with the read detection value to the data processing device 20 in the protocol format of FIG. When the LSB of the bit pattern data received from the bit pattern coordinate data generation circuit 8 is “1”, the controller 6 reads out the detection value corresponding to the received bit pattern.
When the storage of the defective data is completed in one of the two bank memories 5a and 5b of the defective data memory 5, the memory switching signal C is generated and this is received by the controller 6. The first absolute coordinate and bit pattern data generated by the first coordinate generation circuit 8a in order from the first column of the data memory 5 are received from the bit pattern coordinate data generation circuit 8, and one column of the defect data memory 5 read according to this is detected. The value data and the coordinate data are assembled according to the format 60 of FIG. 3 and sequentially transferred to the data processing device 20.
FIG. 3 is an explanatory diagram of the data transfer format 60. The data content flag column 61 is first, then the start bit column 62, the leading X coordinate column 63, the leading Y coordinate 64, and the bit pattern data pt (16 bits). 65, and a detection data number column 66.
In the bit pattern data pt, the LSB of the last 2 bytes is “1” when there is thinning.
[0017]
Here, the transfer data in the second column transferred in the format 60 will be described. Assuming that the start bit is “00 00”, “00 00, 00 00, 00 01, B0 44, B0 44, 0A 4B, 64 55 3C "become.
On the other hand, as shown in FIG. 3C, the transfer data in the third column has “00 00” as the start bit and “00 00, 00 00, 00 02, A3 DD, 21 15, 327 D, C8 96. "become.
The data processor 20 receives this data, and absolute XY coordinates (scanning positions) from which the defect values are obtained from the respective leading coordinate values (X0, Y0) to (X0, Y0 + 4) and the bit pattern data pt. Is calculated by the MPU 21 by executing the defect coordinate calculation program 22a, and the MPU 21 executes the foreign matter map display program 22b and develops it into display data. A map is displayed at the coordinate position on the scan with (corresponding color).
At this time, when there are eight or more defect detection values stored in the relative x coordinate of the defect data memory 5, the detection values are thinned out and limited to the maximum value. However, even in this case, when there are 8 or more, the number is not large, and since it is the maximum value, there is substantially no problem in the case of defect determination or the like. Note that the above eight are examples, and these values are appropriately selected according to the relationship between the inspection object and the defect determination.
[0018]
As described above, in the embodiment, the defective data memory is a memory having a relative address of 2 bytes × 5 bits, which is n bytes × m bits (where n is an integer of 1 or more, m Is an integer of 2 or more).
In the embodiment, the detection value and the data generation of the absolute coordinate position are configured as a hardware circuit as the controller 6, the detection data thinning signal generation circuit 7, and the bit pattern coordinate data generation circuit 8. If the data processor 20 receives the A / D4 signal directly, reads the detected data and the coordinates at that time, stores them as a relative address in the internal memory, and performs data processing, then each of these The circuit can be realized in program processing in the data processing device 20.
[0019]
【The invention's effect】
As described above, according to the present invention, defects are sequentially detected corresponding to the detection areas set on the substrate, and the detection values of the detection areas are relative addresses corresponding to the scanning positions of the detection areas. Are sequentially stored, and a reference coordinate position serving as a reference for converting the relative address into the scanning position of the substrate is stored.
Then, the inspection data is compressed by developing the relative address position where the detection value exists with the reference coordinate position as a reference to a bit pattern and generating the coordinate data composed of the reference coordinate position and the bit pattern data.
As a result, the coordinate data of each defect detection position need not be generated in correspondence with the defect, so that the amount of processing data to be stored can be reduced and the data transfer amount can also be reduced.
As a result, the inspection data can be compressed, the storage capacity of defective data on the data processing apparatus side can be reduced, and the inspection efficiency can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram of a glass substrate inspection apparatus according to an embodiment of a substrate foreign matter inspection apparatus to which the present invention is applied.
FIG. 2 is an explanatory diagram of the defective data memory.
FIG. 3 is an explanatory diagram of a format of a data transfer protocol for defective data.
[Explanation of symbols]
1 ... glass substrate, 2 ... light emitting system, 3 ... light receiving system,
4 ... A / D conversion circuit (A / D), 5 ... defective data memory,
6 ... Controller, 7 ... Detection data thinning signal generation circuit,
8: Bit pattern coordinate data generation circuit,
8a ... Leading coordinate generation circuit,
8b: relative x coordinate pattern generation circuit,
8c: Detection data thinning circuit, 9: Clock generation circuit,
DESCRIPTION OF SYMBOLS 10 ... Surface foreign material detection apparatus, 11 ... Light irradiation control circuit,
12a, 12b ... laser light source,
13 ... Collimating lens,
14 ... polygon mirror, 17 ... mirror,
15 ... Lens, 16a, 16b ... Mirror,
20 ... Data processing device, 22a ... Defect coordinate calculation program, 22b ... Foreign matter map display program.

Claims (6)

In a substrate foreign matter inspection apparatus that scans a substrate and detects defects in the detection region according to a predetermined detection region set on the substrate,
A memory having a predetermined storage capacity for sequentially storing the detection values of the detection area with the scanning position of the substrate as a relative address;
Coordinate storage means for storing a reference coordinate position serving as a reference for converting the relative address into a scanning position of the substrate;
Coordinate data generating means for expanding the position of the relative address where the detection value exists with reference to the reference coordinate position into a bit pattern and generating coordinate data composed of the reference coordinate position and the data of the bit pattern;
A calculation unit that receives the coordinate data and the detection value data stored in the memory and calculates the coordinates of the scanning position of the substrate for each detection value ;
The relative address is a two-dimensional address of n bytes × m bits (where n is an integer of 1 or more and m is an integer of 2 or more), and the reference coordinate position is set to each relative address on the m bit side. M bits in correspondence, the bit pattern corresponds to the relative address on the n-byte side,
The coordinate data generation unit divides the relative address on the n-byte side into P blocks (P is an integer equal to or larger than 2), and calculates the relative address on the n-byte side where the maximum detected value in each block exists. Generate the bit pattern data indicating the coordinate position, transfer only the maximum detection value of the block among the detection values stored in the memory, and thin out the other detection values. apparatus. 2. The apparatus according to claim 1, further comprising data transfer means for transferring the detected value stored in the memory together with the coordinate data to the calculation means, wherein the calculation means is a data processing device, and the substrate is a glass substrate. Foreign material inspection equipment for PCBs. Furthermore, it has a thinning detection means for detecting when the number of detection values stored in the relative address on the n byte side exceeds a predetermined value, and the memory has at least one bit of the relative address on the n byte side Is used as a decimation flag, and a flag is set according to the detection by the detection means, and the coordinate data generation means generates the bit pattern data for the coordinate position where the maximum detection value exists when the decimation flag exists. The foreign matter inspection apparatus for a substrate according to claim 2 . The substrate foreign matter inspection apparatus according to claim 3 , wherein the predetermined value is n × 8/2. The n is 2, m is 1, and P is 5, and the data processing device receives the coordinate data and the detection value from the data transfer means and receives the scan corresponding to each detection value. 4. The substrate foreign matter inspection apparatus according to claim 3 , wherein a position is generated and a defect is displayed as a map. Method of manufacturing a display panel to produce a display panel by inspecting the substrate using the particle inspection apparatus of the substrate according to any one of claims 1 to 5, wherein.

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