JP2903043B2 - Image structure recognition method and circuit configuration used in the method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a real-time (Vide) view of a topologically continuous image structure formed in a plurality of lines.
relates circuit configuration used in the recognition process and method in oechtzeit), at least one identification number consecutive to a pixel group made up of pixels having the same characteristics in a line extending in one row direction in the image structure Each of the pixel groups in the line, which are assigned and located in the next row of the line, have already been assigned to the pixel group in the line immediately before the first contact through at least one pixel along the direction in which the line extends. The same identification number as the assigned identification number is assigned.

[0002]

2. Description of the Related Art Image structure recognition technology is used for automatic inspection of structures such as masks, LCDs, printed circuit boards and semiconductor wafers during manufacturing.

One purpose of image evaluation is to form groups of pixels based on predetermined criteria (characteristics) from an array of pixels, mainly in the form of a matrix or an array, and to perform an evaluation in a compressed form in a subsequent evaluation unit. That is, the same pixel group is processed.

Image processing techniques for classifying pixels within each line to perform data compression and then removing line boundaries are known. In EP 279157 A2, the characteristic is run-length image data (lauflaengenkod
ierten Bilddaten). As a result, a list of run-length image data classified based on the circular area, trapezoidal area, convergence area, and divergence area is formed. At this time, the intermediate space extending in the horizontal direction and the intermediate space extending in the vertical direction are extracted through the filter and are deleted from the recorded data.

Since the defective image is distorted by extracting the intermediate space through the filter and erasing the recorded data from the recorded data, thereby causing an error in the defect class classification of the semiconductor, this process is not suitable for confirming the defect on the semiconductor wafer. Is appropriate.

Examples of more suitable solutions to the problem include:
Based on a characteristic represented by gray density (Grauwerten) or the like, it is possible to label all the continuous regions having the same characteristic in the run-length image data by a uniform method.

[0007] The identification numbers are respectively assigned to groups composed of continuous pixels in each line. As a result, for example, each pixel group starting in the first line extending in the row direction is assigned a continuous identification number. When a pixel group in a second line located directly below the first line does not contact with a pixel group having the same characteristic in the first line via at least one pixel, the same pixel in the second line A new continuous identification number is assigned to each group. If a pixel group in the second line has the same characteristics as a pixel group in the first line that contacts the same pixel group, the pixel group in the second line has the same identification as the pixel group in the first line. A number is assigned.

[0008] Ambiguity or Aequivalenzen occurs when one pixel group has the same characteristics as the same pixel group, but is in contact with a pixel group having a different identification number. Thus, equivalence forms a pair of different identification numbers. Furthermore, while the equivalence starts from different locations, it shows the connections between groups of pixels that flow together.

The equivalence is analyzed by using a search operation rule using a computer, and the execution time of the search operation rule varies based on the shape of an image structure composed of pixel groups. Image structures having a helical shape or a number of intersecting shapes make it impossible to execute the search rules in real time.

[0010]

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the time required for equivalent analysis to perform image processing in real time, regardless of the shape and characteristics of the image structure.

[0011]

SUMMARY OF THE INVENTION The object of the present invention is to
A method for recognizing a topologically continuous image structure formed in a line extending in a row direction, wherein the identification number is continuous with a pixel group composed of at least one pixel having the same characteristic in one line. Respectively, and the pixel group in the line located next to the line is already assigned to the pixel group in the line in the line immediately before the first contact via the at least one pixel along the direction in which the line extends. In the recognition method for assigning the same identification number as the identified identification number, the first storage means stores a plurality of addressed storages.
Position has, each memory location has a specific initial state Rutoto
Storing the monitor data values, or Tsu as an address value in the first storage means, using one arbitrarily selected from the identification number of a pair of pixel groups mutually contact each other and having a different identification number, and before by also using hexene-option has been one of the identification number as a first identification number, if it has an initial state of address specified location by the first identification number is characterized, the pair of identification number A first step of using the other identification number as a data value for the storage location specified by the first identification number, and the storage location specified by the first identification number has a specific initial state. If not, the other identification numbers and data values already stored in the address specified location of the pair of the identification number, stored with a particular initial state A second step of using each as an address value for determining the location, wherein the treatment with an address value of the identification number to be used in the first step, further specific <br/> storage position detection having an initial state until it is, people
It each data value determined for One address value
Re and be used again as an address, further and ignoring the pair of identification number that result in the formation of the same address value in the second step, in the first storage means as well as the address can be specified within the second storage means and concerning the storage position of the third step and, wherein in said first storage means corresponding to the obtained address value obtained from the first step of forming the allocation table, its
If the storage location of the address value has a specific initial state, the same address value is used as the data value and the second
Assigned to a corresponding storage location of the storage means , wherein the storage location is
If no specific initial state, until the storage location with specific initial state is detected, the stored data values used as an address value, said characterized initial state the address value This can be achieved by a recognition method comprising using as a data value for an address value that does not have it.

Further in accordance with the present invention, a plurality of lines extend in a row direction.
That the topologically continuous image structure formed in line with a recognized circuit configuration by using the means for processing the pair of the identification number of different pixel groups, the pixel group at least one pixel And adjacent to each other in the image structure formed in a plurality of lines adjacent to each other, wherein the identification numbers of the pixel groups located in one line are continuously assigned. An identification number already assigned to the pixel group in the line in the row immediately before the pixel group in the line located in the next row of the line is first contacted via at least one pixel along the direction of extension of the line; The same identification number is given, and one input terminal of each of the first multiplexer and the second multiplexer in the circuit configuration is a counter output value of the counter. One input terminal of the second multiplexer is connected to a fixed voltage source, the comparator has an input terminal corresponding to each of the identification number signals, and the input terminal of the comparator is The data input terminals of the first and second registers are connected to the output terminal of a third register, respectively, and the data input terminals of the first and second registers are connected to the output terminals of a third register.
A circuit configuration is provided in which the output terminal of the register is connected to the respective address input terminals of the first storage means and the second storage means, and the input terminal of the third register is connected to the output terminal of the first multiplexer. You.

Further, the data input / output terminal of the first storage means having the same circuit configuration is connected to the counter of the first multiplexer.
Input terminal different from the one input terminal, a data output terminal of the second multiplexer, and a null indicator (Nullindikator).
s) and the first data input terminal of the second storage means. Further, the second storage means has a second address input terminal and a second data output terminal.
Also, a KN signal input terminal, a reset signal input terminal, an EN
The arithmetic and control unit having the K signal output terminal and the ready signal output terminal includes a control input terminal of the first multiplexer, a control input terminal of the second multiplexer, an enable input terminal of the second multiplexer, an enable input terminal of the first storage means, It further has an output terminal connected to the write input terminal of the first storage means and the write input terminal of the second storage means, respectively. Each clock output terminal of the arithmetic and control unit is connected to an input terminal corresponding to each of the first register, the second register, the third register, and the counter. In addition, the plurality of arithmetic and control units
A control output terminal different from the control output terminal is connected to a load input terminal of the counter, an enable input terminal of the first register, and an enable input terminal of the second register. Furthermore, the KN signal input terminal of the arithmetic and control unit and
Another input terminal a fine reset signal input terminal counter end message output terminals of the two output terminals of the comparator
And one output terminal of the null indicator.

[0014]

Since the assignment table including the assignment of all equivalent identification numbers to which addresses are assigned is formed directly from the intermediate code, the equivalence can be evaluated at the moment when the equivalence is recognized.

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. In the circuit configuration shown in FIG. 1, the first multiplexer M1
And one of the input terminals of the second multiplexer M2 is connected to the count value output terminal of the counter Z. The comparator C has input terminals for signals of identification numbers KN1 and KN2. Also, the identification number K of the comparator C
The input terminals of the signals N1 and KN2 are connected to the first register R1.
And the output terminal of the second register R2.

The output terminal of the third register R3 is connected to the respective data input terminals of the first register R1 and the second register R2. The third register R3 is connected to each address input terminal of the first storage means RAM1 and the second storage means RAM2. The input terminal of the third register R3 is connected to the output terminal of the first multiplexer M1.

The first storage means RAM1 is composed of a random access memory, and its data input / output terminal D is another input terminal of the first multiplexer M1, a data output terminal of the second multiplexer M2, and an input of the null indicator N. Terminal and the data input terminal D of the second storage means RAM2. A fixed voltage is supplied to another input terminal of the second multiplexer M2.

The second storage means RAM2 is formed as a random access memory having a dual port and has a second address input terminal A1 for the input signal AL and a second output terminal D1 for the output signal DL. doing.

[0019] KN signal input terminal, a reset signal input terminal, the arithmetic and control unit ST having ENK signal output terminal and ready signal output terminal includes a plurality of control output terminals, each control
The control output terminal is a control input terminal of the first multiplexer M1,
The control input terminal of the second multiplexer M2, the enable input terminal EN of the second multiplexer M2, the first storage means R
AM1 enable input terminal EN, first storage means RAM
1 and a write input terminal W of the second storage means RAM2.

CLK-R1 output terminal, CLK-R2 output terminal, CL
The KR3 output terminal and the CLK-Z output terminal are connected to input terminals corresponding to the first register R1, the second register R2, the third register R3, and the counter Z, respectively. Furthermore, the above-mentioned multiple
A control output terminal different from the number of control output terminals
, The enable input terminal EN of the first register R1, and the enable input terminal EN of the second register R2. Further, each other input terminal of the arithmetic and control unit ST is connected to the end of the counter Z.
Message output terminals U, are respectively connected to one output terminal of the two output terminals of the comparators C, and the null indicator N.

FIG. 2 shows an image structure constituted by pixels and having characteristics represented by different lightness, ie, gray density. FIG. 2 shows an identification number, which is assigned to each pixel group based on a conventional method as a part of print data. And
Each pixel group is composed of at least one pixel.

As a result, two figures each composed of one pixel located on the line 0 extending in the row direction can be represented by the following run-length image data record method. Data record 1 Data record 2 Line number: 0 Line number: 0 Starting column number: 4 Starting column number: 10 Run length: 1 Run length: 1 Identification number: 1 Identification number: 2 Gray density: 10 Gray density: 10 For lines extending below the line 0 in the row direction, the similar data record is combined with the corresponding pixel group, examples of which are the following pixel groups located on line 2. Data record 1 Data record 2 Data record 3 Line number: 2 Line number: 2 Line number: 2 Starting column number: 5 Starting column number: 16 Starting column number: 37 Run length: 8 Run length: 12 Run length: 2 Identification number: 1 Identification number: 4 Identification number: 4 Gray density: 10 Gray density: 30 Gray density: 30 The equivalent is that a pixel group located on one line has the same characteristics as those of the same pixel group. This occurs when a pixel group is connected to a pixel group in a line located directly above it with a different identification number. An example showing the equivalence in FIG. 2 is the relationship between a pixel group with identification number 1 located on line 2 and a pixel group with identification number 3 located on line 1. Another example showing the equivalence is a relationship between a pixel group having the same identification number 1 located on the line 2 and a pixel group having the identification number 2 located on the line 1.

All equivalents obtained from FIG. 2 are summarized in Table 1 based on their identification numbers. The data shown in Table 1 is in a storage form for performing further processing. The effects of the present invention can be expected from columns A and B in Table 1.

[0024]

[Table 1]

The reset signal input to the arithmetic and control unit ST causes the counter Z to output a null address to the first multiplexer M1. At the same time, the arithmetic and control unit ST controls the first multiplexer M1 and the second multiplexer M2 via the control line. With this control, while the count value of the counter Z is output from the output terminal of the first multiplexer M1 and input to the third register R3, a characterized initial state , that is, a null identifier (Nullkennung) indicating a specific initial state. ) Is the first storage means RAM
1 data input terminal. At this time, the counter Z
Is counted from the counter Z to the register R based on the clock signal CLK-Z output from the arithmetic and control unit ST.
3, and the same count value input to the register R3 is input to the first storage means RAM1 as an address.

Next, the arithmetic and control unit ST writes a null identifier in the storage location designated by the address in the first storage means RAM1, and at the same time increments the count value of the counter Z. This process is repeatedly executed in all the storage locations of the first storage means RAM1 until a null identifier is written in the entire first storage means RAM1. After the null identifier is written in all the storage locations of the first storage means RAM1, the state change required for the equivalent processing is executed.

The KN signal output from the storage means (not shown) to the circuit of the present invention indicates that the equivalence has been stored in the storage means. By outputting the ENK signal from the arithmetic and control unit ST, a pair of identification numbers KN1 and KN2 indicating equivalence are input to the corresponding input terminals. The comparator C compares the two identification numbers KN1 and KN2. 2
Equivalence does not occur when the two identification numbers KN1 and KN2 are the same. If the two identification numbers are not the same, a control signal is input to the arithmetic and control unit ST, and after evaluating the control signal, the arithmetic and control unit ST assigns the larger one of the two identification numbers to the first identification number. Multiplexer M1 as number
Output from The processing according to the present invention can also be executed when the smaller one of the two identification numbers is always used as the first identification number. Next, the first identification number is stored in the register R3 by the next clock signal issued from the arithmetic and control unit ST. Since the output of the register R3 at this time is always permitted or released, the first identification number is stored in the first storage means RAM1 and the second storage means R1.
The signal is transmitted to the respective address input terminals of AM2 and to the registers R1 and R2. Next, the arithmetic and control unit ST switches the first storage means RAM1 to the read mode via the control line.

The contents stored at the storage location in the first storage means RAM1 designated by the first identification number which is the larger identification number are output from the data output terminal (D) of the first storage means RAM1. And the multiplexer M1
, The output terminal of the multiplexer M2, the data input terminal of the second storage means RAM2, and the null indicator N. The null indicator N is provided to the arithmetic and control unit ST as the first
A signal indicating whether or not the storage content output from the storage means RAM1 has a null identifier is transmitted. First storage means R
When the storage content output from AM1 includes a null identifier, the arithmetic and control unit ST stops outputting the storage content including the null identifier to the first storage means RAM1 from the data output terminal of the first storage means RAM1. Then, the second identification number (the smaller identification number in this embodiment) is output from the output terminal of the second multiplexer M2. As a result, the first
The second identification number is input to the data input terminal (D) of the storage means RAM1. The value of the smaller identification number is stored in the address-specified storage location in the first storage means RAM1. This storage position is stored in the first storage unit R designated by the larger identification number when the write pulse output from the arithmetic and control unit ST is input to the RAM 1.
Points to a storage location in AM1.

If the storage location in the first storage means RAM1 does not include a null identifier, a search process is started in the first storage means RAM1 based on the following steps. The arithmetic and control unit ST is connected to the multiplexer M1 via the control line.
, The value output from the data output terminal of the first storage means RAM1 is output to the register R3, and the arithmetic and control unit ST transmits the clock signal CLK-R3 to store the same value in the register R3. The arithmetic and control unit ST confirms whether or not the null identifier has been stored in the address-specified storage location based on the method using the null indicator N. This process is repeatedly executed until a signal indicating the storage of the null identifier in the storage location is transmitted from the null indicator N to the arithmetic and control unit ST. Then, the search process is interrupted. The arithmetic and control unit ST receives the clock signal CLK-
By sending R1 to register R1, register R3
Is stored in the register R1. Next, the arithmetic and control unit ST outputs the smaller identification number to the first storage means RAM1 based on the method described above, and the step of searching for a null identifier is started based on the method. Next, the address of the null identifier with the smaller identification number is stored in register R2. The source of the identification number signal is inactivated by the control signal ENK, the signals from the registers R1 and R2 are output to the input terminals of the identification numbers KN1 and KN2, respectively, and the value output from the registers R1 and R2 is the identification number KN1. And KN2.

When all the equivalents that can be identified by the input signal KN are input into the first storage means RAM1, a state change occurs in the circuit so as to form an allocation table immediately. The counter Z is started, and the count value is transmitted to the first storage means RAM1 as a null address. The contents of the storage location designated by the address in the first storage means RAM1 are read by a null display. When a null identifier is stored at the storage location in the first storage means RAM1,
The arithmetic and control unit ST transmits the first storage means R via the control line.
The input of AM1 is deactivated, and a signal is output from its enable output terminal to cause the multiplexer M2 to output a count value corresponding to the storage location. This count value is input into the storage means RAM2 by the write pulse W. Next, the count value of the counter Z is incremented, and the above-described processing is repeatedly executed for all storage locations having a null identifier in the first storage means RAM1. If it is determined that a null identifier is not included in one of the storage locations in the storage means RAM1, the arithmetic and control unit ST transfers the stored content stored in the first storage means RAM1 from the output terminal of the multiplexer M1. The multiplexer M1 is controlled so as to output to the input terminal of the register R3.

The address previously present in the first storage means RAM1 is stored in the register R1 by the signals CLK-R1 and CLK-R3. Further, the first storage means R
The contents stored in AM1 are stored in the register R3 as a new address for the first storage means RAM1.
Is entered in The null indicator N searches the first storage means RAM1 again for the presence of a null identifier. If the null identifier is not included, the storage content of the storage location designated by the address in the first storage means RAM1 is input again to the register R3 as the next address. This process is repeated until a storage location with a null identifier is found.

The address of this storage location in the first storage means RAM1 is input into the register R2 by the control signal CLK-R2. At the same time, the register R1 is released by the arithmetic and control unit ST, and its contents are output to the input terminal of the identification number KN1. And the identification number KN
The content stored in the register R1 input to the input terminal 1 is output to the register R3 by controlling the multiplexer M1. The contents of the register R1 are stored in the arithmetic and control unit S.
The control signal CLK-R3 output from T is stored in the register R3.

Then, when the output of the register R2 is released, the register R is input to the input terminal of the multiplexer M2.
2 is input. And the multiplexer M2
Outputs the content stored in the register R2 from its output terminal. The value output from the multiplexer M2 is stored in the second storage means RAM2 by the write pulse transmitted from the arithmetic and control unit ST to the second storage means RAM2.

Next, the count value is incremented,
The search for a null identifier for the next storage location in the first storage means RAM1 based on the above method is resumed, and this search is performed when all the storage locations of the allocation table are stored in the second storage means RAM2.
It is continued until it is input in. The arithmetic and control unit ST detects from the signal output from the end message output terminal U of the counter Z that all the storage positions of the allocation table have been input into the second storage means RAM2. The arithmetic and control unit ST terminates the arithmetic processing after detecting the state signal U, and transmits a ready signal (READY-Signal) indicating completion of preparation to execute the next processing to the outside via the control line.

As described above, in the image structure recognizing method according to the present invention, since the assignment table including the assignment of all the equivalent identification numbers with addresses is formed directly from the intermediate code, the instant the equivalence is recognized, The same equivalence evaluation can be performed, and the equivalent processing time is reduced compared to the conventional arithmetic processing in which the search operation rule is started only when all the equivalences are completed. The number of equivalent analysis steps according to the invention is the same as the equivalent overlap factor (Verschachtelungstiefe). The number of analysis steps when the same processing is executed by a search operation rule using a computer is the same as all equivalent maximum overlap coefficients.

[0036]

As described in detail above, according to the present invention,
An excellent effect of enabling a real-time image processing by reducing the time required for equivalent analysis without being bound by the shape and characteristics of the image structure.

[Brief description of the drawings]

FIG. 1 is a circuit configuration based on the present invention.

FIG. 2 is an image structure having assignment of identification numbers to pixel groups.

[Explanation of symbols]

M1 first multiplexer, M2 second multiplexer, Z counter, C comparator, KN1, KN2 identification number signal, R1 first register, R2 second register,
R3: third register, RAM1: first storage means, RAM
2 ... second storage means, N ... null display, AL ... input signal,
A1: address input terminal of the second storage means, DL: output signal, D1: output terminal of the second storage means, ST: arithmetic control unit, EN: enable input terminal, W: write input terminal,
U: Counter end message output terminal.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-46760 (JP, A) JP-A-1-292478 (JP, A) JP-A-2-187874 (JP, A) JP-A-1- 245366 (JP, A) JP-A-63-208177 (JP, A) JP-A-63-284685 (JP, A) JP-A-1-156874 (JP, A) JP-A-62-73382 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) G06T 7/00 G06T 1/00

Claims (2)

(57) [Claims] 1. A method for recognizing a topologically continuous image structure formed in a plurality of lines extending in a row direction , comprising:
A continuous identification number is assigned to each pixel group composed of at least one pixel having the same characteristic in one line, and a pixel group in a line located in a line next to the line has a direction in which the line extends. At least one along
In a recognition method for assigning the same identification number to an already assigned identification number to a pixel group in a line in a row immediately before first contacting via one pixel, the first storage means includes a plurality of addressed storages. Has a position
And, each memory location Rutotomoni data value comprises a particular initial state
Stores, and as the address value of the first storage unit, an arbitrarily chosen one identified from identification numbers of a pair of image <br/> containing group mutually contact each other and having a different identification number
Using the number, and by also using one of the identification number pre-hexene-option as a first identification number, if having an initial state in which the address specified location by the first identification number is characterized to the other identification number of the pair of the identification number, the first step to be used as data values for address specified location by the first identification number, the specified address by said first identification number storage Special location
In the case where the storage location having the specific initial state is not provided, the data value already stored in the storage location specified by the other identification number of the pair of identification numbers and the address is stored. Each as an address value to determine
Is a second step using, where treats the address value as an identification number used in the first step, further until a storage location having a specific initial state is detected, one of the add <br/> and be used again each data value determined for less value as address <br/> scan respectively, and ignoring the further pair of identification number that result in the formation of the same address value in the second step, the A third step of forming an allocation table in the second storage means capable of designating an address in the same manner as the first storage means, and wherein the first step corresponds to the address value obtained from the first step .
And regarding the storage location within the storage means, the same address value if the storage location has a particular initial <br/> period state as a data value, assigned to the corresponding storage locations of the second memory means ,
Wherein when the storage location does not have a specific initial state, especially
Until a storage location having a fixed initial state is detected in the first storage means, the first storage means is associated with the address value.
Using the stored data value within the address value of the first storage unit, and does not have the specific initial address value of the first storage unit in the second storage means
Used as the data value corresponding to the address of the storage location
Thereby forming the allocation table . 2. A circuit configuration for recognizing a topologically continuous image structure formed in a plurality of lines extending in a row direction by using means for processing a pair of different identification numbers of a pixel group. , The pixel group has at least one pixel and is adjacent to one another in the image structure formed in a plurality of lines adjacent to each other, wherein the pixel group located in one line identification number is assigned sequentially split, the next of said lines
A group of pixels in a line located in a row immediately before being first contacted via at least one pixel along a direction in which the line extends.
The same identification numbers as those already assigned to the pixel groups in the line in the row are assigned, and one input terminal of each of the first multiplexer (M1) and the second multiplexer (M2) in the circuit configuration is a counter. (Z) is connected to a count value output terminal, one input terminal of the second multiplexer (M2) is connected to a fixed voltage source, and the comparator (C) is connected to an identification number signal (KN1, KN2). And an input terminal of the comparator is connected to an output terminal of a first register (R1) and an output terminal of a second register (R2), respectively, and the first register (R1) and the The data input terminal of the second register (R2) is connected to the output terminal of the third register (R3).
The output terminal of 3) is connected to the respective address input terminals (A) of the first storage means (RAM1) and the second storage means (RAM2), and the input terminal of the third register (R3) is connected to the first multiplexer ( M1), and the data input / output terminal (D) of the first storage means (RAM1) is connected to the counter of the first multiplexer (M1).
An input terminal different from the one input terminal connected to (Z), a data output terminal of the second multiplexer (M2),
A data input terminal of the second storage means (RAM2) including an input terminal of the null indicator (N), an address input terminal (A1) for the input signal (AL) and an output terminal (D1) of the output signal (DL). D), the plurality of control output terminals of the arithmetic and control unit (ST) having a KN signal input terminal, a reset signal input terminal, an ENK signal output terminal, and a ready signal output terminal are connected to the first multiplexer (M1). Control input terminal, second multiplexer (M2)
Control input terminal, the enable input terminal (EN) of the second multiplexer (M2), the enable input terminal (EN) of the first storage means (RAM1), the first storage means (RAM1)
Write input terminal (W) and the second storage means (RAM
2) is connected to the write input terminal (W) of the arithmetic and control unit (ST), and the CLK-R1 clock signal output terminal, the CLK-R2 clock signal output terminal,
The LK-R3 clock signal output terminal and the CLK-Z clock signal output terminal are inputs respectively corresponding to the first register (R1), the second register (R2), the third register (R3), and the counter (Z). And a plurality of control output terminals of the arithmetic and control unit (ST).
The other control output terminals correspond to the load input terminal (L) of the counter (Z), the enable input terminal (EN) of the first register (R1), and the enable input terminal (EN) of the second register (R2). Connected to the KN signal input terminal of the arithmetic and control unit (ST) and
Another input terminal and a reset signal input terminal end message output terminal of the counter (Z) (U), with respect to one output terminal of the two output terminals of the comparator (C), and a null indicator (N) Circuit configuration characterized by being connected to each other.