JP4519272B2 - Pattern inspection apparatus and pattern inspection method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a pattern inspection apparatus and a pattern inspection method for inspecting the quality of a test object such as a printed wiring board having a pattern such as a wiring pattern on its surface. More specifically, the present invention relates to a pattern inspection apparatus and a pattern inspection method that do not require an excessively large amount of memory or logic resources and have pattern recognition flexibility even for an object having a complicated and fine pattern. is there.
[0002]
[Prior art]
The printed circuit board may not be formed correctly according to specifications. Of course, such a printed wiring board is a defective product and must be excluded from the product. For this purpose, printed wiring board products are inspected. In the inspection for this purpose, the figure appearing at the defective part is designated in advance. If the figure is not found in the pattern of the printed wiring board, the printed wiring board is assumed to be good. Of course, if the figure is found in the pattern, the printed wiring board is considered defective.
[0003]
Here, a typical example of a defective part is a short circuit between lines or a disconnection of lines. These are not necessarily certain figures. In other words, there are many variations in the shape of these defective portions. Therefore, figure recognition for pattern inspection must be a method that can cope with variations.
[0004]
One common method for this purpose will be described with reference to FIGS. In this method, the recognition pattern shown in FIG. 19 is used. FIG. 19 shows an example of a recognition pattern for recognizing a short circuit between lines. That is, the alphabetic characters on the left side and the numbers on the upper side in FIG. ² This is a coordinate value for specifying a pixel in the pixel area. The six pixels described as “1” are pixels that require a binarized value of “1” in order to recognize a figure. The three pixels described as “0” are pixels that require a binarized value of “0” in order to recognize a graphic. The blank areas other than these nine are pixel areas that do not affect the recognition of the figure regardless of whether the binarized value is “0” or “1”. The reason for the blank area is to accommodate variations in the shape of the short circuit.
[0005]
FIG. 20 shows an example in which the recognition pattern of FIG. 19 is actually applied to image data. In FIG. 20, the gray pixel indicates the pixel of the pattern portion (binarization value is “1”), and the white pixel indicates the pixel of the portion where the base material is exposed (binarization value is “0”). Show. The pixels described as “1” are all gray, and the pixels described as “0” are all white. That is, all the above conditions are satisfied. For this reason, it is recognized that there is a short circuit between lines at this location in the image data. If even one pixel described as “0” or “1” does not satisfy the above condition, it is not recognized that there is a short circuit at that location.
[0006]
Graphic recognition by such a method is realized by, for example, a logic gate. That is, the multi-input AND of the signal of each pixel described as “1” in FIG. 19 and the inverted signal of each pixel described as “0” in FIG. As a result, the pattern recognition signal is output only when all the above conditions are satisfied. In general, the OR of the recognition pattern of FIG. 19 and its left / right inversion pattern (or rotation pattern every 90 °) is taken. In addition, a look-up table using a high-speed memory can be used instead of the logic gate.
[0007]
An example of a recognition pattern for recognizing a type of defect other than a short circuit is shown in FIG. This is a pattern for recognizing so-called “line thinning” in which the thickness of the wiring is thinner than the specification. The meanings of “0” and “1” are the same as those in FIG. In this recognition pattern, a portion where the line width is 3 pixels or less is recognized. FIG. 23 shows an example in which line thinning is actually recognized.
[0008]
[Problems to be solved by the invention]
However, in recent years, the pattern shape of the printed wiring board has become very complicated and fine. Therefore, a considerable amount of logic resources are required to deal with complicated and fine patterns by the conventional method described above. Otherwise, the flexibility of shape recognition will be reduced, and variations will be insufficient. For this reason, depending on variations, as shown in FIGS. 21 and 24, it may not be possible to recognize that the short circuit or the wire is thin. That is, in the case of FIG. 21, although there is a short circuit, the short circuit cannot be recognized no matter how the image data and the recognition pattern are applied. Further, the case of FIG. 24 is a case where there is a thin line near the bent portion of the line, but it cannot be recognized by the recognition pattern of FIG. Even when a lookup table is used, a large amount of memory resources are required, and thus the same problem occurs.
[0009]
The present invention has been made to solve the above-described problems of the prior art. That is, the subject is a pattern inspection apparatus and a pattern inspection method that do not require an excessively large amount of memory or logic resources and have pattern recognition flexibility even for an object having a complicated and fine pattern. Is to provide.
[0010]
[Means for Solving the Problems]
The pattern inspection apparatus of the present invention made for the purpose of solving this problem is: Obtained by imaging the wiring pattern of the printed wiring board From image signal , Defect location that appears in the defect location Extract the shape, Defective part A basic recognition unit that recognizes the basic part of the shape that does not change due to variations; Defective part A variation recognizing unit for recognizing a variation portion that changes depending on the variation of the shape, and the basic recognizing unit Defect shape Recognize the basic part and the variation recognition part Of the variation part of the defect part shape When one of the variations is recognized, Defective part It recognizes that a shape exists.
[0011]
In the pattern inspection method of the present invention, a basic recognition unit for recognizing a basic part that does not change due to variations among the target shapes and a variation recognition unit for recognizing a variation part that changes with variations among the target shapes are prepared. When the basic recognition unit recognizes the basic portion of the signal and the variation recognition unit recognizes any of the variations, it recognizes that the target shape exists in the image signal.
[0012]
That is, in the present invention, the processing in the basic recognition unit and the processing in the variation recognition unit are performed on the acquired image signal. The basic recognition unit recognizes a basic part that does not change due to variations in the target shape. Therefore, a pattern for recognizing the basic part is generally defined in the basic recognition unit. That is, in order to recognize the basic part, some pixels that should have a specific data value are defined. In general, it is assumed that the basic portion of the target shape is recognized when the data values of these pixels all meet the conditions.
[0013]
The variation recognizing unit recognizes a variation portion that changes depending on the variation in the target shape. That is, it is determined whether or not the region corresponding to the variation portion of the image signal corresponds to one of the target shape variations. When the basic recognition unit recognizes the basic portion of the image signal and the variation recognition unit recognizes any of the variations, it is recognized that the target shape exists in the image signal. If either of the basic recognition unit and the variation recognition unit gives a negative result, it is not recognized that the target shape exists in the image signal. In general, even if the target shape is recognized as described above, further narrowing down by comparison with mask data or the like is performed thereafter.
[0014]
The basic recognition unit in this method does not need to cover the entire target shape. For example, when the target shape is a short circuit, it is sufficient to cover the line shape as a premise and the protruding portion from the line that is the starting point of the short circuit. And the variation recognition part is in charge of the variation part instead of the basic recognition part. As a result, less computer resources are required as compared to the case where a single pattern recognition unit is in charge of everything including variations. In addition, the flexibility to cope with the variety of variations is also excellent.
[0015]
In the present invention, the variation recognition unit includes Of the variation part of the defect part shape Each pattern corresponding to the variation The Memory The pattern recognition signal is output only when the image signal corresponds to one of the stored patterns. It is desirable to provide a lookup table. In particular, when this is configured with one memory and all the variations that can be processed with one memory are stored, high-speed processing is possible.
[0016]
For example, the lookup table may output different values for each pattern corresponding to the variation and other patterns. This is because the output value of the lookup table indicates whether the image signal of the variation part is recognized as a variation of the target shape.
[0017]
Furthermore, as a lookup table, SRAM is used from the viewpoint of high speed and rewriteability. The pattern recognition signal is received only when the input address terminal receives the image signal in the area in charge of the variation recognition unit in the image signal and the combination of the received pixel signals corresponds to one of the stored patterns. To output from the output terminal It is desirable to use a configured one.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will be described below in detail with reference to the accompanying drawings. The present embodiment embodies the present invention as a printed wiring board pattern inspection apparatus and an inspection method executed by the apparatus. The pattern inspection apparatus according to the present embodiment inspects whether or not a surface pattern of a printed wiring board, which is an inspection object, includes a defective portion in pattern formation.
[0019]
(First form)
In this embodiment, a short circuit between lines will be described as an example of a typical defect portion. As shown in FIG. 1, this pattern inspection apparatus digitizes analog image data obtained by the imaging unit 1 having an illumination light source, a one-dimensional camera, and an inspection table (with a scanning function). The A / D conversion unit 2, the binarization unit 3 that binarizes the multi-gradation image data obtained by the A / D conversion unit 2, and the binary image data obtained by the binarization unit 3 will be described later. Shape recognition unit 4 that performs shape recognition processing to extract defect candidate information, and defect information totaling unit that aggregates defect candidate information obtained by the shape recognition unit 4 and sorts and deletes unnecessary items, and performs other statistical processing, etc. 5 and a defect display terminal 6 for individually displaying coordinates and types of the defect information output from the defect information totaling unit 5 and statistical display, and a defect confirmation device 7 for visually confirming an image of the defect part. And have.
[0020]
The shape recognition unit 4 is configured as shown in FIG. The shape recognition unit 4 is roughly divided into an image two-dimensional development unit 41 and a logical recognition unit 42. The image two-dimensional development unit 41 is a part that two-dimensionally develops the binary image data input from the binarization unit 3. In the image two-dimensional development unit 41 of the present embodiment, the binary image data is developed in 13 rows (A to M, sub-scanning direction) × 13 columns (1 to 13, main scanning direction). Therefore, the image two-dimensional development unit 41 is provided with a large number of line memories and shift registers (denoted as “SR” in the figure). The line memory is in charge of delay expansion in the row direction, and the shift register is in charge of delay expansion in the column direction.
[0021]
The logical recognition unit 42 is a part that performs shape recognition processing on the two-dimensional developed image (hereinafter simply referred to as a two-dimensional developed image) developed by the image two-dimensional developing unit 41. The logical recognition unit 42 is configured as shown in FIG. That is, the logical recognition unit 42 includes a basic recognition unit 421, a variation recognition unit 422, and a logical operation unit 423. The basic recognition unit 421 is a part for identifying whether or not the two-dimensional development image has a line shape as a premise of a short circuit and a protruding shape from the line as a starting point of the short circuit. The variation recognizing unit 422 is a part for identifying whether or not the two-dimensional developed image is suitable for any of the variations that can be short-circuited. The basic recognizing unit 421 and the variation recognizing unit 422 are in charge of a portion where the shape of the short circuit does not change due to the variation and a portion where the shape changes. The logic operation unit 423 is a part that performs logic processing on the outputs of the basic recognition unit 421 and the variation recognition unit 422 and outputs the result to the defect information totaling unit 5 as defect candidate information.
[0022]
The basic recognition unit 421 includes a pattern A recognition circuit 4211 and a pattern B recognition circuit 4212. The pattern A recognition circuit 4211 is a circuit for recognizing the recognition pattern A shown in FIG. 4, and is configured by a logic IC as a multi-input AND circuit as shown in FIG. As the logic IC, it is convenient to use a rewritable CPLD or FPGA having a large gate scale, and a circuit can be configured relatively compactly. The alphabetic characters on the left side and the numbers on the upper side in FIG. 4 are coordinate values as in FIG. The meanings of “1”, “0” and blank are the same as in FIG. Among the blank regions, a region T (the number of pixels is 15) surrounded by a thick line is a region in charge of the variation recognition unit 422. In the pattern recognition circuit of FIG. 5, the signal of each pixel described as “1” in FIG. 4 is positively input to the multi-input AND circuit, and the signal of each pixel described as “0” in FIG. Is inverted. Thus, the pattern recognition signal is output only when “1” and “0” in FIG. 4 are all satisfied.
[0023]
The pattern B recognition circuit 4212 is a circuit for recognizing the recognition pattern B shown in FIG. The recognition pattern B in FIG. 6 is a pattern obtained by horizontally inverting the recognition pattern A in FIG. Therefore, the pattern B recognition circuit 4212 has the configuration shown in FIG.
[0024]
The variation recognition unit 422 includes a pattern A lookup table circuit 4221 and a pattern B lookup table circuit 4222. The pattern A look-up table circuit 4221 stores patterns in which the shape of the short circuit can vary depending on variations in the region T in FIG. Similarly, the pattern B look-up table circuit 4222 stores patterns in which the shape of the short circuit can be varied depending on the region T in FIG.
[0025]
The logical operation unit 423 is provided with an AND circuit 4231 that receives the output of the pattern A recognition circuit 4211 and the output of the pattern A lookup table circuit 4221. Thereby, in the recognition pattern A of FIG. 4, the output of the AND circuit 4231 is turned on only when the condition is satisfied both inside and outside the region T. Similarly, an AND circuit 4232 that receives the output of the pattern B recognition circuit 4212 and the output of the pattern B lookup table circuit 4222 is provided. As a result, also in the recognition pattern B of FIG. 6, the output of the AND circuit 4232 is turned on only when the condition is satisfied both inside and outside the region T. Further, an OR circuit 4233 that receives the output of the AND circuit 4231 and the output of the AND circuit 4232 is provided. As a result, if any one of the recognition pattern A in FIG. 4 and the recognition pattern B in FIG. 6 satisfies the internal / external condition, defect candidate information is output from the OR circuit 4233 to the defect information totaling unit 5. Yes.
[0026]
The pattern A lookup table circuit 4221 will be further described. An example (but not all) of variation patterns stored in the pattern A lookup table circuit 4221 is shown in FIG. Thus, there are many variations in the shape of the short circuit. This is because any pattern connected from the left side to the right side of the region T corresponds to “short circuit”. The pattern B lookup table circuit 4222 stores variation patterns obtained by horizontally inverting the variation patterns shown in FIG.
[0027]
The pattern A lookup table circuit 4221 is configured as shown in FIG. That is, it has an arrangement setting circuit 10, a multiplexer 11, a high-speed SRAM 12, and a gate 13. Of these, the multiplexer 11, the high-speed SRAM 12, and the gate 13 receive control signals (including address signals) from the CPU.
[0028]
Of the circuit configuration shown in FIG. 9, the main part as a lookup table is of course the high speed SRAM 12. The addresses A0 to A14 correspond to 15 pixels in the region T in FIG. The input / output I / O 0 is an output terminal to the AND circuit 4231. The remaining 7 bits (I / O1 to I / O7) are reserved. The arrangement setting circuit 10 selects an appropriate pixel according to the purpose from the two-dimensional developed image input from the image two-dimensional developing unit 41 and supplies the selected pixel to the high-speed SRAM 12. Of course, all 15 pixels in the region T are selected. The 15-pixel signal is input to the A0 to A14 terminals of the high-speed SRAM 12 via the multiplexer 11. The multiplexer 11 and the gate 13 are for performing operations from the CPU when setting the contents of the high-speed SRAM 12. That is, the multiplexer 11 selects whether an input signal to the A0 to A14 terminals of the high-speed SRAM 12 is a pixel signal from the arrangement setting circuit 10 or an address signal from the CPU. The gate 13 turns on / off the signal input from the CPU to the I / O0 to I / O7 terminals of the high-speed SRAM 12.
[0029]
In the normal inspection mode, the output pixel signal of the arrangement setting circuit 10 is input to the A0 to A14 terminals of the high-speed SRAM 12. The gate 13 is off. On the other hand, when the contents of the high-speed SRAM 12 are set, that is, when each variation illustrated in FIG. 8 is stored in the high-speed SRAM 12 (or when the contents are changed), the CPU address is A0 to A14 of the high-speed SRAM 12. Input to the terminal. Also, the gate 13 is turned on.
[0030]
In the high-speed SRAM 12, as shown in FIG. 10, the output value (“0” or “1”) of the I / O0 terminal can be set for any combination of the input values to the A0 to A14 terminals. is there. Therefore, the output value “1” is assigned to all combinations corresponding to the pattern connected from the left side to the right side of the region T as illustrated in FIG. All other combinations are assigned the output value “0”. As a result, all variations of short-circuit shapes can be handled with one memory.
[0031]
Returning to FIG. 1, the defect information totaling unit 5 has mask data for deleting unnecessary information from the defect candidate information output from the shape recognition unit 4. This is because, in the specification of the printed wiring board, a shape that looks like a short circuit may be included as a correct pattern.
[0032]
Next, a pattern inspection procedure by the pattern inspection apparatus will be described. When pattern inspection is executed by this pattern inspection apparatus, a printed wiring board as an inspection object is placed on an inspection table (see FIG. 1) of the imaging unit 1. Then, the printed wiring board is imaged with a camera while illuminating it with an illumination light source to obtain image data. Since this image data is analog, it is digitized by the A / D converter 2. Further, binarization is performed by the binarization unit 3. The binary image data thus obtained is input to the shape recognition unit 4. Then, in the shape recognition unit 4, the binary image data is delayed and expanded in two dimensions (13 rows × 13 columns) by the image two-dimensional expansion unit 41 (see FIG. 2).
[0033]
The two-dimensional developed image thus obtained is input in parallel to the basic recognition unit 421 and the variation recognition unit 422 in the logical recognition unit 42. The two-dimensional developed image is further input in parallel to the pattern A recognition circuit 4211 and the pattern B recognition circuit 4212 in the basic recognition unit 421. Also in the variation recognition unit 422, the pattern A lookup table circuit 4221 and the pattern B lookup table circuit 4222 are input in parallel. Hereinafter, the pattern A will be described as a representative.
[0034]
The pattern A recognition circuit 4211 has all the binarized values of each pixel described as “1” in FIG. 4 as “1” and the binarized value of each pixel described as “0”. When all are “0”, a pattern recognition signal is output (see FIG. 5). When a pattern recognition signal is output from the pattern A recognition circuit 4211, it means that the two-dimensional developed image includes a line shape as a premise of short circuit and a protruding shape as a short circuit starting point. is doing. If any one of the pixels described as “1” or “0” in FIG. 4 does not meet the above condition, the pattern A recognition circuit 4211 does not output a pattern recognition signal.
[0035]
The pattern A look-up table circuit 4221 outputs a pattern recognition signal when the combination of the binarized values of each pixel in the region T in FIG. 4 is “1” in FIG. That is, when a pattern recognition signal is output from the pattern A lookup table circuit 4221, pixels having a binarized value “1” from the left side to the right side of the region T are connected as illustrated in FIG. It means that
[0036]
When both the pattern A recognition circuit 4211 and the pattern A lookup table circuit 4221 output pattern recognition signals, the output of the AND circuit 4231 is turned on. For example, in the example shown in FIG. 11, both the recognition conditions of the pattern A recognition circuit 4211 and the pattern A lookup table circuit 4221 are satisfied. Therefore, the output of the AND circuit 4231 is turned on, and defect candidate information is output from the OR circuit 4233 to the defect information totaling unit 5. The two-dimensional developed image in the example of FIG. 11 is the same as that of FIG. That is, in the present embodiment, the flexibility of variation is dramatically improved.
[0037]
Of course, even when each condition is matched in the pattern B, defect candidate information is similarly output from the OR circuit 4233 to the defect information totaling unit 5.
[0038]
The defect information totaling unit 5 compares the defect candidate information output from the OR circuit 4233 of the shape recognition unit 4 with the mask data. This is to delete unnecessary items. What remains without being deleted is defect information. The defect information totaling unit 5 further performs statistical processing for each type of defect information. With respect to the defect information aggregated in the defect information aggregation unit 5, individual display of coordinates and types and statistical display can be performed on the defect display terminal 6. Moreover, the defect confirmation apparatus 7 can also visually confirm the image of the defective part.
[0039]
As described above in detail, in this embodiment, the logical recognition unit 42 of the shape recognition unit 4 is provided with the basic recognition unit 421 and the variation recognition unit 422. The basic recognition unit 421 configured by a logic circuit has a role of identifying whether or not the two-dimensional developed image has a line shape as a short-circuiting premise and a protruding shape as a short-circuit starting point. Further, the variation recognition unit 422 configured as a look-up table using the high-speed SRAM 12 identifies whether the binarized image in the region T corresponds to one of the possible variations of the short-circuit shape. Giving a role. And when both output the recognition signal, defect candidate information is output because there is a short circuit there.
[0040]
As a result, the short-circuit shape can be appropriately recognized by one logic IC and one memory (high-speed SRAM) per recognition pattern. In other words, any variation-shaped short circuit can be reliably recognized without omission. The required capacity of logic circuits and memories is also kept to a minimum. On the other hand, when trying to take charge of everything in the logic circuit as described in the prior art, recognition failure occurs due to insufficient response (flexibility) to various variations. On the other hand, if you try to process everything with a lookup table, an extremely large amount of memory is required. This is because the required amount of memory increases by a factorial of 2 each time the number of pixels increases. In the present embodiment, this difficulty is overcome by using a combination of both and arranging a lookup table at a key point. Further, since the lookup table is composed of a high-speed SRAM, the processing speed is high and processing can be performed in real time of imaging in the imaging unit 1. It also has the flexibility to allow content changes as needed.
[0041]
(Second form)
Next, what recognizes a thin line as a defect location other than a short circuit will be described. The configuration of FIGS. 1 and 2 is of course common to that of the first embodiment. The configuration of FIG. 9 is also almost common.
[0042]
The logical recognition unit 42 has the configuration shown in FIG. 12 instead of the configuration of FIG. That is, the basic recognition unit 421 is provided with a pattern C recognition circuit 4213 instead of the pattern A recognition circuit 4211 and the pattern B recognition circuit 4212. In addition, the variation recognition unit 422 is provided with an upper lookup table circuit 4223 and a lower lookup table circuit 4224 instead of the pattern A lookup table circuit 4221 and the pattern B lookup table circuit 4222. . The logic operation unit 423 is provided with a three-input AND circuit 4234 instead of the AND circuit 4231, the AND circuit 4232, and the OR circuit 4233. The three-input AND circuit 4234 receives outputs of the pattern C recognition circuit 4213, the upper lookup table circuit 4223, and the lower lookup table circuit 4224.
[0043]
The pattern C recognition circuit 4213 is a circuit for recognizing the recognition pattern C shown in FIG. 13, and is composed of a multi-input AND circuit by a logic IC as shown in FIG. The coordinate display in FIG. 13 and the meanings of “1”, “0”, and blank are the same as in FIG. In the blank area in FIG. 13, two areas T1 and T2 assigned by the variation recognition unit 422 are set. The upper look-up table circuit 4223 of the logical operation unit 423 is responsible for the area T1, and the lower look-up table circuit 4224 is responsible for the area T2. Therefore, the upper look-up table circuit 4223 stores variation patterns (not all) illustrated in FIG. Similarly, the lower look-up table circuit 4224 stores variation patterns obtained by inverting each variation pattern shown in FIG.
[0044]
In this embodiment, when all three of the pattern C recognition circuit 4213, the upper lookup table circuit 4223, and the lower lookup table circuit 4224 output the pattern recognition signal, the three-input AND of the logic operation unit 423 is output. The defect candidate information is output from the circuit 4234 to the defect information totaling unit 5. In this embodiment, as shown in FIG. 16, even shapes (see FIG. 24) that cannot be recognized as line thinning in the conventional technology are recognized as line thinning.
[0045]
Note that this embodiment is merely an example and does not limit the present invention. Therefore, the present invention can naturally be improved and modified in various ways without departing from the gist thereof. For example, the defect that is the target figure for inspection is not limited to a short circuit or thin line between lines, but may be other types of defects (disconnection, etc.). Further, the inspection object itself is not limited to the printed wiring board, but may be another object. Further, the image data used for the inspection is not limited to the image captured by the image capturing unit 1 each time, but may be data read in advance in an appropriate file format in the storage medium. Further, in the logical recognition unit 42 of the first embodiment, the OR of the recognition results of the two patterns which are in a horizontally reversed relationship with each other is taken, but this is not essential. Only one of them may be used, or a rotation pattern every 90 ° may be further connected by OR. In the imaging unit 1, the inspection table may be fixed and the camera may be a two-dimensional camera instead.
[0046]
Furthermore, the basic recognition unit 421 of the logical recognition unit 42 is not limited to the logic IC method described in the present embodiment, and may be a memory method. FIG. 17 shows a specific circuit example in that case. That is, 13 systems (A to M columns) that are substantially the same as those shown in FIG. 9 are prepared, and the output lines of the high-speed SRAM of each system are aggregated for each row. With this configuration, the pattern recognition results of FIGS. 4, 6, and 13 can be output by setting the contents of each high-speed SRAM.
[0047]
Further, the variation recognition unit 422 can be modified. The first modification is to use a ROM instead of a high-speed SRAM. In this case, however, the contents cannot generally be changed. Although the content can be changed with an EEPROM, the SRAM has an advantage in the rewrite tact time. A DRAM may be used if the processing speed may be sacrificed a little. However, in that case, it is necessary to devise an interleave method in consideration of the precharge operation and the refresh operation. Although the contents are fixed, the function of the lookup table may be incorporated in the custom IC.
[0048]
In the example shown in FIG. 4 (also in FIG. 6), only one region T to be processed by the look-up table is arranged in a 13-row × 13-column two-dimensional developed image. However, depending on the type of defect, it is possible to arrange two as shown in FIG. 13, or three or more. In that case, the shape, the number of pixels, and the contents of each region T may not be the same. Furthermore, it is conceivable to provide a master-slave relationship in two or more regions T. An example is shown in FIG. That is, the position of the sub area T2 is changed according to the recognition result in the main area T1. In this way, it is possible to efficiently recognize a short circuit at a portion where the width between the lines is wide without increasing the number of pixels per region.
[0049]
【The invention's effect】
As is apparent from the above description, according to the present invention, even an object having a complicated and fine pattern does not require an excessively large amount of memory or logic resources, and has a pattern recognition flexibility. An inspection apparatus and a pattern inspection method are provided.
[Brief description of the drawings]
FIG. 1 is a block configuration diagram of a pattern inspection apparatus according to an embodiment.
FIG. 2 is a configuration diagram of a shape recognition unit.
FIG. 3 is a configuration diagram of a logical recognition unit for short circuit recognition.
FIG. 4 is a diagram showing a recognition pattern of a pattern A recognition circuit.
FIG. 5 is a circuit diagram in which the recognition pattern of FIG. 4 is realized by a logic gate.
FIG. 6 is a diagram showing a recognition pattern of a pattern B recognition circuit.
7 is a circuit diagram in which the recognition pattern of FIG. 6 is realized by a logic gate.
FIG. 8 is a diagram illustrating variations in the shape of a short circuit.
FIG. 9 is a circuit diagram in which a lookup table is realized by a high-speed SRAM.
10 is a code pattern table of the high-speed SRAM in FIG. 9. FIG.
FIG. 11 is a diagram illustrating a recognition example of a short circuit.
FIG. 12 is a configuration diagram of a logical recognition unit for line thinning recognition.
FIG. 13 is a diagram showing a recognition pattern of a pattern C recognition circuit.
FIG. 14 is a circuit diagram in which the recognition pattern of FIG. 13 is realized by a logic gate.
FIG. 15 is a diagram illustrating a variation in the shape of a thin line.
FIG. 16 is a diagram illustrating an example of recognition of line thinning.
FIG. 17 is a circuit diagram of an example in which a basic recognition unit is realized by a memory.
FIG. 18 is a diagram illustrating an example in which two lookup table master-slave relationships are provided.
FIG. 19 is a diagram showing a short-circuit recognition pattern in a conventional inspection method.
20 is a diagram showing a recognition example of a short circuit by the recognition pattern of FIG.
FIG. 21 is a diagram illustrating a case where a short circuit cannot be recognized in the recognition pattern of FIG.
FIG. 22 is a diagram showing a line thinning recognition pattern in a conventional inspection method.
23 is a diagram showing an example of line thinning recognition based on the recognition pattern of FIG.
24 is a diagram illustrating a case where thin lines cannot be recognized with the recognition pattern of FIG.
[Explanation of symbols]
12 High-speed SRAM
41 Two-dimensional image development unit
42 Logical recognition unit
421 Basic recognition unit
422 Variation recognition unit
4221 Look-up table circuit
4222 Look-up table circuit
4223 Look-up table circuit
4224 lookup table circuit

Claims (6)

In a pattern inspection device that extracts the shape of a defective part that appears at a defective part from an image signal obtained by imaging a wiring pattern of a printed wiring board ,
A basic recognition unit for recognizing a basic part that does not change due to variations in the shape of the defect part ;
A variation recognizing unit that recognizes a variation part that varies depending on the variation of the defect location shape,
When the basic recognition unit recognizes the basic part of the defect location shape for the image signal, and the variation recognition unit recognizes any of the variations of the variation portion of the defect location shape, the defect location shape is included in the image signal. A pattern inspection apparatus characterized by recognizing that it exists. The pattern inspection apparatus according to claim 1,
The variation recognizing unit stores each pattern corresponding to the variation of the variation portion of the defect location shape, and outputs a pattern recognition signal only when the image signal corresponds to one of the stored patterns. A pattern inspection apparatus comprising: The pattern inspection apparatus according to claim 2 ,
The lookup table is based on SRAM .
The input address terminal receives the image signal in the area in charge of the variation recognition unit in the image signal,
A pattern inspection apparatus configured to output a pattern recognition signal from an output terminal only when a combination of received pixel signals corresponds to one of stored patterns. In a pattern inspection method for extracting a defect part shape that appears in a defect part from an image signal obtained by imaging a wiring pattern of a printed wiring board,
A basic recognition unit for recognizing a basic part that does not change due to variations in the shape of the defect part ;
Variations portion varies with variations of the defective portion shapes have use a variation recognition unit that recognizes,
When the basic recognition unit recognizes the basic part of the defect location shape for the image signal, and the variation recognition unit recognizes any of the variations of the variation portion of the defect location shape, the defect location shape is included in the image signal. A pattern inspection method characterized by recognizing that it exists. In the pattern inspection method according to claim 4 ,
As the variation recognition unit, a lookup that stores each pattern corresponding to a variation of the variation portion of the defect portion shape, and outputs a pattern recognition signal only when the image signal corresponds to any of the patterns stored pattern inspection method comprising Rukoto have use those having a table. The pattern inspection method according to claim 5 ,
As the lookup table, by SRAM ,
The input address terminal receives the image signal in the area in charge of the variation recognition unit in the image signal,
What is claimed is: 1. A pattern inspection method comprising: a pattern recognition signal output from an output terminal only when a combination of received pixel signals corresponds to one of stored patterns.

Images