FR2719684A1 - Method and circuit for detecting image structures in the form of lines linked topologically with one another. - Google Patents

Abstract

Two multiplexers connected by their inputs to the output of a counter (Z), and a comparator (C) have inputs for the reference numbers (KN1, KN2) on the other hand sent to the outputs of two registers (R1, R2 ) whose data inputs are connected to an output of a third register (R3) also coupled to the address input of two memories (RAM1, RAM2) and whose input is connected to the output of the multiplexer (M1 ). A data input and output (D) of the first memory (RAM1) is coupled to another input of the multiplexer (M1), to the data output of the multiplexer (M2), to the input of a zero indicator ( N) and to a data input (D) of the memory (RAM2). From a process flow control (ST) there are connections to the control inputs of the multiplexers (M1, M2), to the enable inputs (EN) of the multiplexer (M2) and to the memory (RAM1) and to the write inputs (W) of the memories (RAM1, RAM2).

Description

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  Method and circuit for detecting image structures in form of lines linked to.pologically between

  d.j a-e ___ e .. f__E ._...................................... __ e ......

  they. The invention relates to the detection in real time video, by lines, of image structures linked topologically to each other, in which groups of image points or pixels of the same characteristics receive in a line different reference numbers each. others among which, for the neighboring groups of a following line, the reference number of the group of pixels of said line is taken, from which a group of pixels of the following line traversed in the direction of the line is first immediately neighbor by at least one pixel in the direction

of the column.

  The invention is implemented for the automatic inspection of structured surfaces in particular of masks, liquid crystals, conductive plates, semiconductor discs during their

manufacturing process.

  One of the operations during the evaluation of an image consists in choosing according to certain criteria (characteristics) among the pixels, or the groups of pixels arranged in a matrix and, for a later exploitation, to prepare them in the form

  compacted for the following operating units.

  It is known, for data compression, to first combine the pixels in a line and to eliminate

then the line terminals.

  According to EP 279 157 A2, data characteristic of information coded according to the length of the displacement is extracted. The result is a list of image data coded according to the length of the displacement which are ordered according to zones.

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  circular, trapezoidal, convergent and divergent. In doing so, vertical and horizontal intervals are filtered and disappear from the dataset. This is inappropriate for

  the detection of defects on semi- chips

  driver, because the filtering of the intervals distorts the image of the defect with the consequence of an incorrect classification in the error classes of the

semiconductor chip.

  A suitable solution is to mark all the image data coded according to the length of the displacement which describes a continuous area with identical characteristics, for example values of

  gray, as a unit as such.

  Reference or count numbers are introduced for the groups of pixels linked together within a line, so that all groups of pixels starting in the first line are given an increasing reference number. A new count number is only assigned in the next line if the group of pixels is not close to a group of pixels having the same characteristics in the previous line. If the pixel group of the next line has the same characteristics as that of the previous line, then the same number is used. There are ambiguities, called equivalences, when groups of pixels linked together in the current line have links with several groups of pixels linked together with the same characteristics but with a reference number different from the previous line. These equivalences are thus presented as pairs of reference numbers different from each other and correspond to relations

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  between groups of pixels which initially meet separately. To resolve these ambiguities, we can use a computer-assisted search algorithm, the working time of which depends on the shape of the structures.

  image distributed in pixel groups.

  Spiral or strongly nested image structures which result therefrom cause working times which can no longer be processed until

  elimination in real time video.

  The object of the invention is to shorten the processing time for eliminating equivalences regardless of the shape and characteristics of the image structures so that processing up to

  elimination in real time video is allowed.

  According to the invention, this problem is solved by a method of recognizing image structures topologically linked to each other and detected by lines, in which groups of pixels with the same characteristics, consisting of at least one pixel, receive at the within a single line increasing reference numbers, and groups of pixels of a following line include the reference numbers already assigned to the groups of pixels for which there is already a neighborhood with at least one pixel in the direction of the line, in that during a first step of the method, the first reference number of pairs of reference numbers of groups of contiguous pixels having reference numbers different from each other, is used as address value for a first memory addressed with a starting state marked for each memory location, and the other reference number is used as the data value of the job memory acement sent by means of the first reference number, when the memory location has the initial state marked,

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  otherwise, in a second step of the method, both the other reference number and the data value of the addressed memory location are used as address data for the detection of the memory locations with a marked starting state, to the address data of which the first step of the method is used, a data value obtained for each address value serving again as an address as long as a memory location with the starting state marked has not was found and pairs of reference numbers leading to the same address values in the second step of the method are not taken into account, and in a third step of the method, to form an allocation table in the form of a second addressable memory, memory locations corresponding to the address values from the first step of the method receive the address value itself as a data value when the marked start state is present for the address value, otherwise a data value obtained as address value is used for an address value without marked start state until a memory location with the marked start state be found whose address value becomes the data value for the

  address value without marked start status.

  The object of the invention is also a circuit for recognizing image structures topologically linked together and detected by lines, by processing a pair of different reference numbers of groups of pixels, consisting of at least one pixels, neighbors between them in contiguous lines inside an image structure, an assignment of the reference numbers for the groups of pixels in a line being carried out continuously and groups of pixels of a following line containing the reference numbers already assigned to the groups of

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  pixels for which there is already a neighborhood with at least one pixel in the line direction, in which a first and a second multiplexer, each of which has an input connected to the count value output of a counter, and a input of the second multiplexer is subjected to a fixed potential, as well as a comparator present inputs for the reference numbers which are on the other hand sent to the outputs of a first and of a second register whose data inputs are connected to an output of a third register which is coupled on the other hand to an address input of a first memory and to a first address input of a second memory and the input of which is connected to the

output of the first multiplexer.

  A data input and output of the first memory is coupled to another input of the first multiplexer, to the data output of the second multiplexer, to the input of a zero indicator and to a first data input of the second memory which also has a second address input and a second output, and, from a process flow command with KN and RESET inputs and ENK and READY outputs, leave from the output side of the connections to the inputs for controlling the first and second multiplexers to the validation inputs of the second multiplexer and of the first memory and to the write inputs of the first and of the second memories. In addition, from the process flow command, there are connections between the rhythm outputs and the first, second and third registers, the counter, and to a counter loading input and to the inputs of validation of the first and second registers. On the input side, the process flow control is also connected to a two-line counter end of signal line.

  of the comparator and one line of the zero indicator.

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  As the assignment table, which contains the assignment of a reference number for each equivalence addressed, is established directly from a generated intermediate code, the equivalences can be evaluated already at the time of their detection. This results in a shorter processing time compared to a computer-assisted search algorithm which can only start working when all the equivalences are present. The number of steps for solving an equivalence according to the invention is equal to the degree of overlapping of the equivalence processed, while the number of steps with a computer-assisted search algorithm for the same work is the even for all equivalences and equal to the highest degree of nesting. An exemplary embodiment of the invention is described in more detail below by means of the appended schematic drawing on which we see: Figure i: a circuit according to the invention Figure 2: an assignment of numbers

  reference to groups of pixels.

  In the circuit shown in FIG. 1, a first and a second multiplexer M1 and M2, each of which an input is connected to the count value output of a counter Z, as well as a comparator C, have inputs for reference numbers KN1 and KN2 and are also connected to an output of a first register R1 and to an output of a second

R2 register.

  The data inputs of the first and second registers R1 and R2 are connected to the output of a third register R3 which is on the other hand coupled to a respective address input of a first and a second memory RAM1 and RAM2. The input of the third register R3 is connected to the output of the first

multiplexer M1.

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  A data input and output D of the first memory RAM1 is connected to another input of the first multiplexer M1, to the data output of the second multiplexer M2, to the input of a zero indicator N and to a data input D of the second RAM2 memory. Another input of the second multiplexer

is subject to a fixed potential.

  The second memory RAM2 is produced in the form of a random access memory with double port and has a second address input A1 for an input signal AL and a second output D1 for a signal

DL output.

  The outputs of an ST process flow control, with KN and RESET inputs and ENK and READY outputs, are connected to the control inputs of the first and second multiplexers M1 and M2, to the EN validation inputs of the second multiplexer M2 and from the first memory RAM1 and to the write input W of the first and from the second memories RAM1 and RAM2. Links exist between

  Rhythm outputs of the sequence control CLK-

  R1 and the first register R1, CLK-R2 and the second register R2, CLK-R3 and the third register R3, CLK-Z and the counter Z, towards a loading input L of the counter Z and towards the validation inputs EN of registers R1 and R2. In addition, the sequence control ST is connected on the input side to a line for the end of process signal U of the counter Z, to two lines of the comparator C and to a line of the zero indicator N. We have shown in the figure 2 of the structures assembled from pixels of a surface with different characteristics in the form of gray values. The numbers shown therein are reference numbers assigned in a known manner to groups of pixels as parts of data sets, these groups of

pixel with at least one pixel.

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  In this way, the two figures, each consisting of a single pixel, of the zero line can be described by the following sets of data coded according to the length of the movement: Data set 1 Data set 2 Line number: 0 Number of 1 line: 0 Start in column: 4 Start in column: 10 Length of movement: 1 Length of movement: 1 Reference number: 1 Reference number: 2 Gray value: 10 Gray value: 10 Games of analogous data are assigned to the pixel groups in the following lines, thus for example for the pixel groups of line 2: Data set 1 Data set 2 Data set 3 Line number: 2 Line number: 2 Number of line: 2 Beginning in column: 5 Beginning in column: 16 Beginning in column: 37 2 0 Lon9 dJeurJ displacement: 8 Length of displacement: 1 Length of displacement: 2 mm reference number: 1 Reference number: 4 Number reference: 4 Gray value: 10 Vale gray: 30 Gray value: 30 Ambiguities appearing as equivalences that occur when the pixel groups of a line have links with several pixel groups, with the same characteristics but with different reference numbers, from the previous line, exist for example between groups of

  reference pixels i and reference pixels 2 or 3.

  The complete number of all the equivalences in FIG. 2, which are in memorized form for further processing, is listed in table i by indicating the reference numbers. Tables 2 and 3 already include the results in advance

targeted by the invention.

  Table 1 Table 2 Table 3 Equivalences Intermediate code Assignment table in the first memory according to RAN1 provision in the second memory RAM2 Mr. KN1 KN2 Address Data Address Data

1 1 3 1 0 1 1

2 1 2 2 1 2 1

3 6 4 3 1 3 1

4 6 5 4 0 4 4

4 6 5 4 5 4

6 8 4 6 4 6 4

7 10 8 7 0 7 7

8 4 12 8 4 8 4

9 4 10 9 0 9 9

17 15 10 8 10 4

11 15 11 11i 7 11 7

12 11 7 12 4 12 4

13 0 13 13

14 0 14 14

11 15 7

16 0 16 16

17 15 17 7

18 0 18 18

  Due to a RESET reset signal to the process control ST, this causes the counter Z to deliver the address Zero to the first multiplexer M1. At the same time, the sequence command ST controls the first and second multiplexers M1 and M2, by command lines, so that the count value of the counter Z is sent from the output of the multiplexer M1 to the third register R3 and that 'a null reference is present at the data entry of the first RAMI memory. By means of a clock signal CLK-Z of the sequence control ST, the count value of the counter Z is taken up by the register R3 and is applied to the

  first RAM1 memory as address.

  The sequence command ST then writes the zero reference to the memory location addressed in the first memory RAMI, and increments the counter Z. This process is repeated at each of the memory locations of the first memory RAM1 until

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  the whole of the first memory RAM1 is filled with

the null reference.

  After introduction of the zero reference to each memory location of the first memory RAM1, there follows a change of state which is

  necessary for the elimination of equivalences.

  A signal KN from a memory not shown activated at the input of the circuit indicates the storage

of equivalences in memory.

  Following an ENK signal, from the ST sequence command, a pair of reference numbers KN1 and KN2, which defines an equivalence, is applied to the

corresponding entries.

  Comparator C compares the two reference numbers KN1 and KN2. If the two reference numbers are equal there is no processing. Otherwise, a control signal is sent to the sequence control ST which, after exploitation of this signal redirects the reference number of greatest value as the first reference number, by its control lines, to the multiplexer Ml1. The process according to the invention can obviously be carried out if the smallest number is permanently used as the reference number. Thus, this reference number is applied as an input value to the register R3 and is stored in this register R3 by means of a rhythm signal from the sequence control ST then arriving. As the output of register R3 is permanently validated, the reference is also found at the address inputs of the first and second memories RAM1 AND RAM2 as well as at registers R1 and R2. Then, the sequence control ST switches the first memory RAM1 into read mode by

its command line.

  The content of the first memory location of the first memory RAM1 addressed with the first reference number, in the largest present example, is present at the data output of the first memory il 2719684 RAM1 and goes from there to input of the multiplexer M1, at the output of the multiplexer M2, to the data input of the second memory RAM2 and to the zero indicator N. The latter informs the process flow control ST if the content of the memory is a zero reference. If a zero reference is present, then the sequence command ST commands the first memory RAM1 to delete this reference at its output and validates the second reference number, in the smallest present example, at the output of the multiplexer M2, so that it is found at the data entry of the first memory RAM1. By a writing pulse of the sequence command ST, the value of the smallest reference number is stored in the memory location of the first memory RAM1 addressed with the largest reference number for the zero reference. If no null reference is present, a search process is triggered in the first

  RAM1 memory with the following sequence.

  The process flow control ST switches the multiplexer M1 by its control lines into a state in which the value present at the output of the first memory RAM1 is validated towards the register R3, and stores it therein by means of '' a CLK-R3 rhythm signal. The zero indicator N tests in the manner previously described if a zero reference has been recorded at the addressed memory location. This process is repeated until a zero reference has been signaled to the ST sequence control by the zero indicator. The search process is then interrupted. The sequence control ST stores the address located in the register R3 in the

  register R1 by sending a CLOCK-R1 rhythm signal.

  Then, the smallest reference number is applied in the same way by the sequence command ST to the first memory RAM1 and a

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  process of finding a null reference is triggered as described. The address of the null reference of the smallest reference number is stored in the register R2. Then the source of reference numbers is inhibited by means of the control signal ENK and the outputs of registers R1 and R2 are applied to the inputs KN1 and KN2, so that now the values of the registers are processed

  as reference numbers KN1 and KN2.

  As soon as for all the equivalences a recording has taken place in the first memory RAM1, recognizable by the input signal KN, a change of state takes place, necessary for the establishment of a

  allocation table, in the circuit.

  This results in a start of the counter Z and the delivery of a value as a zero address to the first memory RAM1. The content of the addressed memory location is read by the zero indicator N. If the zero reference is still present in the memory location, the process flow command ST switches the first memory RAM1 with its command line in the inactive state and commands the multiplexer M2 to validate the count value at its output. With the write pulse W, the count value is saved in memory RAM2. The counting state is then incremented and the process is then repeated for each memory location which has a zero reference in the first memory RAM1. If a memory location having no zero reference is detected, the process control ST puts the multiplexer M1 in a state in which at its output, and thus at the input of the register R3, the contents of the first memory RAM1 is

present.

  With a CLK-R1 and CLK-R3 signal, the address found so far in the first memory RAM1 is

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  stored in register R1 and the content of the first memory RAM1 is stored in register R3

  as new address for the first RAM1 memory.

  The first RAMI memory is again tested by the zero indicator N, looking for a zero reference. If this is not the case, the content of the addressed memory location of the first memory RAM1 is again recorded as the following address in the register R3. This process repeats until a memory location with a null reference

be found.

  The address of this memory location is stored in the register R2 by the control signal CLK-R2. At the same time the register R1 is connected by the sequence control ST to the input KN1 and by the control of the multiplexer M1, the input KN1 is connected to the

register R3.

  By a control signal CLK-R3 of the sequence control ST, the content of the register R1 is

transferred to register R3.

  Then, by the sequence command ST, the output of the register R2 is validated at the input of the multiplexer M2 and the multiplexer M2 controlled to validate the content of the register R2 at its output. Thanks to a write pulse from the ST sequence command, this value is recorded in the second

RAM2 memory.

  Then the count value is incremented and the test for finding a zero reference in the next memory location of the first memory RAM1 again starts again in the manner described until all the memory locations in the table assignment are stored in the second RAM2 memory. The process control ST recognizes this state by an information signal 0 from the counter Z, ends the job and announces this state by

a READY signal through the READY line.

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Claims (2)

  1. - Method for recognizing topologically linked image structures detected by lines, in which groups of pixels with the same characteristics, consisting of at least one pixel, receive numbers within the same line of increasing references, and groups of pixels of a following line take up the reference numbers already assigned to the groups of pixels for which there is already a neighborhood with at least one pixel in the direction of the line, characterized in that during of a first step of the method, the first reference number of pairs of reference numbers of groups of contiguous pixels having different reference numbers between them, is used as address value for a first memory addressed with a starting state marked for each memory location, and the other reference number is used as the data value of the memory location addressed to the means of the first reference number, when the memory location has the initial state marked, otherwise, in a second step of the process, both the other reference number and the data value of the memory location addressed are used as address data for the detection of memory locations with a marked starting state, at the address data of which the first step of the method is used, a data value obtained for each address value used again for address as long as a memory location with the starting state marked was not found and pairs of numbers 2719684   reference leading to the same address values in the second step of the method not being taken into account, and in that in a third step of the method, to form an allocation table in the form of a second addressable memory, memory locations corresponding to the address values from the first step of the method receive the address value itself as a data value when the marked initial state is present for the address value, otherwise we use for an address value without starting state marked a data value obtained as address value until a memory location with the starting state marked is found whose address value becomes data value for the   address value without marked start status.   2. - Circuit for recognizing image structures topologically linked to each other and detected by lines, by processing a pair of different reference numbers of groups of pixels, consisting of at least one pixel, neighboring them in contiguous lines inside an image structure, an assignment of the reference numbers for the groups of pixels in a line being carried out continuously and groups of pixels of a following line taking again the reference numbers already allocated groups of pixels for which there is already a neighborhood with at least one pixel in the direction of the line, characterized in that a first and a second multiplexer (M1) and (M2), one input of each of which is connected to the counter value output of a counter (Z), and an input of the second multiplexer (M2) is subjected to a fixed potential, as well as a comparator (C) have inputs for the reference numbers (K N1) and (KN2) which are also sent to the outputs of a first 16 2719684   and a second register (R1, R2) whose data inputs are connected to an output of a third register (R3) which is coupled on the other hand to a respective address input of a first and of a second memory (RAMi) and (RAM2) and the input of which is connected to the output of the first multiplexer (M1), in that a data input and output (D) of the first memory (RAM1) is coupled to another input from the first multiplexer (M1), at the data output from the second multiplexer (M2), at the input of a zero indicator (N) and to a data input (D) from the second memory (RAM2 ) which also comprises an address input (A1) for an input signal (AL) and an output (D1) for an output signal (DL), and in that, from a sequence control of process (ST) with inputs (KN) and (RESET) and outputs (ENK) and (READY) start from the output side as well from the connections to the control inputs of the first and second m ultiplexers (M1, M2) to the validation inputs (EN) of the second multiplexer (M2) and the first memory (RAM1) and to the write inputs (W) of the first and second memories (RAMI, RAM2 ) that, from the process flow command, links between a rhythm output (CLK-R1) and the first register (R1), a rhythm output (CLK-R2) and the second register (R2) and a rhythm output (CLK-R3) and the third register (R3), a rhythm output (CLK-Z) and the counter (Z), to a loading input (L) of the counter (Z) and to the inputs validation (EN) of the first and second registers (R1, R2), and, on the input side, the process flow control (ST) is linked to an end of work signal line () of the counter (Z), two lines from the comparator (C) and one line from the zero indicator (N).