FR2628237A1 - VECTOR REGISTER FILE, COMPUTER SYSTEM FOR PROCESSING VECTORS USING SUCH FILE, AND METHOD FOR MANAGING ACCESS TO THIS FILE - Google Patents

Abstract

A vector register file for a vector processing computer system comprises a first group 101 of memory circuits, a second group 102 of memory circuits, which can be cyclically controlled independently of the first group, a third group 103 of memory can be controlled cyclically independently of the first group and a fourth group 104 of memory circuit, which can be controlled cyclically independently of the other groups, the first two groups being formed by static direct-access memories and the file being subdivided into a plurality of context areas usable for separate processes. Application in particular to mathematical calculations of convolution and recurrence.

Description

Q FRENCH REPUBLIC N of publication: 2 628 237 (to be used only

  for INSTITUTE NATIONAL Reproduction Orders)

FROM THE INDUSTRIAL PROPERTY G

  OF INDUSTRIAL PROPERTY N of national registration: 89 02569 PARIS

(Int CI4 G 06 F 15/336, 12/02.

@ APPLICATION FOR PATENT OF INVENTION A1

  Date Filed: February 28, 1989. Q Applicant (s): ARDENT COMPUTER CORPORATION.

- US.

  () Priority: US, 1 March 1988, No. 162,738.

  @ Inventor (s): Glen S. Miranker: Steve Johnson.

  (Date of the public availability of the

  application: BOPI "Patents" No. 36 of 8 September 1989.

  6 References to other national documents appearing

  Q Holder (s): Agent (s): Cabinet Regimbeau, Martin, Schrimpf,

Warcoin and Ahner.

  (Vector register file, computer system for processing vectors using such a file and

  method of managing access to this file.

  A vector register file for a vector processing system 2047 includes the first - GROUP /. // //

  group 101 memory circuits, a second group 102 of l || - - | t | -L .. it ...

  memory circuits, which can be cyclically controlled 2 independently of the first group, a third group 103

  memory that can be controlled inde-

  from the first group and a fourth memory circuit group 104, which can be controlled in a controlled manner.

  cyclical independently of other groups, both pre-.

  wherein the first groups are formed by direct access static memories and the file is subdivided into a plurality of I-contexts fields usable for separate processes. 2047 4 0 Application in particular to mathematical calculations of /// // /// convolution and recurrence, os | .-. t, = -7 ff020

204714 127 "21

  N /Z/-/.../,./'.../x// 0, o04_, 1l] - 'I --- II' 'II IV ,,, te: L. D Sale of fascicles The present invention relates to vector register files for computer systems of the present invention.

vector processing.

  In a vector processing computer system, a vector register file is typically used to store vectors for computation purposes. The operations involved in such a system can be performed on one vector at a time. For example, an operation such as ADDITION VREG1, VREG2, VREG3 in a vector processing system can cause the addition of the first element located in the vector register 1 to the first element of the vector register 2 and the storage of the result in the first element of the vector register 3. The second element of the vector register i would, likewise, be added to the second element of the vector register 2 and the results would be stored in the second element of the vector register 3. Each element of the vector register 1 and the vector register 2 is treated in a similar way and is stored in

  the corresponding element of the vector register 3.

  To increase the processing speed in such computer systems, multi-access memories are usually used to form the vector register files. In such multi-access memories, the advantage is to be able to perform reading or recording at multiple locations of the memory during a single memory cycle. However, such multiple access memories have several disadvantages, typically including being more expensive from a design, construction, and price point of view than single access memories, being less readily available than memory devices. with one access and, typically,

  operate more slowly than the latter.

  Therefore, in accordance with an object of the present invention, it is desired to design a vector register file for a vector processing computer system, which uses single access memory cells, while providing the advantages of multiple access, from the speed point of view. Known vector processing systems typically use vector register files with relatively small dimensions. For example, a typical computer system referred to as CRAY and manufactured by Cray Research of Minneapolis, Minnesota, may have 8 vector registers, each of which has a length of 64 elements for a total of 512 elements. Other known systems typically use a volume of between double and quadruple of this volume of vector registers. Normally, the increased volume of the vector registers is achieved by increasing the length (which therefore goes to a length of 128 or 256) of each vector register. In accordance with a second object of the invention, it is desirable to increase the available amount of the volume of the vector registers and to obtain increased flexibility of use in the use and delivery of the vectors.

management of this volume.

  A third object of the present invention is to provide programming flexibility to execute instructions that apply to a vector and calculations that require access to a vector at any point. Examples of such calculations are presented in recurrence calculations

and / or cumulation.

  The present invention relates to a vector register file and methods for managing access to such a file. The present invention describes the use of static direct access memories (SRAMs) organized in a plurality of groups and operating at a speed of at least twice the system timing rate to simulate multiple access memories. The use of SRAM memories to form a vector register file provides a number of features of the invention. The use of SRAM memories makes it possible to arrange the computer system so that the file of the registers of the vectors has a relatively large volume. The latter can be subdivided into a plurality of context areas, each context area allowing to support the execution of a separate process. The use of such context areas avoids the need to transfer context information present in a vector register file to a disk when switching between processes. According to the present invention, a register for the system base, a register for the user base and a register for a system limit are used to ensure the use of a plurality of

contexts areas.

  According to the present invention, an addressing code is also used for addressing the context zones and allowing an optional addressing capability for individual elements or cells in

a vector.

  Other features and benefits of

  the invention will emerge from the description given above.

  after reference is made to the accompanying drawings, in which: - Figure 1 shows a block diagram showing groups of memories, of the type that can be used in the present invention; Fig. 2 is a block diagram illustrating a method of subdividing the memory groups into a plurality of vector registers according to the present invention; FIG. 3 is a block diagram illustrating a method for subdividing the memory groups into a plurality of context areas according to the present invention; FIG. 4 is a block diagram illustrating the use of registers of the system base, the user base and the system boundary in accordance with the present invention; FIG. 5 represents a schematic block illustrating the use of registers of the system base, the user base and the system limit and

  the use of variables shared between sub-

  programs according to the present invention; and FIG. 6 is a block diagram showing an operand descriptor of the type that can be used.

  in the context of the present invention.

  We will describe a file of records of

  vectors. In the following description, it is indicated

  many specific details such as a specific number of bits, specific dimensions, etc., so as to have a precise understanding of the present invention. But, the skilled person will appreciate that the present invention can be implemented without these specific details. In other cases, well-known circuits, structures and techniques have not been shown in detail to avoid unnecessarily obscuring the explanation of the

present invention.

VECTOR RECORD FILE

  The present invention describes the arrangement of a vector register file in a vector processing computer system, in the form of a

  plurality of random access memory (RAM) groups.

  In the context of this description, the term

  "group" is meant to refer to a set of memories,

  can be cyclically controlled independently.

  That is, each group-of the plurality of groups can be addressed independently during

the same clock cycle.

  This embodiment of the present invention will be described in more detail with reference to Fig. 1. This preferred embodiment uses four memory groups 101, 102, 103 and 104 for its vector register file. Each group 101, 102, 103, 104 has 2048 x 8 static direct access memories (SRAM) arranged in such a manner

  that a group can include 2048 64-bit elements.

  The present invention provides a logical equivalent of an 8-port memory by combining two techniques. First, the fact of arranging the memories into 4 groups or sets of memories, which can be cyclically controlled independently, allows

  to obtain the equivalent of a 4-port memory (ie

  say that a record can be executed in groups 0 and 1 during the same clock cycle as a reading from groups 2 and 3). Secondly, the present invention utilizes SRAM memories having access times at least twice as fast as the system clock rate, which effectively allows two accesses to each group during a cycle. given clock of the system. In the preferred embodiment, the system clock operates by delivering clock pulses separated by 120 nanoseconds (ns) from each other, which requires the use of SRAM memories having an access time equal to the maximum at 60 ns. It is better to use memories. SRAM with an access time of at least 35 ns. Therefore, each of the four groups can be accessed twice during a given clock cycle, which corresponds to an 8-port logical memory. Those skilled in the art will appreciate that these methods can be used either individually or in combination to achieve multi-access memory operation. It is furthermore obvious that a different number of groups can be used, memories having different sizes or memories having different speeds for obtaining more than 2 accesses during each interval of system clock pulses. , without leaving the frame

of the present invention.

  Among the advantages provided by the present invention using a vector register file constituted by SRAMs, mention may be made of the relatively low cost of such memories, the availability of SRAM memories from many manufacturers and the relative speed provided by current technology. SRAM memories. These advantages and other factors make it possible to use a vector register file having a size greater than that of the file.

  used in known systems of vector processing.

  The present invention describes several inventive techniques and features for management,

  and the use of the vector register file.

  According to a feature of the present invention, each group belonging to the plurality of groups may be subdivided into a plurality of vector registers. For example, with reference to FIG. 2, each of the groups 201, 202, 203 and 204 may be subdivided into a plurality of vector registers, such as, for example, the vector registers 210, 211, 212 and 213. In the particular example of FIG. , each group containing 2048 elements is subdivided into 64

  vector registers containing 32 elements.

  In fact, the groups 201, 202, 203 and 204 may be subdivided into any number of vector registers, up to a maximum value equal to p, where p is the number of elements in a group. Each vector register has p / n elements. The particular values of p and n can be chosen on the basis of a certain convention, depending on the trade-off between the advantages and disadvantages between having a large number of vector registers or vector registers containing large number of elements (i.e., a large length) in each particular case. The particular convention may be linked either to hardware devices or to

software processes.

  In the context of the practice of the present invention, a vector register can begin at any element within a group. The particular method of addressing the elements will be described more

  detailed with reference to Figure 6.

  In the preferred embodiment, a particular register of vectors may be designated using a group number and an offset. For example VR0 (0) can designate the first vector register in the group 0, VR0 (32) can designate the second vector register in the. group 0, in which the vector registers have a length of 32 elements, VR0 (64) can designate the third vector register in the group 0, etc. In another embodiment, the vector registers can be designated using a group number and a vector number. For example VR0,0 can designate a vector register located in group 0, number 0. The system can be sensitive to a conversion

  the vector number (i.e., 0) in one offset.

  VR0,1 may designate the second vector register in group 0. The system may be responsive to a conversion of the vector number (i.e., 1) to an offset. For example, if each vector register must have a length of 32 elements, the system must

  convert the vector number 1 to a shift 32.

  According to a third embodiment, vector registers can be designated using only a vector register number. The system can then be responsive to a conversion of the vector number into a group and an offset. For example VR0 can be converted to group 0, offset 0, VR1 can be converted to group 1, offset 0, VR2 can be converted to group 2, offset 0, VR3 can be converted to group 3, offset 0, VR4 can be converted to group 0, offset 32, and so on. Each of these different solutions provides compromises in terms of the portability of the program as a function of the conversion speed of the program.

number of vectors.

  ZONES OF CONTEXTS OF VECTOR REGISTERS

  In accordance with the present invention, as previously described, a comparatively large volume of vector registers is available. In general, it is not necessary to have the total volume of vector registers for any process considered alone. Therefore, according to another aspect of the present invention, the volume of vector registers can be subdivided into a plurality of areas of processing contexts. This system can then support a plurality of processes without the need for a process context data transfer from the register file This vectors to another recording medium, such as a disk,

  when switching between processes.

  With reference to FIG. 3, according to one embodiment, the groups 301, 302, 303 and 304 containing 2048 elements are subdivided into eight 310-317 context areas with a length of 256 elements in each group. Referring to FIG. 4, when executing a process, the system maintains a SBASE 410 base register. The SBASE 410 base register contains the offset or distance of the current context area from the start of the process. group (that is, from element 0). For example, if the current context is the context area 312 of Fig. 3, the SBASE 410 contains the value 512. If the SBASE 410 is used, the system can switch between the current process and a process. associated with context data located in a different context area, by means of a modification of the value contained in the SBASE register 10. When executing a process, the value contained in the SBASE register 10 is added to the offset value of any reference to the

memory of vectors.

  The SBASE register is further used to ensure that user processes do not refer to offsets below the assigned context area. In addition, using the SBASE register allows you to save a process regardless of the particular context area assigned to it. A process may be registered to be executed as if it were always executed in the first context 310. It will be apparent to the ordinary specialist that the vector register file can be subdivided into any number of contexts n between 1 and p, where p is the number of elements in a group. The number of elements in each context area is equal to p / n. The particular number n can be determined on the basis of a number of factors. It is also clear that it is possible to change the size of the context areas so that they do not have identical dimensions, allowing the use of a smaller context area for a relatively small process. and a larger context area for a relatively large process. The present invention further uses a second SLIMIT register 411 to indicate the last element, to which reference can be made, of the current context area. The SLIMIT 411 register is used to ensure that a process does not tend to refer to an item that is more than offset from the offset in that context area. Any reference to an element located in the vector register file is compared by reference to the SLIMIT register 411. If the reference concerns an element situated at a shift greater than the value contained in SLIMIT 411,

  it is inhibited and an error condition is indicated.

  The present invention further utilizes a third UBASE register 412, which allows further subdivision of the own context space of a particular process. Typically, the use system may be sensitive to manipulation of the UBASE and SLIMIT registers. A usage process allows you to manipulate the UBASE register. For example, the process may contain context data for individual subprograms located at fixed offsets with respect to a given value contained in the UBASE 412 register. The user sets the UBASE 412 register to the given value of this register when the execution of the subroutine. The subroutine can then refer to elements in the vector register file, by sending the offset value from the base register 412. The system calculates the actual offset within the file of the vector register file. vector registers by calculating (SBASE 410) + (UBASE 412) + (the given offset). With reference to FIG. 5, a method of jointly using context data and subroutines will be described. A process can set this context data anywhere within the limits of SBASE 510 and SLIMITE 511. The process can initially set its UBASE register at point 520, to refer to area 530 when executing db. a first subroutine. The process can change the setting of the UBASE register on point 521 to refer to area 531. Field 540 contains commonly used variables or other context information used in common, which can be referenced by

any subprogram.

  A second use of the UBASE register is to allow addressing of the entire base area of the system (area limited by SBASE and SLIMIT) by using a limited length address area. For example, assume that the area of the system base has a length of 512 elements and that an 8-bit address is used to address in this area. To address elements having relative offsets from 0 to 255 relative to SBASE, UBASE is set to 0. To address elements with relative offsets between 256 and 511 relative to SBASE, UBASE is set to 256 and the elements are addressed in accordance with

  (0 + 255) + UBASE (i.e. 256-511).

  Referring now to Figure 6, we will

  describe an operand descriptor 600 for instruc-

  of the preferred embodiment. The instructions of the preferred embodiment may comprise three operands: a vector register x (VRx), 601 (a) and 601 (b), a vector register y (VRy), 602 (a) and 602 (b) , and a z vector register (VRz),

603 (a) and 603 (b).

  A vector register can be addressed by entering a group number in bits 9 and 8 of the operand of the vector register and a value of

offset in the 7-0 bits.

  In the preferred embodiment, bits 9 to 5 of each operand of a vector register are inserted in the high rank half of word 610. Using bits 9 to 5 of the address, it is possible to address any set of four groups of the preferred embodiment using bits 9 and 8, and shifts within the groups can be addressed in multiples of 32. For example, a value 000012 in the bits 9 to 5 of an operand of a vector register would denote group 0, offset 32. A value 110102 would denote group 3, offset 64. As was previously described, the values contained in SBASE and

  UBASE are added to offsets.

  The subdivision of the address of the vector registers makes it possible to use a constant with 16 bits, instead of a constant with 32 bits, given with reference to a register of vectors. The ordinary specialist will see clearly that the particular organization in address bits can be modified without departing from the scope of the

present invention.

  In the present embodiment, a direct constant of 16 bits or less can be stored as part of an instruction. Therefore, by using only half the top rank of a word to memorize operand information, the present invention makes it possible to store the information of the operand in the instruction. This method saves a processing time, since there is no need to retrieve the information relating to

  the operand, separately from the instruction.

  It is desirable to address directly to a cell of a vector register or to use a vector register to store scalar variables, the lower half of the word 611 of the operand provides the remainder of the information of the address addresses. offset in bits 4 to 0 of the offset. It is also necessary to use bits 4 to 0 of the offset to allow overlapping of data for subprograms as described

  previously with reference to Figure 5.

  The addressability of the cell levels makes it possible to perform convolution calculations and recursive calculations. For example, using the addressability characteristic of cell levels, a convolutional calculation such as:

OD I = 1, 32

Y (I) = w (1) * x [U + 1]

+ W (2) * X [I + 2]

+ W (3) * X [I + 3]

  END In addition, the preferred embodiment of the present invention makes it possible to perform all operations including operations on individual elements of a vector, in an order compatible with an execution.

  sequentially. This allows, in combination with the address-

  cell level, to perform calculation recursion calculations directly and for example to calculate a

continuation of Fibonacci.

  Thus, in the foregoing, a vector register file and a method for managing

access to this file.

Claims (22)

  A vector register file for a vector processing computer system, characterized in that it comprises: a first group (101; 201; 301; 401) of memory circuits; and a second group (102; 202; 302,402) of memory circuits, which can be cyclically controlled from a   independently of said first group.   Vector register file according to claim 1, characterized in that said first group (101; 201; 301; 401) of memory circuits is   consisting of static memories with direct access.   A vector register file according to claim 1, characterized in that said first memory circuit group (101; 201; 301; 401) is constituted by eight 2048 x 8 direct-access static memories. Vector register file according to claim 1, characterized in that it further comprises: a third group (103; 203; 303; 403) of memories, which can be cyclically controlled independently of said first group (101 201; 301; 401) of memories and said second group (102; 202; 302; 402) of memories; and a fourth group (104; 202; 304; 404) of memory circuits, which can be cyclically controlled independently of said first group (101; 201; 301; 401) of memory circuits, said second group (102; 202 302; 402) memory circuits and the third   group (103; 203; 303; 403) of memory circuits.   A vector register file according to claim 1, wherein each of said memory circuits (101,201,301,401; 102,202,302,402; 103,203,303,403) is accessible at least twice during the cycle time. clock of the system.   A vector register file according to claim 5, characterized in that said duration of the system clock cycle is equal to about 120 ns and that access to said memory circuits (101,201,301,401; 102,202,302,402; 103,203,303,403) can be done during   a duration of not more than 60 ns.   A vector register file according to claim 5, characterized in that said duration of the system clock cycle is about 120 ns and that access to said memory circuits (101,201,301,401; 102,202,302,402; 103,203,303,403) can be to be carried out during at least approximately 35 ns.   8. Computer processing system for vec-   carriers comprising a vector register file, characterized in that it comprises a clock of the system having a cycle time equal to n, and a plurality of memory circuits (101,201, 301,401; 102,202,302, 402; 103,203,303,403), having a access time equal to at least about n / p, p being equal at least 2.   A vector processing computer system according to claim 8, characterized in that n is equal to about 120 ns and p is equal to the maximum of about 60 ns.   10. Computer system for processing vectors, characterized in that it comprises: a vector register file, a register (410) of the system base, used to store a value of the system base, which is added to a offset value for addressing said file of vector registers.   11. Computerized treatment system for vec-   in accordance with claim 10, characterized in that it further comprises a limit register (411), which serves to store a limit value which is compared to the sum of said base system value and said offset, and a condition of error being reported in the case o   said sum is greater than said limit.   12. Computerized treatment system for   The apparatus according to claim 10, further comprising a user base register (402) for storing a value of a user base, which is added to said offset value and said value of the system base when addressing   of said vector register file.   13. Computerized treatment system for vec-   in accordance with claim 10, characterized in that said value of the system base is modified when said computer system for processing vectors modifies active processes.   14. A method of addressing a vector register file in a vector processing computer system comprising this file and a register (410) of the system base for storing a value of the system base, characterized in that it includes the steps of: (a) adding an offset value to said value of the system base so as to obtain a sum; (b) addressing said vector register file with said sum; and (c) said computer processing-vector system modifying its active process; (d) modifying the value of said register (410) of the system base, in response to said modification of the processes. 15. The method of claim 14, implemented in a computer system for processing vectors further comprising a register (412) of a user base, for storing a value of a user base, characterized in that further includes the step of adding the value of said user base to said sum -before addressing said file of vector registers.   16. The method of claim 14, intended to be implemented in a computer system for processing vectors further comprising a limit register (411) for storing a limit value, characterized in that it further includes the step of comparing said sum with said limit value and producing an error condition, in the case where said sum is greater than said limit value before   addressing said vector register file.   17. The method of claim 16, characterized   in that it further includes the step of modifying said limit value in response to said change process.   18. Method for subdividing a file of   vector registers of a plurality of vector registers (210, 211, 112, 213) in a vector processing computer system containing this vector register file including addressable elements, characterized by including the steps of: ) determining a value n indicating a desired number of vector registers, and (b) logically dividing said vector register file into said plurality of vector registers (210,211,212,213), each of said plurality of vector registers   vectors having a length equal to p / n elements.   19. The method of claim 18, characterized   rised in that p is 2048.   A method for storing operands in a vector processing computer system comprising a vector register file and using instructions requiring a plurality of operands comprising addresses within said vector register file, characterized in that it consists in: storing a first plurality of bits of said address for each of said operands in a first half of a word, and storing a second plurality of bits of said address of each of said operands in a second half of that word.   21. The method of claim 20, characterized   in that said plurality of bits includes bits 9   at 5 of said address of each of said operands.   22. The method of claim 21, characterized   in that said second plurality of bits includes bits 4 to 0 of said address of each of said operands. PL, I / 6 2047 2046 2, / 127 63 2 1 0 GROUP.,../. 1010 Ill "'lt"' ll "'l V111X4 on' 2048 2047 2046 \ / 127.63 2 1 0 /// * .. // <.//.*..///, Ill .. se .. ,, 102 - 1: 11 * 1 * TI TITV / 7., _2048 2047 2046 \ X / 127 63 2 1 0 - // /, // //// i 103 2 II ... The I. ..] I .. I. * - the, - "2048 2047 2046 4 2 127 63 21 0 //..//X.//.../// 104 -311 - i 64 - "2048. PL, II / 6 2047 2015 95 63 31 0 / /, ',' / / GROUP / 201 --0: 213 * 212 12 21 0 vZ x., -.- ,, _-., VR 0, 31 VR 0.2 VR 0, I VR 0, 0   VR 0, (1984) VR O (64) VR 0 (64) VR 0 (0) VRI, 31 VRI, 2 VRI / VR ,, 0 /. . / 2 3 R /. v 202 --- 1: 1 * To I I I IR 3, 31 V 3.2 3.1 3.0II I VR 1,31 VR1,2 VRl, I VR 1,0 / ,, ,, / // * / / / R / À 3, / / / 203 "-, 2: E I * lÀÀ | VR 2,31I VR 2,2VR 2.1 VR 2.0 / AT/, / , ' // /, ',',', 'AT 204, -3: I I I I - VR 3,531 VR 3,2 VRS, I VR 3,0 PL, III / 6 1792 1536 1280 1024 768 512 256   E 2047 \ 1791 \ 1535 \ 1279 \ 1023 \ 767 \ 511 \ 255 \ GROUPE Im / I I I I I I I Io I -I I, I, I, I I I I I I I I 1 I1 301 _-- O: I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I   I 303-21 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I, I I II / 1 1 1 II II I 1   r-l, l. I - I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I II I I I I I II BACKGROUND CONTEXT CONTEXT BACKGROUND 7 I I 3 I 3   CONTiLXTECON XTE CONTENTS CONTEXT '317 6 4 2 o 315 313 31311 31 316 314 312 310 I I I.- 128-. I I I I I I I. III GROUP   aO: I I I I I I I t 2: '* I HAVE - I I I TO I 1 1 I.- tt t I I I I I 4 I S BASEUE UBSESLSMITE 410 - 412 '-411 r co CE / PE CONTEXT OF THE PROCESS 530,531 1 * - 128-- I I I I I I I1 GROUP I I I I 0: .. I I I I I II 1: .01 I I IS ! I II I 1 i 1 1 i I I I 3 :. * I I I I I I I there is 520 VARIABLES I | I 1 IN COMMUNI SBASE \ - 540 SLIMITE 51J lU ANTERIOR BASE 511 DETECTION-PROGRAM CONTEXT1 PREVIOUS I 521- & CONTEXT OF SUB-PROGRMAME CURRENT CURRENT LUBASE 610 61'1   31 30 29 28 26 25 24 23 21 20 19 18 16 15 14 10 9 5 4 0 600 1 II 1   I ÉDCALAGE 'ÉDKCALAGf 1 SHIFT   1D <CALAGDCAL ID DECALAG DECALAGEDSTANDINGDALAGE -   GROUPI <7..5> GROUPI <7 5> ROUPE <7..5> - 4> <4>   <9.8> 1 <9..8> <9..8>. <4..O> <4 .. 0> <4 .. O>   III o-> ACVR x <9., 5> VRy <9..5> VR z <9..5> VR X <4..0> VRy <4..o0> VR z <4 .. 0> <o> _ / _ / I   601 (a) 602 (0) 603 (a) 601 (b) 602 (b) 603 (b) ro os (0% co -.