JPS6326784A - Image connection processor - Google Patents

Abstract

PURPOSE:To reduce a circuit scale, and to make a device small in size by using a wired OFF circuit for a selecting circuit of a label number of a connecting component. CONSTITUTION:In a line buffer 31, label numbers of a binary image data before one scan and each image data are stored. The binary image data of an aimed picture element P is stored in an FF 33. Binary image data of picture elements A-C being adjacent to the upper left part, the upper part and the left part of the aimed picture element P, and its label numbers are held in latching circuits 34-36. Output signals of the FF 33 and the latching circuits 34-36, and a time division pulse signal from a control circuit 30 are applied to a ROM 37 being a connection detecting means, and in accordance with it, the ROM 37 outputs data D0-D8. At the time of putting a new label number to the aimed picture element P, a black label counter NNH 38 executes a count operation by D1, and it is outputted to a label bus 41 by a '0' output of the data D8. Also, outputs of the latching circuits 33-34 are outputted by a '0' output of D2-D4 from 3-state gates 42-44.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an image connection processing device that detects connected components of binary images.

(Prior Art) Labeling circuits have been used in the field of character extraction and image measurement in character recognition. This labeling circuit extracts connected components from image data and assigns one label number to each connected component, and is configured as shown in FIG. 8, for example.

That is, the line buffer 1 stores the binarized image data of the previous line ("1", "O") and the label of each pixel corresponding thereto. Then, the image data of the pixel of interest P is stored in the flip-flop circuit 2 (P), and each adjacent pixel A adjacent to the upper left, upper and left side of the pixel of interest P
, B, C and the label number are sent to the latch circuit 3,
Store in 4.5. When image data is stored in these flip-flop circuits 2 and latch circuits 3 to 5, it is possible to determine whether or not a pixel of interest is connected to an adjacent pixel and the position of the connected pixel based on the image data of these four pits. is given as the address of ROM 6. ROM6 is
Pixel of interest P is adjacent) concubine pixel A.

If it is connected to either one of B or C, the label number of the connected adjacent pixel is selected via the multiplexer 7. Furthermore, if there is no connected pixel, the value of the white label counter 8 or black label counter 9 in which a newly assigned label number is stored is selected. As a result, the same label number is assigned to the connected components and input to the connection processing unit 1o. In the concatenation processing unit 1o, processing speed is increased by performing concatenation of label numbers in parallel or in a vibrating manner.

However, in the conventional image concatenation processing device described above, the use of the multiplexer 7 for selecting the label number
The number of C's required is equal to the number of bits of the label number. Therefore, if a large number of connected components exist in the target screen, a multiplexer using a large number of ICs is required.

Furthermore, many registers were required to perform parallel processing and pipeline processing in the concatenation processing section. For this reason, conventional image processing apparatuses have had the disadvantage that the circuit size increases as the number of pixels on the screen increases.

(Problems to be Solved by the Invention) As described above, in the conventional image concatenation processing device, especially when processing an image with many connected components, an increase in circuit scale is unavoidable, and the device is small. There was a problem with lower prices.

The present invention has been made to solve such problems, and an object of the present invention is to provide an image concatenation processing device that can reduce the circuit scale and contribute to miniaturization and cost reduction of the device.

[Structure of the Invention] (Means for Solving the Problems) The present invention is an image linking processing apparatus configured as follows, and is particularly characterized by the configuration of the selection means.

That is, the image linking processing device according to the present invention is first provided with first to third holding means. The first holding means holds binary image data of the pixel of interest. The second holding means holds second field image data of neighboring pixels adjacent to the pixel of interest and their label numbers. The third holding means holds a newly assigned label number. and detecting a connection between the pixel of interest and a neighboring pixel by a connection detection means based on the binary image data held by the first and second holding means,
Based on the detection result of the connection detection means, the second and third
In the image concatenation processing device, the selection means selects a label number to be given to the pixel of interest from the holding means of the pixel of interest. The label number output from the second and third holding means is selectively input based on the detection result of the connection detecting means.

(action).

The label numbers held in the second and third holding means are selectively input to the wired-OR circuit at a certain timing based on data from the connection detection means. therefore,
The output of the wired-OR circuit can then be used as it is as the selected label number. In this case, even if there are a large number of connected components, the circuit scale will hardly increase.

(Example) An embodiment of the present invention will be described below.

FIG. 1 is a diagram showing the configuration of an image processing apparatus according to an embodiment of the present invention.

This i-position is roughly divided into a connected component extraction section 21 that detects the presence or absence of pixel connections, their directions, etc., and a connection processing section 22 that integrates and organizes the labels of the detected connected components.

The connected component extraction unit L1 is configured as follows.

That is, the control circuit 30 is a circuit that instructs the processing timing of this device, and controls P1 to P4, W1 as shown in FIG.
Outputs a 4-cycle time-division pulse of ~W4.

The line buffer 31 stores the binary image data before scanning (data of '0' and '1') and the label number of each image data in pairs, and reads them out via the AND circuit 32. The enable state of is set. Here, it is assumed that a label number is added to a black pixel, and a label number is not added to a white pixel.

The binarized plane (image data) of the pixel of interest P is stored in a flip-flop (hereinafter referred to as rFFj) 33, which is a first storage means. The binary image data of A, B, and C and label numbers are stored in latch circuits 34, 35, and 36, which are second holding means.
are held respectively. FF33 and latch circuit 34.
35 is held at the timing of Wl, and the latch circuit 36
is held at W4, which is earlier than this.

These FF33. A total of 4 bits of binary image data held in the latch circuits 34, 35, and 36 are given as lower addresses AO to A3 of the ROM 37, which is a connection detection means. Further, time division pulses P2 to P4 are given to the upper address A4-80 of this ROM 37.

Therefore, different addresses are given to the ROM 37 from P2 to P4, and accordingly different data DO
~D8 is output. The data DO to D8 are used as count pulses for each counter, gate enable pulses, memory write pulses, etc., which will be described later.

A black label counter (hereinafter referred to as rNNHJ) 38, which is a third holding means, is connected to the oo and oi terminals of the ROM 37.
and white label counter (hereinafter referred to as rNNLJ) 3
are connected. The following label numbers are held in the NNH38. That is, when the pixel of interest is black and all adjacent pixels are white, it is necessary to give a new label number to the pixel of interest P as indicating the starting point of the connected component, but this new label number is not assigned to the above NNH38. The label number to be used is stored. On the other hand, a new label number for a white pixel is stored in the NNL 39, but it is not used when assigning a label number only to this black pixel.

These NNH38 and NNL39 perform counting operations according to changes in data Do and D+ in the ROM 37, and their outputs are normally in a high impedance state, and data D7.
The "0" output from D8 enables the enable state and is output to the label bus 41. In addition, three latch circuits 34
The outputs from ~36 are the three-state gates 42, 43.4
4 separately to the label bus 41.

The outputs of these three gates 42 to 44 are also normally in a high impedance state, and the outputs of the ROM 37 02, D
3, when the D4 output becomes o'', it becomes an enable state.In other words, these NNH38°NNL39 and gate 4
2 to 44 are wired-OR connected to the label bus 41, and this wired-OR connection and the enable pulse constitute a label selection means. The label number output to this label bus 41 is W4
The signal is input to the line buffer 31, latch circuit 36, and connection table of the connection processing section 22 at the timing of .

The concatenation processing section 22 includes a control counter 51, two memories 52 and 53, a concatenation label integration section 54, and a concatenation table 55.

Two memories 52 and 53 store pixel C adjacent to pixel P of interest,
B is connected and adjacent Ig: pixel B.

When the label numbers of C are different, in order to determine which label number should be assigned to the pixel of interest P, the label numbers of the neighboring multi-pixels B and C are held on both sides. The label number of the adjacent pixel B is stored in the first memory 52, and the label number of the adjacent pixel B is stored in the second memory 53. The concatenated label integrating unit 54 is for consolidating the different label numbers of the same address stored in these two memories 52 and 53 and storing them in the concatenated table 55. Note that the control counter 51 is connected to these memories 52.5.
3 and the address of the connected label integration unit 54.

In the image linking device configured as described above, the pixel of interest P and its adjacent pixels A, B, and C are arranged as shown in d1 to d16 in FIG.
In each case, the following label number is given to the pixel P of interest.

That is, first, di, d2. d3. d5. d6゜d12
．． In the cases of d13 and (j15, the pixel of interest is "0°"
(white), so no label number is assigned.

In the case of di, d14, the pixel of interest P is adjacent pixels B, C
Since is white, it is taken as the starting point of the connected component.

Note that in d14, the adjacent pixel A is in a so-called "four-in-a-row" relationship, so in this case, it is considered that they are far apart. Therefore, a new label number held in the NNH 38 is assigned to the pixel P of interest.

In the case of d7, dlo, and di6, since the pixel P of interest is connected to the adjacent pixel C, a label number within the latch circuit 36 is assigned.

In the case of C18, dll, since the pixel P of interest is connected to the adjacent pixel B, the label number held in the latch circuit 35 is assigned.

In the case of d9, the pixel P of interest is adjacent pixel B and adjacent pixel C.
It is conceivable that the adjacent pixels B and C have different label numbers. Therefore, in this case, the label number of the adjacent pixel C is provisionally assigned, and the label number of the adjacent pixel C1B is held in the memories 52 and 53, respectively, as described above, and is used for later integration processing.

FIG. 4 is a diagram showing an example of binary image data.

When such an image is input, the pattern shown in Fig. 3 d15 is detected for a while by raster scanning, and then the pattern shown in Fig. 4 (a) is detected.
) is detected at time 01 of di. At this point, the latch circuit 36 has already stored the binary image data of 'O' and the label number.The line buffer 31 enters the read enable state with the pulse of Pl, and the
The binary image data of the pixel P of interest is stored in the FF 33 with the pulse of l, and the binary image data and label numbers of the adjacent pixels A and B are stored in the latch circuits 34 and 35.

When the P2 pulse is input to the ROM 37, the address of the ROM 37 becomes (01100) as shown in the first stage of FIG.
10). At that time, the data in the ROM 37 becomes <111111100) as shown in the figure.

When the P3 pulse is input to the ROM 37, the address of the ROM 37 is changed to (101001) as shown in the second stage of the figure.
0). At that time, the data in the ROM 37 becomes (111111101) as shown in the same road.

As a result, the lower bit OO of the data rises to "1", so the NNH 38 counts up.

When the P4 pulse is input to ROM 37, ROM 37
The address is (11000) as shown in the third row of the same figure.
10). At that time, the data in the ROM 37 becomes (011111100) as shown in the same road.

As a result, the top pit D8 changes to a hole, so
The NNH 38 is enabled and output to the label bus 41. At this time, the W4 pulse is then applied to the line buffer 31. Since it is given to the latch circuit 36 and the connection table 55, these are used as the label of the pixel P of interest NNH3.
The contents of 8 are stored. The above procedure is e2. e3. e
The same applies to 5.

Next, when the state of e4 in FIG. 4(a) is detected, the FF 33 and the latch circuit 34 are
~36 data are held respectively, and the P2 pulse is R
When input to the OM 37, the address of the ROM 37 becomes (0411010) as shown in the fourth stage of FIG.

At that time, the data in ROM 37 is as shown in the same way (
111111100). P3 pulse is ROM13
7, the address of the ROM 37 is uni (1011010) tonal as shown in the fifth row of the figure. At the time of recording, the data in ROM37 remains unchanged and remains (111111110) as shown in the same country. P4 pulse is RO
When input to M37, the address of the ROM 37 becomes (1101010) as shown in the sixth row of the figure.

At that time, the data in ROM37 will be shown to the country (1
11111000). As a result, data D2 becomes “
Since the signal changes to 0, the gate 42 becomes enabled and the label number held in the latch circuit 35 is output to the label bus 41. At this time, the W4 pulse is then applied to the line buffer 31. Latch circuit 36 and connection table 55
, the label number of the adjacent pixel B is stored as the label of the pixel P of interest.

Similarly e6. If e7 pattern is detected, P2
When the pulse is input to the ROM 37, the address of the ROM 37 is changed to (0111011) as shown in the seventh stage of FIG.
). At that time, the data in the ROM 37 is (110111011) as shown in the same page. Therefore, the gate 42 is enabled, and the contents of the latch circuit 35 are output to the label bus 41 and stored in the memory 53. When P3 pulse is input to ROM37, ROM3
The address of 7 is (1041) as shown in the 8th row of the same figure.
011). At that time, the data in the ROM 37 will be (111010111) as shown in the same page. As a result, the gate 43 becomes enabled and the latch circuit 36
The label number within is output to the label bus 41 and held in the memory 52. When the P4 pulse is input to the ROM 37, the address of the ROM 37 becomes (1101011) as shown in the ninth stage of the figure. At that time, the data in ROM37 is as shown in the same country (111110111')
becomes. As a result, the output of the label number held in the latch circuit 36 onto the label bus 41 is maintained, so that the label number is applied to the line buffer 31.degree. latch circuit 36 and the connection table 55 by the subsequent ~v4 pulse.

If such operations are continued, label numbers as shown in FIG. 4(b) are held in the concatenation table 55.

In this state, different label numbers 1, 2, and 4 are assigned to the same connected component, so it is necessary to unify these to the same label number. Therefore, by the following operations,
Label integration processing for these connected components is performed.

First, the contents of the memory 52 are shown in f1 in FIG.
The contents are as shown in f2 in the same figure, and these both mean label numbers given to the same connected component. On the other hand, the concatenation table 55 stores four label numbers as shown in f3 in the figure. The data in the two memories 52 and 53 described above are compared by the label integrating unit 54 and integrated into the one with the smaller label number. At this time, f3
In order not to lose the connection between addresses 2 and 4, save 2'', which was the content of address 4 temporarily, and re-create the content of address 4 ``1'' and the content of address 2 ``2''. , and insert 1'' into address 2. As a result, the contents of the concatenation table 55 are finally integrated and rearranged to become "1" and "3" as shown in f4 of the same figure.

Although the label number is determined by the above procedure, in general image measurement, in addition to the image connection process described above, it is necessary to know the x and y coordinates of the start point and end point of each connected component, their area, etc. In this case, for example, as shown in FIG.
Give to 2.

The x, y coordinates and area of the start point and end point of each label are measured by the catalog creation circuit 62 and the two-dimensional counter 63 during scanning, and are compared, added, and rearranged in synchronization with the connected label integration unit 54. Ru. x, y of the concatenated and integrated image
! The minimum straightness (!!8 points), maximum value (end point), and area value of the target are stored in the internal memory of the catalog creation circuit 62.

As described above, according to this embodiment, since the wired-OR circuit is employed as the selection means, the circuit configuration of the selection means can be simplified. Moreover, in this embodiment, one process is performed by time-sharing processing of four cycles, so there is no need to perform parallel processing in the concatenation processing section. Therefore, this also simplifies the circuit configuration. I can figure it out.

In the above embodiment, three state gates were arranged at the outputs of the three latch circuits, but if a latch circuit with an enable terminal is used, each gate can be connected by providing an address latch at the address input section of the ROM. Since this can be omitted, the configuration can be further simplified.

Further, in the above explanation, the connection of black pixels was investigated, but the M word processing of white pixels can be similarly performed using NNL. Further, even if the pixels to be extracted are 2×3 pixels, the 4-cycle concatenation process is similarly possible. Furthermore, the scanning direction is not limited to the horizontal direction, and scanning may be performed in the vertical direction.

[Effects of the Invention] As described above, according to the present invention, a wired-OR circuit is used as the selection circuit, and the label number to be given to the pixel of interest is selectively selected based on the output data of the connection detection means. is applied to the input of the wired-OR circuit, the configuration of the selection circuit can be simplified, and an image concatenation processing device that can be made smaller and lower in price can be provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an image concatenation processing device according to an embodiment of the present invention, FIG. 2 is a timing diagram showing control pulses in the device, and FIG. 3 is a diagram showing an input pattern in the device. 4 is a diagram showing an example of a crab field image input to the device, FIG. 5 is a diagram showing the contents of the ROM in the device, and FIG. 6 is a diagram for explaining the operation of the connection processing section in the device. FIG. 7 is a block diagram showing an example of use of the same device, and FIG. 8 is a block diagram showing the configuration of a conventional inter-plane processing device. 1.31... Line buffer, 2.33... Flip-flop circuit, 3-5, 34-36... Latch circuit, 6.37... ROM, 7... Multiplexer, 8
゜29... White label counter, 9, 38... Black label counter, 10.22... Concatenation processing unit, 21...
Connected component extraction unit, 30... Control circuit, 42-44...
・3-state gate. Applicant's Representative Patent Attorney Takehiko Suzue Figure 3 - Figure 2 Figure 4 Figure 6

Claims (3)

[Claims] (1) a first holding unit that holds binary image data of a pixel of interest; a second holding unit that holds binary image data of neighboring pixels adjacent to the pixel of interest and their label numbers;
a third holding means for holding a newly assigned label number; and connection detection for detecting a connection between the pixel of interest and neighboring pixels based on the binary image data held by the first and second holding means. and a selection means for selecting a label number to be given to a pixel of interest from the second and third holding means based on the detection result of the connection detection means, the selection means comprising: It is constituted by a wired-OR circuit that receives the outputs of the second and third holding means as input, and selectively outputs the label number from the second and third holding means based on the detection result of the connection detection means. An image concatenation processing device characterized in that it is an input device. (2) The selection means is configured such that when the connection detection means detects that a plurality of neighboring pixels having different label numbers among the neighboring pixels held in the second holding means are simultaneously connected to the pixel of interest, 2. The image concatenation processing apparatus according to claim 1, wherein the plurality of label numbers to be concatenated are time-divisionally input based on the detection results of the concatenation detection means. (3) A first timing for storing binary image data in the first and second holding means, a second and third timing for time-divisionally inputting the plurality of linked label numbers, and 3. The image concatenation processing device according to claim 2, wherein the image concatenation processing device performs time-division processing in the order of the fourth timing at which label numbers are assigned.