JP2003208627A5 - - Google Patents
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- JP2003208627A5 JP2003208627A5 JP2002006393A JP2002006393A JP2003208627A5 JP 2003208627 A5 JP2003208627 A5 JP 2003208627A5 JP 2002006393 A JP2002006393 A JP 2002006393A JP 2002006393 A JP2002006393 A JP 2002006393A JP 2003208627 A5 JP2003208627 A5 JP 2003208627A5
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Claims (11)
上記複数の処理モジュールはそれぞれ、
描画すべきプリミティブに関する情報を受けて、プリミティブがあらかじめインターリーブ状に分割された自モジュールの担当領域に含まれるか否かを判定する領域判定回路と、
上記領域判定回路により自モジュールの担当領域に含まれると判定されると、入力情報に基づいて担当領域に対する描画処理を行う処理回路と、を含む
画像処理装置。An image processing apparatus in which a plurality of processing modules share processing data, perform parallel processing, and draw in a memory,
Each of the plurality of processing modules is
An area determination circuit that receives information about a primitive to be drawn and determines whether or not the primitive is included in an area in charge of the module that has been divided into interleaves in advance;
An image processing apparatus comprising: a processing circuit that performs a drawing process on a responsible area based on input information when the area determining circuit determines that the assigned area is included in the assigned area of the own module.
請求項１記載の画像処理装置。The image processing apparatus according to claim 1, wherein the same information regarding the primitive to be rendered is broadcast to the area determination circuits of the plurality of processing modules.
請求項１記載の画像処理装置。The image processing apparatus according to claim 1, wherein information regarding different primitives to be drawn is supplied to the area determination circuits of the plurality of processing modules.
請求項１記載の画像処理装置。The image processing apparatus according to claim 1, wherein the processing circuits of the plurality of processing modules draw only pixels included in a region in charge of the module.
上記複数の処理モジュールの処理回路は、複数の単位領域における担当領域をスキャンしながらピクセルを発生する
請求項４記載の画像処理装置。The area assigned to each processing module is assigned to each area obtained by dividing a predetermined unit area by the number of the processing modules,
The image processing apparatus according to claim 4, wherein the processing circuits of the plurality of processing modules generate pixels while scanning the assigned areas in the plurality of unit areas.
上記複数の処理モジュールの処理回路は、複数の単位領域における担当領域をスキャンし、階層的に分割領域単位で同時にピクセルを発生する
請求項４記載の画像処理装置。The area assigned to each processing module is assigned to each area obtained by dividing a predetermined unit area by the number of the processing modules,
The image processing apparatus according to claim 4, wherein the processing circuits of the plurality of processing modules scan the assigned areas in the plurality of unit areas and generate pixels simultaneously in a hierarchically divided area unit.
上記複数の処理モジュールと上記複数のメモリモジュールとが一対一に対応しており、
上記複数の処理モジュールの処理回路は、自モジュールの担当する領域に対する処理結果のみを描画して対応するメモリモジュールに出力する
請求項１記載の画像処理装置。The memory includes a plurality of memory interleaved memory modules,
The plurality of processing modules and the plurality of memory modules correspond one-to-one,
The image processing apparatus according to claim 1, wherein the processing circuits of the plurality of processing modules draw only a processing result for an area handled by the module and output the result to a corresponding memory module.
上記複数の処理モジュールの処理回路は、複数の単位領域における担当領域をスキャンしながらピクセルを発生する
請求項７記載の画像処理装置。The area assigned to each processing module is assigned to each area obtained by dividing a predetermined unit area by the number of the processing modules,
The image processing apparatus according to claim 7 , wherein the processing circuits of the plurality of processing modules generate pixels while scanning the assigned areas in the plurality of unit areas.
上記複数の処理モジュールの処理回路は、複数の単位領域における担当領域をスキャンし、階層的に分割領域単位で同時にピクセルを発生する
請求項７記載の画像処理装置。The area assigned to each processing module is assigned to each area obtained by dividing a predetermined unit area by the number of the processing modules,
The image processing apparatus according to claim 7 , wherein the processing circuits of the plurality of processing modules scan the assigned areas in the plurality of unit areas and generate pixels simultaneously in a hierarchically divided area unit.
請求項１記載の画像処理装置。The area determination circuit outputs the input information to the processing circuit when it is determined that the primitive is included in the area in charge of its own module, and outputs the input information to the processing circuit when it is determined that the primitive is not included. The image processing apparatus according to claim 1, wherein the image processing apparatus is discarded.
上記複数の処理モジュールに対してインターリーブ状に分割して自モジュールが処理する担当領域を割り当てておき、
上記複数の処理モジュールに対して描画すべきプリミティブに関する情報を供給し、
各処理モジュールにおいて、プリミティブがあらかじめインターリーブ状に分割された自モジュールの担当領域に含まれるか否かを判定し、
自モジュールの担当領域に含まれると判定した場合に、供給された情報に基づいて担当領域に対する描画処理を行う
画像処理方法。An image processing method in which a plurality of processing modules share processing data, perform parallel processing, and draw in a memory.
Dividing the plurality of processing modules into an interleaved manner and assigning a responsible area to be processed by the module,
Supply information about primitives to be drawn to the plurality of processing modules,
In each processing module, it is determined whether or not the primitive is included in the area in charge of the own module divided in advance in an interleaved manner,
An image processing method for performing drawing processing on a responsible area based on supplied information when it is determined that the module is included in the assigned area of the own module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002006393A JP2003208627A (en) | 2002-01-15 | 2002-01-15 | Image processing device and method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002006393A JP2003208627A (en) | 2002-01-15 | 2002-01-15 | Image processing device and method therefor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003208627A JP2003208627A (en) | 2003-07-25 |
| JP2003208627A5 true JP2003208627A5 (en) | 2005-07-21 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002006393A Pending JP2003208627A (en) | 2002-01-15 | 2002-01-15 | Image processing device and method therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003208627A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7289125B2 (en) * | 2004-02-27 | 2007-10-30 | Nvidia Corporation | Graphics device clustering with PCI-express |
| JP3892016B2 (en) * | 2005-02-23 | 2007-03-14 | 株式会社ソニー・コンピュータエンタテインメント | Image processing apparatus and image processing method |
| JP4826922B2 (en) * | 2008-03-31 | 2011-11-30 | アイシン・エィ・ダブリュ株式会社 | MAP DISPLAY DEVICE, MAP DISPLAY PROGRAM, AND NAVIGATION DEVICE USING THE SAME |
| US9196031B2 (en) | 2012-01-17 | 2015-11-24 | SCREEN Holdings Co., Ltd. | Appearance inspection apparatus and method |
| JP5887145B2 (en) * | 2012-01-17 | 2016-03-16 | 株式会社Ｓｃｒｅｅｎホールディングス | Appearance inspection device |
-
2002
- 2002-01-15 JP JP2002006393A patent/JP2003208627A/en active Pending
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