JP2003208627A - Image processing device and method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing device and a method therefor capable of performing parallel processing irrespective of operation mode, realizing parallel processing having high execution efficiency without receiving the restriction for the number of pixels capable of being parallel processed, and improving the performance. <P>SOLUTION: The same triangle data are transmitted to each processing module 140-0 to 140-3 in parallel, and each processing module 140-0 to 140-3 receives the information related to the same triangle to discriminate whether it is included in regions RGN0 to RGN3 in charge of own module or not. Each processing module has region discrimination circuits 142-0 to 142-3 for outputting the input information to DDA circuits 143-0 to 143-3 if it is included in the regions RGN0 to RGN3, draws only pixel included in the regions RGN0 to RGN3 in charge of own module, and transmits it to corresponding memory modules 147-0 to 147-3. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus in which a plurality of arithmetic processing modules share processing data and perform parallel processing, and a method thereof.

[0002]

2. Description of the Related Art In recent years, a graphics LSI for executing three-dimensional computer graphics (3D Computer Graphics) at high speed with hardware has been remarkably popular, and this graphics LSI is standard in a game machine and a personal computer (PC). Many are equipped with.

FIG. 1 is a diagram conceptually showing a general image processing apparatus for performing graphics drawing.

The image processing apparatus 1 has a pixel generating section 2 and a plurality of (four in the example of FIG. 1) memory modules 3-0 to 3-3. This image processing device 1
Then, in the pixel generation unit 2, a unit figure such as a triangle primitive PM is rasterized to generate a plurality of pixels PX. Then, the generated pixel P
X is sent to the plurality of memory modules 3-0 to 3-3 via a connection circuit (not shown). At this time, the generated pixel is sent to the corresponding memory module according to the XY coordinate of the pixel.

As described above, the image processing apparatus 1 shown in FIG.
Distribute 0 to 3-3.

[0006]

By the way, the technological progress in graphics LSIs is rapid, and "Direct
While the functional expansion represented by “Vertex Shader” and “Pixe 1 Shader” adopted in “X” continues to be enhanced, it is desired to improve the performance at a pace higher than that of the CPU.

In order to improve the performance of the graphics LSI, it is possible to deal with it by raising the operating frequency of the LSI. However, the image processing device 1 described above is
Since it has a basic configuration in which a plurality of pixels generated in the system pixel generation unit 2 are distributed to a plurality of memory modules, it is not possible to obtain satisfactory performance simply by increasing the operating frequency of the LSI.

In order to improve the performance of the graphics LSI, it is effective not only to increase the operating frequency of the LSI but also to utilize a parallel processing method. The parallel processing methods are roughly classified as follows. The first is a parallel processing method by region division, and the second is a parallel processing method at the pixel level.

The above classification is based on the granularity of parallel processing, the granularity of area division parallel processing is rough, and the granularity of pixel level parallel processing is fine. The outline of each method is described below.

Parallel processing by area division Parallel processing by area division is a method of dividing a screen into a plurality of rectangular areas and performing parallel processing while allocating areas in charge of a plurality of processing modules.

Parallel Processing at Pixel Level Parallel processing at the pixel level is a fine-grained parallel processing technique. FIG. 2 is a diagram conceptually showing the parallel processing at the primitive level based on the method of parallel processing at the pixel level. As shown in FIG. 2, in the method of parallel processing at the pixel level, when rasterizing a triangle, pixels are arranged in a rectangular area unit called a pixel stamp (Pixel Stamp) PS composed of pixels arranged in a 2 × 8 matrix. Is generated. In the example of FIG. 2, a total of eight pixel stamps from pixel stamp PS0 to pixel stamp PS7 are generated. Up to 16 pixels included in these pixel stamps PS0 to PS7 are processed simultaneously. Since this method has a finer granularity, it is efficient in parallel processing.

However, in the case of parallel processing by the above-described area division, in order to efficiently operate the processing modules in parallel, it is necessary to classify the objects to be drawn in the respective areas in advance, and the load of scene data analysis is increased. heavy. In addition, drawing is not started after all the scene data for one frame has been gathered, but drawing is started immediately when object data is given. So-called immediate mode draws parallelism. I can't.

Further, in the case of parallel processing at the pixel level, since the size of primitives processed by graphics tends to be small, even if the size of the pixel stamp is increased, it is executed only by increasing the number of invalid pixels. Efficiency does not increase. Therefore, there is a limit to the number of pixels that can be processed in parallel by this method.

The present invention has been made in view of the above circumstances, and its purpose is to enable parallel processing regardless of the operation mode when a plurality of processing modules share processing data and perform parallel processing. An object of the present invention is to provide an image processing apparatus and method capable of realizing parallel processing with high execution efficiency without being restricted by the number of pixels that can be processed in parallel, and further improving performance.

[0015]

To achieve the above object, a first aspect of the present invention is an image processing apparatus in which a plurality of processing modules share processing data, perform parallel processing, and draw in a memory. , Each of the plurality of processing modules receives information about the primitive to be drawn,
An area determination circuit that determines whether or not a primitive is included in the area of its own module that has been divided into interleaves in advance. If the area determination circuit determines that the primitive is included in the area of its own module, the input information And a processing circuit for performing drawing processing on the area in charge.

According to the first aspect, the same information regarding the primitive to be drawn is broadcast to the area determination circuits of the plurality of processing modules.

Further, according to the first aspect, the area determining circuits of the plurality of processing modules are respectively supplied with information regarding different primitives to be drawn.

According to the first aspect, it is preferable that the processing circuits of the plurality of processing modules draw only the pixels included in the area in charge of the own module.

Further, according to the first aspect, the areas in charge of the respective processing modules are assigned respective areas obtained by dividing a predetermined unit area by the number of the processing modules, and the processing circuits of the plurality of processing modules have a plurality of processing circuits. Generate pixels while scanning the area in charge of the unit area.

Further, according to the first aspect, as the areas in charge of the respective processing modules, respective areas obtained by dividing a predetermined unit area by the number of the processing modules are respectively allocated, and the processing circuits of the plurality of processing modules have a plurality of processing circuits. The area in charge of each unit area is scanned, and pixels are simultaneously generated in a hierarchically divided area unit.

According to a first aspect, the memory includes a plurality of memory interleaved memory modules, and the plurality of processing modules and the plurality of memory modules have a one-to-one correspondence with each other. The processing circuit of the module draws only the processing result for the area in charge of its own module and outputs it to the corresponding memory module.

Further, preferably, the area determination circuit outputs the input information to the processing circuit when it is determined that the primitive is included in the area that the module is in charge of, and when it is determined that the primitive is not included. Discards the input information without outputting it to the processing circuit.

A second aspect of the present invention is an image processing method in which a plurality of processing modules share processing data, perform parallel processing, and draw in a memory, wherein the plurality of processing modules are divided in an interleaved manner. Then, the assigned area to be processed by the own module is allocated, and information about the primitives to be drawn is supplied to the above-mentioned plurality of processing modules. In each processing module, the assigned area of the own module in which the primitives are divided into interleaves beforehand. Is included in the assigned area of the module, and if it is determined that the included area is included in the assigned area of the own module, the drawing processing is performed on the assigned area based on the supplied information.

In the second aspect, the same information regarding the primitive to be drawn is broadcast to the plurality of processing modules.

In the second aspect, the plurality of processing modules are respectively supplied with information regarding different primitives to be drawn.

Preferably, each of the plurality of processing modules draws only the pixels included in the area in which the module is in charge.

Further, in the second aspect, as the areas in charge of each processing module, respective areas obtained by dividing a predetermined unit area by the number of the processing modules are respectively allocated, and in the plurality of processing modules, a plurality of unit areas are allocated. Generate pixels while scanning the area in charge.

Further, in the second aspect, as the areas in charge of the respective processing modules, respective areas obtained by dividing a predetermined unit area by the number of the processing modules are respectively allocated, and in the plurality of processing modules, a plurality of unit areas are allocated. The area in charge is scanned and pixels are simultaneously generated in a hierarchically divided area unit.

According to a second aspect, the memory is interleaved with a plurality of memory modules so that the plurality of processing modules correspond to the plurality of memory modules in a one-to-one correspondence. , Draws only the processing result for the area in charge of its own module and outputs it to the corresponding memory module.

According to the invention, for example, information about the same drawing primitive is broadcast to each processing module. Further, each processing module is associated with each interleaved memory module. Then, in the area determination circuit of each processing module, it is determined whether or not the primitive related to the input information is included in the area in charge of the own module, which is divided into interleaves in advance. In each area determination circuit, when it is determined that the primitive is included in the area of its own module, the input information is output to the processing circuit of its own module.
On the other hand, when it is determined that the input information is not included, the input information is not output to the processing circuit and is discarded. Then, in each processing circuit that has received the information regarding the drawing primitive, for example, only the pixels included in the area that the module owns are drawn based on the input information and sent to the corresponding memory module.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, in the present embodiment, a desired three-dimensional image for an arbitrary three-dimensional object model, which is applied to a personal computer or the like, is displayed on a CRT (Cathode).
A three-dimensional computer graphics system that displays at high speed on a display such as a Ray Tube will be described.

FIG. 3 is a system configuration diagram of a three-dimensional computer graphics system 10 as an image processing apparatus according to the present invention.

The three-dimensional computer graphics system 10 expresses a three-dimensional model as a combination of triangles (polygons) which are unit figures, draws these polygons to determine the color of each pixel on the display screen, and displays them on the display. This is a system for performing polygon rendering processing. In addition, in the three-dimensional computer graphics system 10, in addition to the (x, y) coordinates that represent the position on the plane, the z coordinate that represents the depth is used to represent the three-dimensional object, and this (x, y, z) An arbitrary point in the three-dimensional space is specified by the three coordinates.

As shown in FIG. 3, the three-dimensional computer graphics system 10 includes a main processor 11,
The main memory 12, the I / O interface circuit 13, and the rendering circuit 14 are connected via the main bus 15. The function of each component will be described below.

The main processor 11 uses the main memory 1 according to the progress status of the application, for example.
Read the required graphic data from 2 and perform coordinate conversion and clipping (Cli
Geometry processing such as pping processing and lighting processing is performed to generate polygon rendering data. The main processor 11 outputs the polygon rendering data S11 to the rendering circuit 14 via the main bus 15.

The I / O interface circuit 13 inputs motion control information or polygon rendering data from the outside as necessary, and outputs this to the rendering circuit 14 via the main bus 15.

The polygon rendering data input to the rendering circuit 14 includes (x,
y, z, R, G, B, s, t, q) data. Here, the (x, y, z) data indicates the three-dimensional coordinates of the vertices of the Polingo, and the (R, G, B) data indicates the brightness values of red, green, and blue at the three-dimensional coordinates, respectively. There is. In the (s, t, q) data, (s, t) indicates the homogeneous coordinates of the corresponding texture, and q indicates the homogeneous term. Where "s / q" and "t / q"
, Texture size USIZE and VSI respectively
The actual texture coordinate data (u, v) multiplied by ZE
Is obtained. The texture data stored in the graphics memory (specifically, the texture buffer) of the rendering circuit 14 is accessed using the texture coordinate data (u, v). That is, the polygon rendering data is the physical coordinate value of each vertex of the triangle, and the color and texture data of each vertex.

The rendering circuit 14 will be described in detail below.

As shown in FIG. 4, the rendering circuit 14
Is a DDA (Digital Differential Anarizer) setup circuit 141 as an initial setting calculation block for linear interpolation calculation, a plurality of (four in this embodiment) area determination circuits 142-0 to 142-3, and a linear interpolation processing block. Triangle DDA circuit (hereinafter, simply referred to as DDA circuit) 143-0 to 143-3, texture engine circuit 144-0 to 144-3, memory interface (I / F) circuit 145-0 to 145-3, dedicated memory I
It has a / F circuit 146, a graphics memory 147 composed of, for example, a DRAM, a CRT control circuit 148, a setup data broadcast bus 149, and a texture bus 150.

The rendering circuit 14 in this embodiment
In one semiconductor chip, a logic circuit and a graphics memory 147 for storing at least display data and texture data are mounted together.

In the rendering circuit 14, a plurality of, four in the present embodiment, four processing modules 140-0 to 140-3 are connected in parallel by the broadcast bus 149 to the output of the DDA setup circuit 141, and a plurality of processing modules are provided. The processing data is shared by 140-0 to 140-3, and the drawing areas assigned to each module are processed in parallel.

Then, the graphics memory 147 is
The processing modules 140-0 to 140-3 are divided into a plurality (four in the present embodiment) of memory modules 147-0 to 147-3 having the same function. In each of the processing modules 140-0 to 140-3, the memory modules 147-0 to 147-3 are interleaved in a processing size, for example, in a unit of 4 × 4 rectangular area,
Memory module 147-0 and processing module 140-
0, memory module 147-1 and processing module 14
0-1, the memory module 147-2 and the processing module 140-2, and the memory module 147-3 and the processing module 140-3 are in charge of one-to-one correspondence with each other, and the drawing system with respect to other memory modules. No memory access occurs.

FIGS. 5 and 6 are diagrams for explaining the basic concept of parallelization processing according to this embodiment. As shown in FIG. 5, in the present embodiment, the DDA setup circuit 1
Information (triangle data) regarding the same triangle primitive 41 is sent to each processing module 140-0 to 140-3 as a pixel generating means. As described above, the processing modules 140-0 to 140-3 are associated with the memory modules 147-0 to 147-3, respectively, and the areas RGN0 to RG in charge of the own module are in charge.
Only the pixels included in N3 are drawn and sent to the corresponding memory modules 147-0 to 147-3. Responsible areas RGN0 to R of each processing module 140-0 to 140-3
As GN3, a predetermined unit area (16 units in this embodiment) is used.
Each region obtained by dividing the (× 16 pixel rectangular region) by the number of processing modules (4 in this embodiment) is allocated. Each processing module 140-0 to 140
-3, as will be described later, generates pixels while scanning areas in charge in a plurality of unit areas.

For example, when a triangle as shown in FIG. 6A is drawn, pixels are conventionally generated in units of rectangular areas, but in the present embodiment, as shown in FIGS. 6B to 6E. In the area RGN0 to RGN in charge of its own module
Only pixels included in No. 3 are drawn and sent to the corresponding memory modules 147-0 to 147-3. In particular,
As shown in FIGS. 6A and 6B, the region RGN
The pixels contained in 0 are sent to the memory module 147-0. Similarly, as shown in FIGS. 6A and 6C, the pixels included in the region RGN1 are sent to the memory module 147-1. As shown in FIGS. 6A and 6D, the pixels included in the region RGN2 are sent to the memory module 147-2. 6A and 6A.
As shown in (E), the pixels included in the region RGN3 are sent to the memory module 147-3.

That is, in this embodiment, pixel level parallel processing is adopted from the viewpoint of the granularity of parallel processing. Since the parallelism at the pixel level has a limit on the degree of parallelism, a plurality of primitives are processed at the same time. In this embodiment, areas in charge of the same primitive are assigned to a plurality of processing modules 140-0 to 140-3 and processed in parallel. Further, in the present embodiment, the processing distribution can be directly connected to the processing modules 140-0 to 140-3 and the memory modules 147-0 to 147-3, and the number of wirings can be reduced and the size can be reduced. As a result, the design is facilitated and the wiring cost and wiring delay are reduced. As a result, in this embodiment, triangle primitive data is broadcast and pixels are transferred one-to-one, so that simple data transfer is realized. Further, even when a huge triangle is input, for example, efficient parallel processing is possible in each processing module.

On the other hand, each processing module 140-0 to 14
0-3 requires memory access to other processing modules for the texture read system. In this case, the texture engine circuits 144-0 to 144-3 of the processing modules 140-0 to 140-3 communicate with the dedicated memory I / D circuit 146 via the texture bus 150 as shown in FIG. Access the memory.

In this embodiment, the processing module 14
0-0 is the area determination circuit 142-0 and the DDA circuit 143.
-0, a texture engine circuit 144-0, and a memory I / F circuit 145-0. And DDA
Circuit 143-0, texture engine circuit 144-0,
The memory I / F circuit 145-0 constitutes a processing circuit.

Similarly, the processing module 140-1 has a region determination circuit 142-1, a DDA circuit 143-1, a texture engine circuit 144-1, and a memory I / F circuit 145-1. Then, the DDA circuit 143-
1, the texture engine circuit 144-1 and the memory I / F circuit 145-1 constitute a processing circuit. The processing module 140-2 includes an area determination circuit 142-2,
DDA circuit 143-2, texture engine circuit 144
-2, and a memory I / F circuit 145-2. Then, the DDA circuit 143-2, the texture engine circuit 144-2, and the memory I / F circuit 145-2.
A processing circuit is configured by Processing module 140-
3 is a region determination circuit 142-3 and a DDA circuit 143-
3, a texture engine circuit 144-3, and a memory I / F circuit 145-3. The DDA circuit 143-3, the texture engine circuit 144-3, and the memory I / F circuit 145-3 form a processing circuit.

The structure and function of each block of the rendering circuit 14 will be described below in order with reference to the drawings.

The DDA setup circuit 141 linearly interpolates the values of the vertices of the triangle on the physical coordinate system in the DDA circuits 143-0 to 143-34 of the respective processing modules 140-0 to 140-3 in the subsequent stage to perform linear interpolation. Before the color and depth information of each pixel inside the
(Z, R, G, B, s, t, q) data indicated by the polygon rendering data S11 input via
Perform a setup operation to find the difference between the sides of the triangle and the horizontal direction. Specifically, this setup calculation uses the values of the start point and end point and the distance between the start point and end point to calculate the variation of the value to be obtained when the unit length is moved. . DDA setup circuit 143
Sends information about the input triangle including the calculated variation data through the broadcast bus 149 to the area determination circuits 142-0 to 142-0 of the processing modules 140-0 to 140-3.
142-3 in parallel (output).

The function of the DDA setup circuit 141 will be further described with reference to FIG. As described above, the main processing of the DDA setup circuit 141 is the three vertices P0 (x0, y0) to which various kinds of information (color, texture coordinates) at each vertex that has fallen to the physical coordinates through the geometry processing of the previous stage. ), P1 (x1, y1), P
This is to calculate the variation within the triangle formed by 2 (x2, y2) and calculate the basic data of the subsequent linear interpolation processing. The drawing of a triangle is concentrated on the drawing of each pixel, but for that purpose it is necessary to find the first value at the drawing start point. The various information at the first drawing point is obtained by adding the value obtained by multiplying the horizontal distance from the vertex to the first drawing point by the horizontal variation and the value obtained by multiplying the vertical distance by the vertical variation. Become. Once the value on one integer grid inside the target triangle is found, the values at other grid points inside the target triangle can be found by integer multiples of the variation.

Each vertex data of the triangle has, for example, x and y coordinates of 16 bits, z coordinates of 24 bits, and RGB.
The color value is 12 bits (= 8 + 4), and the s, t, q texture coordinates are each 32 bits floating point value (IEEE format).

The DDA setup circuit 141
Are mounted by the ASIC method instead of the DSP structure, for example. Specifically, as shown in FIG. 8, an arithmetic unit group 14 in which a plurality of arithmetic units are arranged in parallel between the registers 1411-1 to 1413 arranged in multiple stages
It is configured as a full data path logic having 12-1 to 1412-3 inserted, in other words, a time parallel structure of a synchronous pipeline system.

The area determination circuit 142-0 of the processing module 140-0 receives the information about the triangle including the variation data by the DDA setup circuit 141 input via the broadcast bus 149, and the triangle is defined in advance. Area RG of own module
It is determined whether or not N0 is included, and if it is included, the input information is output to the DDA circuit 143-0 at the next stage. On the other hand, when the triangle is not included in the assigned area RGN0 of the own module in which the triangle is defined in advance, the area determination circuit 142-0 outputs the input information to the DDA circuit 143 of the next stage.
Discard without outputting to -0. This area determination circuit 142-0
Determines whether the assigned area RGN0 includes a triangle using the coordinates of the start point and the end point in the X direction and the Y direction included in the input information.

Area RG in charge of the processing module 140-0
N0 is an upper left region of a 2 × 2 matrix, as shown in FIG. 9, where a generation unit of 4 × 4 pixels per cycle for one processing module is used, for example. Therefore, the area determination circuit 142-0 determines whether or not a part of the corresponding triangle is (is included) in this assigned area RGN0.

10 and 11 show the area determination circuit 14
It is a figure for demonstrating notionally the 2 determination process, FIG. 10 has shown the example in case of 4 parallel, and FIG. 11 has shown the example in case of 8 parallel.

In the example of FIGS. 10 and 11, the triangle PM
11 and PM12 include no region included in the assigned region RGN0 of the processing module 140-0, the region determination circuit 142-0 is not included in the assigned region RGN0 of its own module in which a triangle is defined in advance. As input, the input information is discarded without being output to the DDA circuit 143-0 at the next stage.

In this case, the processing module 140-
Although the processing of the area determination circuit 142-0 of 0 is shown as an example, the processing of the area determination circuits 142-1 to 142-3 of the other processing modules 140-1 to 140-3 is performed in the same manner.

FIG. 12 shows each processing module 140-0.
Area determination circuits 142-0 to 142- in 140-3
It is a flow chart which shows judgment processing operation of 3. 12
As shown in, the area determination circuit 142 (-0 to 3) first determines whether or not the area in charge is included between the start point coordinates and the end coordinates in the X direction (ST1). When it is determined in step ST1 that the assigned area is not included, the area determination circuit 142 determines whether the assigned area is included between the start point coordinate and the end coordinate in the Y direction (ST2). . Then, when it is determined in step ST2 that the assigned area is not included, the input information is discarded without being output to the DDA circuit 143 (−0 to 3) of the next stage. On the other hand, step ST1 or step ST2
In, when it is determined that the area in charge is included,
The input information is output to the DDA circuit 143 at the next stage.

DDA circuit 1 of processing module 140-0
43-0 is linearly interpolated (z, R, G, B, s, t, in each pixel of the area in charge of the triangle using the variation data supplied from the area determination circuit 142-0.
q) Calculate the data. The DDA circuit 143-0 sets the (x, y) data of each pixel and the (z, R, G, B, s, t, q) data at the (x, y) coordinates to DD.
It is output to the texture engine circuit 144-0 as A data (interpolation data). That is, the DDA circuit 143-
0 performs rasterization based on the parameter data, for example, when the triangle is the area that it is in charge of. Specifically, when the triangle is the area in charge of itself, various data (z, texture coordinates, color, etc.) is rasterized. In this case, the generation unit is 4 × 4 pixels in one cycle per local module.

The function of the DDA circuit 143-0 is shown in FIG.
Further description will be given in connection with No. 3. As described above, the DDA setup circuit 141 at the preceding stage prepares the initial value at the drawing start point of the triangle and the inclination information of the various information described above in the horizontal direction (X direction) and the vertical direction (Y direction). The basic process here is to find the values on the integer grid contained within the given triangle,
The substance of the process is that the integral distance from the drawing start point is multiplied by the slope. Further, actually, rather than performing multiplication, a value of one pixel advanced in the horizontal direction (X direction) can be obtained by adding the amount of inclination in the horizontal direction. Therefore, as the calculation content,
This is a constant value addition process.

However, the DDA circuit according to this embodiment is
As shown in FIG. 1, the method of scanning is different from the case of performing a series of pixel generation processing. For example, when drawing a triangle as shown in FIG. 13A, pixels are conventionally generated in units of rectangular areas. That is, in the figure, the scanning is started in the X direction from the processing start point indicated by the broken line, and when it goes out of the triangle, it moves in the Y direction and scans again.
On the other hand, in the present embodiment, the processing start point is moved to the area in charge of the own module. Then, scanning is performed in the X direction. When it goes out of the triangle, it moves in the Y direction and scans in the X direction again. That is, in the present embodiment in which the assigned area is allocated and the parallel processing is performed, the width of movement of the scan itself is different from the conventional one. DDA of processing module 140-0
As described above, in the circuit 143-0, the upper left area of the 2 × 2 divided rectangular area is the area in charge. In this example, FIG.
As shown in (B), since the processing start point indicated by the broken line is the assigned area RGN0 of the own module, the DDA circuit 1
43-0 then moves in the Y direction (upward in the drawing),
Scan again in the X direction (to the right in the drawing).

Here, the processing module 140-
Although the processing of the DDA circuit 143-0 of 0 is shown as an example,
The processing in the DDA circuits 143-1 to 143-3 of the other processing modules 140-1 to 140-3 is performed in the same manner.

FIG. 14 shows each processing module 140-0.
DDA circuits 143-0 to 143-3 in 140-3
5 is a flowchart showing the determination processing operation of FIG. As shown in FIG. 14, the DDA circuit 143 (−0 to 3) first
The process moves from the processing start point to the assigned area closest to the end direction in each of the X and Y directions (ST11). Next, pixels are generated for a portion within the triangle (triangle) in the assigned area (ST12).

The texture engine circuit 144-0 is
Calculation processing of “s / q” and “t / q”, calculation processing of texture coordinate data (u, v), (R, G, from the texture buffer included in the graphics memory 147).
B) The data read processing and the like are performed by a pipeline method. Note that the texture engine circuit 144-0 cooperates with the texture engine circuits 144-1 to 144-3 of the other processing modules 140-1 to 140-3 to, for example, for 8 pixels located in a predetermined rectangle. Perform processing concurrently in parallel. Texture engine circuit 144-
0 is DD by the DDA circuit 144-0 of its own module
For the (s, t, q) data indicated by the A data, an operation of dividing s data by q data and an operation of dividing t data by q data are performed. In addition, the texture engine circuit 144-0 outputs the division results “s / q” and “t /
q ”to the texture sizes USIZE and V, respectively.
SIZE is multiplied to generate texture coordinate data (u, v).

Further, the texture engine circuit 144-0
Is the texture bus 150, the dedicated memory I / F circuit 14
6, a read request including the generated texture coordinate data (u, v) is output to the graphics memory 147, and the texture buffer included in the graphics memory 147 is output via the dedicated memory I / F circuit 146. By reading the stored texture data,
(R, G, B) data stored at the texture address corresponding to (s, t) data is obtained. The texture engine circuit 144-0 multiplies the read (R, G, B) data by the (R, G, B) data included in the DDA data from the preceding DDA circuit 143-0, respectively. To generate pixel data. The texture engine circuit 144-0 finally uses this pixel data as the color value of the pixel, and the memory I / F circuit 145.
Output to -0. In this case, the texture engine circuit 1
44-0 is the read texture data and (u,
v) The address is subjected to filtering processing such as 4-neighbor interpolation using the decimal part obtained at the time of calculation.

The texture buffer contains MIPM.
Texture data corresponding to a plurality of reduction ratios such as AP (multi-resolution texture) is stored. Here, which reduction rate of texture data is used is determined for each triangle by using a predetermined algorithm.

In the case of the full color system, the texture engine circuit 144-0 directly uses the (R, G, B) data read from the texture buffer. On the other hand, in the case of the index color system, the texture engine circuit 144-0 stores SR of the data of the color index table created in advance from the texture color lookup table (CLUT) buffer.
Transfer to a temporary storage buffer composed of AM etc.,
Using this color lookup table, (R, G, B) data corresponding to the color index read from the texture buffer is obtained. For example, when the color look-up table is composed of SRAM, when the color index is input to the address of SRAM, the actual (R, G, B) data appears at the output.

The memory I / F circuit 145-0 stores the z data corresponding to the pixel data input from the texture engine circuit 144-0 and the z data stored in the z buffer included in the memory module 147-0. The image drawn by the comparison and input pixel data is in front (viewpoint side) from the image written in the memory module 147-0 (display buffer) last time.
If it is located in front,
The z data stored in the z buffer is updated with the z data corresponding to the image data. In addition, the memory I / F circuit 145
-0 indicates (R, G, B) data in the memory module 14
Write to 7-0. The memory I / F circuit 145-0 is a memory module 147 that stores pixel data corresponding to a pixel address which is about to be drawn.
With respect to −0, the pixel data is read from the corresponding address in order to perform the modified writing, and the modified data is written back to the same address. When performing hidden surface processing, it is necessary to read the depth data from the corresponding address for modification writing to the memory block that also stores the depth data corresponding to the pixel address that is about to be drawn. If so, write back to the same address after modification. Further, the memory I / F circuit 145-0 is the texture engine circuit 14
Upon receiving the pixel-level processing result supplied by 4-0, the pixel data that has passed various tests in the pixel-level processing is drawn in the memory module 147-0.

The area determination circuit 142-1 of the processing module 140-1 receives the information about the triangle including the variation data by the DDA setup circuit 141 input via the broadcast bus 149, and the triangle is defined in advance. Area RG of own module
It is determined whether or not it is included in N1, and if it is included, the input information is output to the DDA circuit 143-1 at the next stage. On the other hand, when the triangle is not included in the assigned area RGN1 of the own module in which the triangle is defined in advance, the area determination circuit 142-1 outputs the input information to the DDA circuit 143 of the next stage.
Discard without outputting to -1. This area determination circuit 142-1
Determines whether the assigned area RGN1 includes a triangle by using the coordinates of the start point and the end point in the X direction and the Y direction included in the input information.

Area RG in charge of the processing module 140-1
N1 is the upper right region of the 2 × 2 matrix, as shown in FIG. 9, when the unit of generation is, for example, 2 × 2 pixels in one cycle per processing module. Therefore, the area determination circuit 142-1 determines whether or not a part of the corresponding triangle is (is included) in this assigned area RGN1.

For example, in the example of FIG. 10, a triangle PM11
Is not included in the assigned area RGN1 of the processing module 140-1 at all, the area determination circuit 142-1
Assumes that the triangle PM11 is not included in the assigned area RGN1 of the own module which is defined in advance, and discards the input information without outputting it to the DDA circuit 143-1 at the next stage. On the other hand, the triangle PM12 in the example of FIG.
Indicates that there is a region included in the assigned region RGN1 of the processing module 140-1, and therefore the region determination circuit 142-1
Indicates that the triangle PM12 is included in the area RGN1 of the own module, which is defined in advance,
The input information is output to the DDA circuit 143-1 at the next stage.

DDA circuit 1 of processing module 140-1
43-1 linearly interpolates (z, R, G, B, s, t, at each pixel of the area in charge of the triangle using the variation data supplied from the area determination circuit 142-1.
q) Calculate the data. The DDA circuit 143-1 uses the (x, y) data of each pixel and the (z, R, G, B, s, t, q) data at the (x, y) coordinates as the DD data.
It is output to the texture engine circuit 144-1 as A data (interpolation data). That is, the DDA circuit 143-
1 performs rasterization (Rasterization) based on the parameter data, for example, when the triangle is the area in which the triangle is in charge. Specifically, when the triangle is the area in charge of itself, various data (z, texture coordinates, color, etc.) is rasterized. In this case, the generation unit is 4 × 4 pixels in one cycle per local module.

The DDA circuit 143-1 uses the DDA setup circuit 141 in the preceding stage to set the first value at the drawing start point of the triangle, the horizontal direction (X direction), and the vertical direction (Y).
Inclination information of the various information described above in the direction) is prepared. The basic processing here is to obtain values on an integer grid included in a given triangle, and the substance of this processing is to multiply the integer distance from the drawing start point by the slope. Further, actually, rather than performing multiplication, a value of one pixel advanced in the horizontal direction (X direction) can be obtained by adding the amount of inclination in the horizontal direction. Therefore, the calculation content is a constant value addition process.

However, the DDA circuit according to the present embodiment is different from the case of performing a series of pixel generation processing as shown in FIG. 1 in the way of scanning. For example, when drawing a triangle as shown in FIG. 13A, pixels are conventionally generated in units of rectangular areas. That is, in the figure, the scanning is started in the X direction from the processing start point indicated by the broken line, and when it goes out of the triangle, it moves in the Y direction and scans again. On the other hand, in the present embodiment, the processing start point is moved to the area in charge of the own module. Then, scanning is performed in the X direction. When it goes out of the triangle, it moves in the Y direction and scans in the X direction again. That is, in the present embodiment in which a region in charge is allocated and parallel processing is performed, the width of movement of the scan itself is
Different from conventional. As described above, the DDA circuit 143-1 of the processing module 140-1 is in charge of the upper right area of the 2 × 2 divided rectangular area. In this example, FIG.
As shown in, the scan starts from the processing start point indicated by the broken line in the X direction and moves to the assigned area RGN1 of the own module.
Then, the DDA circuit 143-1 next moves in the Y direction (upward in the drawing) and scans again in the X direction (rightward in the drawing).

The texture engine circuit 144-1 is
Calculation processing of “s / q” and “t / q”, calculation processing of texture coordinate data (u, v), (R, G, from the texture buffer included in the graphics memory 147).
B) The data read processing and the like are performed by a pipeline method. The texture engine circuit 144-1 is the texture engine circuit 144-0, 144-2 to 14-3 of the other processing module 140-0, 140-2 to 140-3.
8 in cooperation with 4-3, for example located within a given rectangle
Pixels are processed simultaneously in parallel. The texture engine circuit 144-1 is the DDA of its own module.
DDA data from the circuit 144-1 indicates (s, t,
For q) data, an operation of dividing s data by q data and an operation of dividing t data by q data are performed. Further, the texture engine circuit 144-1 multiplies the division results “s / q” and “t / q” by the texture sizes USIZE and VSIZE, respectively, to generate texture coordinate data (u, v).

Further, the texture engine circuit 144-1
Is the texture bus 150, the dedicated memory I / F circuit 14
6, a read request including the generated texture coordinate data (u, v) is output to the graphics memory 147, and the texture buffer included in the graphics memory 147 is output via the dedicated memory I / F circuit 146. By reading the stored texture data,
(R, G, B) data stored at the texture address corresponding to (s, t) data is obtained. The texture engine circuit 144-1 multiplies the read (R, G, B) data by the (R, G, B) data included in the DDA data from the preceding DDA circuit 143-1. To generate pixel data. The texture engine circuit 144-1 finally uses the pixel data as the color value of the pixel, and the memory I / F circuit 145.
Output to -1. In this case, the texture engine circuit 1
44-1 includes the read texture data and (u,
v) The address is subjected to filtering processing such as 4-neighbor interpolation using the decimal part obtained at the time of calculation.

The texture buffer contains MIPM.
Texture data corresponding to a plurality of reduction ratios such as AP (multi-resolution texture) is stored. Here, which reduction rate of texture data is used is determined for each triangle by using a predetermined algorithm.

In the case of the full color system, the texture engine circuit 144-1 directly uses the (R, G, B) data read from the texture buffer. On the other hand, in the case of the index color system, the texture engine circuit 144-1 incorporates the data of the color index table created in advance from the texture color lookup table (CLUT) buffer into an SR.
Transfer to a temporary storage buffer composed of AM etc.,
Using this color lookup table, (R, G, B) data corresponding to the color index read from the texture buffer is obtained. For example, when the color look-up table is composed of SRAM, when the color index is input to the address of SRAM, the actual (R, G, B) data appears at the output.

The memory I / F circuit 145-1 stores the z data corresponding to the pixel data input from the texture engine circuit 144-1 and the z data stored in the z buffer included in the memory module 147-1. The image drawn by the comparison and input pixel data is in front (viewpoint side) from the image written in the memory module 147-1 (display buffer) last time.
If it is located in front,
The z data stored in the z buffer is updated with the z data corresponding to the image data. In addition, the memory I / F circuit 145
-1 indicates (R, G, B) data in the memory module 14
Write in 7-1. The memory I / F circuit 145-1 includes a memory module 147 that stores pixel data corresponding to a pixel address that is about to be drawn.
For -1, the pixel data is read from the corresponding address for modification writing, and after modification, writing back to the same address. When performing hidden surface processing, it is necessary to read the depth data from the corresponding address for modification writing to the memory block that also stores the depth data corresponding to the pixel address that is about to be drawn. If so, write back to the same address after modification. Further, the memory I / F circuit 145-1 is the texture engine circuit 14
Receiving the pixel-level processing result supplied by 4-1 the pixel data that has passed various tests in the pixel-level processing is drawn in the memory module 147-1.

The area determination circuit 142-2 of the processing module 140-2 receives the information regarding the triangle including the variation data by the DDA setup circuit 141 input via the broadcast bus 149, and the triangle is defined in advance. Area RG of own module
It is determined whether or not it is included in N2, and if it is included, the input information is output to the DDA circuit 143-2 at the next stage. On the other hand, when the triangle is not included in the assigned area RGN2 of the own module in which the triangle is defined in advance, the area determination circuit 142-2 outputs the input information to the DDA circuit 143 of the next stage.
Discard without outputting to -2. This area determination circuit 142-2
Determines whether the assigned area RGN2 includes a triangle by using the coordinates of the start point and the end point in the X direction and the Y direction included in the input information.

Area RG in charge of the processing module 140-2
N2 is a lower left region of 2 × 2 division, as shown in FIG. 9, when a generation unit of 4 × 4 pixels per one processing module is used, for example. Therefore, the area determination circuit 142-2 determines whether or not a part of the corresponding triangle is (is included) in this assigned area RGN2.

For example, in the example of FIG. 10, a triangle PM11
Is included in the assigned area RGN2 of the processing module 140-2, the area determination circuit 142-2
Assuming that the triangle PM11 is included in the assigned area RGN2 of the own module which is defined in advance, the input information is output to the DDA circuit 143-2 at the next stage. on the other hand,
Since the triangle PM12 in the example of FIG. 10 has no area included in the area RGN2 in charge of the processing module 140-2, the area determination circuit 142-2 determines that the triangle PM1.
2 is not included in the assigned area RGN2 of the own module defined in advance, the input information is discarded without being output to the DDA circuit 143-2 in the next stage.

DDA circuit 1 of processing module 140-2
43-2 linearly interpolates (z, R, G, B, s, t, at each pixel of the area in charge of the triangle using the variation data supplied from the area determination circuit 142-2.
q) Calculate the data. The DDA circuit 143-2 DD-converts the (x, y) data of each pixel and the (z, R, G, B, s, t, q) data at the (x, y) coordinates.
It is output to the texture engine circuit 144-2 as A data (interpolation data). That is, the DDA circuit 143-
2 performs rasterization based on the parameter data, for example, when the triangle is the area in which the triangle is in charge. Specifically, when the triangle is the area in charge of itself, various data (z, texture coordinates, color, etc.) is rasterized. In this case, the generation unit is 4 × 4 pixels in one cycle per local module.

The DDA circuit 143-2 uses the DDA setup circuit 141 in the preceding stage to set the first value at the drawing start point of the triangle, the horizontal direction (X direction) and the vertical direction (Y direction).
Inclination information of the various information described above in the direction) is prepared. The basic processing here is to obtain values on an integer grid included in a given triangle, and the substance of this processing is to multiply the integer distance from the drawing start point by the slope. Further, actually, rather than performing multiplication, a value of one pixel advanced in the horizontal direction (X direction) can be obtained by adding the amount of inclination in the horizontal direction. Therefore, the calculation content is a constant value addition process.

However, the DDA circuit according to this embodiment is different from the case of performing a series of pixel generation processing as shown in FIG. 1 in the way of scanning. For example, when drawing a triangle as shown in FIG. 13A, pixels are conventionally generated in units of rectangular areas. That is, in the figure, the scanning is started in the X direction from the processing start point indicated by the broken line, and when it goes out of the triangle, it moves in the Y direction and scans again. On the other hand, in the present embodiment, the processing start point is moved to the area in charge of the own module. Then, scanning is performed in the X direction. When it goes out of the triangle, it moves in the Y direction and scans in the X direction again. That is, in the present embodiment in which a region in charge is allocated and parallel processing is performed, the width of movement of the scan itself is
Different from conventional. As described above, the DDA circuit 143-2 of the processing module 140-2 is in charge of the lower left area of the 2 × 2 rectangular area. In this example, as shown in FIG. 13D, the area in charge of the own module RGN2 is scanned in the Y direction (upward in the drawing) from the processing start point indicated by the broken line.
Move to. Then, the DDA circuit 143-2 next
Scan in the X direction (right in the drawing).

The texture engine circuit 144-2 is
Calculation processing of “s / q” and “t / q”, calculation processing of texture coordinate data (u, v), (R, G, from the texture buffer included in the graphics memory 147).
B) The data read processing and the like are performed by a pipeline method. The texture engine circuit 144-2 is the texture engine circuit 144-0, 144-1, 14 of the other processing modules 140-0, 140-1, 140-3.
8 in cooperation with 4-3, for example located within a given rectangle
Pixels are processed simultaneously in parallel. The texture engine circuit 144-2 is the DDA of its own module.
The DDA data from the circuit 144-2 indicates (s, t,
For q) data, an operation of dividing s data by q data and an operation of dividing t data by q data are performed. Further, the texture engine circuit 144-2 multiplies the division results “s / q” and “t / q” by the texture sizes USIZE and VSIZE, respectively, to generate texture coordinate data (u, v).

Also, the texture engine circuit 144-2
Is the texture bus 150, the dedicated memory I / F circuit 14
6, a read request including the generated texture coordinate data (u, v) is output to the graphics memory 147, and the texture buffer included in the graphics memory 147 is output via the dedicated memory I / F circuit 146. By reading the stored texture data,
(R, G, B) data stored at the texture address corresponding to (s, t) data is obtained. The texture engine circuit 144-2 multiplies the read (R, G, B) data by the (R, G, B) data included in the DDA data from the DDA circuit 143-2 at the preceding stage. To generate pixel data. The texture engine circuit 144-2 finally uses the pixel data as the color value of the pixel and the memory I / F circuit 145.
Output to -2. In this case, the texture engine circuit 1
44-2 represents the read texture data and (u,
v) The address is subjected to filtering processing such as 4-neighbor interpolation using the decimal part obtained at the time of calculation.

The texture buffer contains MIPM.
Texture data corresponding to a plurality of reduction ratios such as AP (multi-resolution texture) is stored. Here, which reduction rate of texture data is used is determined for each triangle by using a predetermined algorithm.

In the case of the full color system, the texture engine circuit 144-2 directly uses the (R, G, B) data read from the texture buffer. On the other hand, in the case of the index color system, the texture engine circuit 144-2 is an SR that incorporates the data of the color index table created in advance from the texture color lookup table (CLUT) buffer.
Transfer to a temporary storage buffer composed of AM etc.,
Using this color lookup table, (R, G, B) data corresponding to the color index read from the texture buffer is obtained. For example, when the color look-up table is composed of SRAM, when the color index is input to the address of SRAM, the actual (R, G, B) data appears at the output.

The memory I / F circuit 145-2 stores the z data corresponding to the pixel data input from the texture engine circuit 144-2 and the z data stored in the z buffer included in the memory module 147-2. The image drawn by the comparison and input pixel data is in front (viewpoint side) from the image written in the memory module 147-2 (display buffer) last time.
If it is located in front,
The z data stored in the z buffer is updated with the z data corresponding to the image data. In addition, the memory I / F circuit 145
-2 stores (R, G, B) data in the memory module 14
Write in 7-1. The memory I / F circuit 145-2 is a memory module 147 that stores pixel data corresponding to a pixel address that is about to be drawn.
With respect to -2, the pixel data is read from the corresponding address for the modified writing, and after the modification, it is written back to the same address. When performing hidden surface processing, it is necessary to read the depth data from the corresponding address for modification writing to the memory block that also stores the depth data corresponding to the pixel address that is about to be drawn. If so, write back to the same address after modification. Further, the memory I / F circuit 145-2 is the texture engine circuit 14
Upon receiving the pixel-level processing result supplied by 4-2, pixel data that has passed various tests in the pixel-level processing is drawn in the memory module 147-2.

The area determination circuit 142-3 of the processing module 140-3 receives the information regarding the triangle including the variation data by the DDA setup circuit 141 input via the broadcast bus 149, and the triangle is defined in advance. Area RG of own module
It is determined whether or not it is included in N1, and if it is included, the input information is output to the DDA circuit 143-3 at the next stage. On the other hand, when the triangle is not included in the assigned area RGN3 of the own module in which the triangle is defined in advance, the area determination circuit 142-3 outputs the input information to the DDA circuit 143 of the next stage.
Discard without outputting to -3. This area determination circuit 142-3
Determines whether the assigned area RGN1 includes a triangle by using the coordinates of the start point and the end point in the X direction and the Y direction included in the input information.

Area RG in charge of the processing module 140-3
N3 is a lower right region of 2 × 2 division, as shown in FIG. 9, where a generation unit of 4 × 4 pixels per cycle for one processing module is used, for example. Therefore, the area determination circuit 142-3 determines whether or not a part of the corresponding triangle is (is included) in this assigned area RGN3.

For example, in the example of FIG. 10, a triangle PM11
And PM12 have a region included in the assigned region RGN3 of the processing module 140-3, the region determination circuit 142-3 determines that the triangular regions PM11 and PM12 are assigned to the assigned region RGN3 of its own module.
And outputs the input information to the DDA circuit 143-3 at the next stage.

DDA circuit 1 of processing module 140-3
43-3 linearly interpolates (z, R, G, B, s, t, at each pixel in the area in charge of the triangle using the variation data supplied from the area determination circuit 142-3.
q) Calculate the data. The DDA circuit 143-3 sets the (x, y) data of each pixel and the (z, R, G, B, s, t, q) data at the (x, y) coordinates to DD.
It is output to the texture engine circuit 144-3 as A data (interpolation data). That is, the DDA circuit 143-
3 performs rasterization based on the parameter data when, for example, the triangle is the area in which the triangle is in charge. Specifically, when the triangle is the area in charge of itself, various data (z, texture coordinates, color, etc.) is rasterized. In this case, the generation unit is 4 × 4 pixels in one cycle per local module.

The DDA circuit 143-3 uses the DDA setup circuit 141 in the preceding stage to set the first value at the drawing start point of the triangle, the horizontal direction (X direction) and the vertical direction (Y direction).
Inclination information of the various information described above in the direction) is prepared. The basic processing here is to obtain values on an integer grid included in a given triangle, and the substance of this processing is to multiply the integer distance from the drawing start point by the slope. Further, actually, rather than performing multiplication, a value of one pixel advanced in the horizontal direction (X direction) can be obtained by adding the amount of inclination in the horizontal direction. Therefore, the calculation content is a constant value addition process.

However, the DDA circuit according to this embodiment is different from the case of performing a series of pixel generation processing as shown in FIG. 1 in the way of scanning. For example, when drawing a triangle as shown in FIG. 13A, pixels are conventionally generated in units of rectangular areas. That is, in the figure, the scanning is started in the X direction from the processing start point indicated by the broken line, and when it goes out of the triangle, it moves in the Y direction and scans again. On the other hand, in the present embodiment, the processing start point is moved to the area in charge of the own module. Then, scanning is performed in the X direction. When it goes out of the triangle, it moves in the Y direction and scans in the X direction again. That is, in the present embodiment in which a region in charge is allocated and parallel processing is performed, the width of movement of the scan itself is
Different from conventional. As described above, the DDA circuit 143-3 of the processing module 140-3 is in charge of the lower right area of the 2 × 2 divided rectangular area. In this example, FIG.
As shown in, the scan starts from the processing start point indicated by the broken line in the X direction, and further in the Y direction to move to the assigned area RGN3 of the own module. Then, the DDA circuit 143
-3 is then scanned in the X direction (to the right in the drawing).

The texture engine circuit 144-3 is
Calculation processing of “s / q” and “t / q”, calculation processing of texture coordinate data (u, v), (R, G, from the texture buffer included in the graphics memory 147).
B) The data read processing and the like are performed by a pipeline method. Note that the texture engine circuit 144-3 cooperates with the texture engine circuits 144-0 to 144-2 of the other processing modules 140-0 to 140-2 to, for example, for 8 pixels located in a predetermined rectangle. Perform processing concurrently in parallel. Texture engine circuit 144-
3 is a DD by the DDA circuit 144-3 of its own module
For the (s, t, q) data indicated by the A data, an operation of dividing s data by q data and an operation of dividing t data by q data are performed. Further, the texture engine circuit 144-3 uses the division results “s / q” and “t /”.
q ”to the texture sizes USIZE and V, respectively.
SIZE is multiplied to generate texture coordinate data (u, v).

Further, the texture engine circuit 144-3
Is the texture bus 150, the dedicated memory I / F circuit 14
6, a read request including the generated texture coordinate data (u, v) is output to the graphics memory 147, and the texture buffer included in the graphics memory 147 is output via the dedicated memory I / F circuit 146. By reading the stored texture data,
(R, G, B) data stored at the texture address corresponding to (s, t) data is obtained. The texture engine circuit 144-3 multiplies the read (R, G, B) data by the (R, G, B) data included in the DDA data from the DDA circuit 143-3 at the preceding stage. To generate pixel data. The texture engine circuit 144-3 finally uses the pixel data as the color value of the pixel, and the memory I / F circuit 145.
Output to -3. In this case, the texture engine circuit 1
44-3 is the read texture data and (u,
v) The address is subjected to filtering processing such as 4-neighbor interpolation using the decimal part obtained at the time of calculation.

The texture buffer contains MIPM.
Texture data corresponding to a plurality of reduction ratios such as AP (multi-resolution texture) is stored. Here, which reduction rate of texture data is used is determined for each triangle by using a predetermined algorithm.

In the case of the full color system, the texture engine circuit 144-3 directly uses the (R, G, B) data read from the texture buffer. On the other hand, in the case of the index color system, the texture engine circuit 144-3 is an SR that incorporates the data of the color index table created in advance from the texture color lookup table (CLUT) buffer.
Transfer to a temporary storage buffer composed of AM etc.,
Using this color lookup table, (R, G, B) data corresponding to the color index read from the texture buffer is obtained. For example, when the color look-up table is composed of SRAM, when the color index is input to the address of SRAM, the actual (R, G, B) data appears at the output.

The memory I / F circuit 145-3 stores the z data corresponding to the pixel data input from the texture engine circuit 144-3 and the z data stored in the z buffer included in the memory module 147-3. The image drawn by the comparison and input pixel data is in front (viewpoint side) from the image written in the memory module 147-3 (display buffer) last time.
If it is located in front,
The z data stored in the z buffer is updated with the z data corresponding to the image data. In addition, the memory I / F circuit 145
-3 is (R, G, B) data for the memory module 14
Write in 7-3. The memory I / F circuit 145-3 is a memory module 147 that stores pixel data corresponding to a pixel address that is about to be drawn.
For -3, the pixel data is read from the corresponding address for modification writing, and after modification, writing back to the same address. When performing hidden surface processing, it is necessary to read the depth data from the corresponding address for modification writing to the memory block that also stores the depth data corresponding to the pixel address that is about to be drawn. If so, write back to the same address after modification. Further, the memory I / F circuit 145-3 is connected to the texture engine circuit 14
Upon receipt of the pixel-level processing result supplied by 4-3, pixel data that has passed various tests in the pixel-level processing is drawn in the memory module 147-3.

The dedicated memory I / F circuit 146 calculates the memory block storing the texture data corresponding to the texture address of the pixel which is about to be drawn from the texture address, and stores it in the predetermined memory of the graphics memory 147. Texture data is read by issuing a read request only to the module. Further, when the dedicated memory I / F circuit 146 receives a read request including the texture coordinate data (u, v) generated from the texture engine circuits 144-0 to 144-3, it is stored in a buffer such as SRAM. The read (R, G, B) data is read. In addition, the dedicated memory I
When the / F circuit 146 receives a request to read the display data from the CRT control circuit 148, the / F circuit 146 responds to the request from the graphics memory 147 (specifically, the display buffer) in a fixed block, for example, 8 pixels or Display data is read in units of 16 pixels.

The graphics memory 147 functions as, for example, a texture buffer, a display buffer, az buffer and a texture CLUT (Color Look Up Table) buffer. Also, graphics memory 1
As described above, reference numeral 47 denotes a plurality (four in this embodiment) of memory modules 147-0 to 14-14 having the same function.
It is divided into 7-3. Further, in the graphics memory 147, in order to store more texture data, the index in the index color and the color lookup table value for that are stored in the texture CLUT buffer. The index and color lookup table values are as described above.
Used for texture processing. That is, normally R, G,
A texture element is represented by a total of 24 bits of 8 bits for each B. However, since the amount of data expands, one color is selected from 256 colors selected in advance, and the data is textured. Used for processing. As a result, if there are 256 colors, each texture element can be represented by 8 bits. The conversion table from the index to the actual color is required, but the higher the resolution of the texture, the more compact the texture data can be. As a result, the texture data can be compressed and the internal memory can be used efficiently.

As described above, the DDA setup circuit 1
41, the DDA circuit 143-0 to 143-3, the texture engine circuit 144-0 to 144-3, the memory I / F circuit 145-0 to 145-3, and the like. ; Picture Cell E
lement) is the drawing pixel unit.

The CRT control circuit 148 synchronizes with the supplied horizontal and vertical synchronizing signals, and outputs a C signal (not shown).
A display address to be displayed on the RT is generated, and a request to read the display data from the display buffer included in the graphics memory 147 is output to the dedicated memory I / F circuit 146. In response to this request, the dedicated memory I / F circuit 1
46 reads display data from the graphics memory 147 (display buffer) in a fixed block. C
The RT control circuit 148 stores the display data read from the graphics memory 147, for example, F
It incorporates an IFO circuit and generates RGB index values at regular time intervals. CRT control circuit 148
Stores the R, G, B data corresponding to each index value, and stores the digital format R, G, B data corresponding to the generated RGB index values in D /
The data is transferred to an A converter (Digital / Analog Converter) to generate R, G, B data in analog format. The CRT control circuit 148 outputs the generated R, G, B data to a CRT (not shown).

Next, the operation of the above configuration will be described with reference to FIGS. Note that, here, as shown in FIG. 15, three triangular primitives PM101, PM
A case will be described in which 102 and PM 103 are sequentially input to perform drawing processing. In this example, the primitive PM 101 is the responsible area RG of all the processing modules 140-0 to 140-3.
Hanging (included) on N0-RGN3. The primitive PM 102 is a processing module 140-0 to -1.
The processing modules 140-2 and 14 are included in the areas RGN0 and RGN1 in charge of 40-1.
The areas 0 to 3 in charge are not covered (not included) in the areas RGN2 and RGN3. The primitive PM 103 is a responsible area RG of all the processing modules 140-0 to 140-3.
Hanging (included) on N0-RGN3.

In the three-dimensional computer graphics system 10, data such as graphics drawing is
It is supplied to the rendering circuit 14 from the main memory 12 of the main processor 11 or the I / O interface circuit 13 that receives graphics data from the outside via the main bus 15. Note that data such as graphics drawing is subjected to geometry processing such as coordinate conversion, clipping processing, and lighting processing in the main processor 11 or the like, if necessary. The graphics data after the geometry processing is composed of the vertex coordinates x, y, z of the three vertices of the triangle, the brightness values R, G, B, and the texture coordinates s, t, q corresponding to the pixel to be drawn. It becomes the polygon rendering data S11.

In this example, as shown in FIG. 16, three triangular primitives PM101, PM102, PM103 are provided.
The polygon rendering data S11 according to the above is sequentially transferred to the DDA setup circuit 141 of the rendering circuit 14.

In the DDA setup circuit 141, first, based on the polygon rendering data S11 related to the triangle primitive PM101, variation data indicating the difference between the sides of the triangle and the horizontal direction is generated. Specifically, using the values of the starting point and the ending point, and the distance between them, the variation that is the variation of the value to be obtained when the unit length is moved is calculated, and the variation data Information about the triangle primitive PM101 including
As shown in FIG. 17, the signals are supplied in parallel to the area determination circuits 142-0 to 142-3 of the processing modules 140-0 to 140-3 through the broadcast bus 149.

Each processing module 140-0 to 140-3
In the area determination circuits 142-0 to 142-3, the information about the triangle primitive PM101 including the variation data by the DDA setup circuit 141 input via the broadcast bus 149 is received, and the own module in which the triangle is defined in advance is received. Area in charge of RGN
~ It is determined whether or not it is included in RGN3. in this case,
As described above, the triangle primitive PM101 is assigned to the area RG in charge of all the processing modules 140-0 to 140-3.
Since it is included in N0 to RGN3, as shown in FIG. 18, the input information from each area determination circuit 142-0 to 142-3 is the DDA circuit 143-0 to 143-3 of its own module.
Is output to.

In parallel with this, the polygon rendering data S11 relating to the next triangle primitive PM102.
Is input to the DDA setup circuit 141. DDA
In the setup circuit 141, the polygon rendering data S11 relating to the triangle primitive PM102.
Based on, the variation data indicating the difference between the sides of the triangle and the horizontal direction is generated. Specifically, using the value of the start point and the value of the end point, and the distance between them, the variation that is the variation of the value to be obtained when the unit length is moved is calculated, and the variation data Information about the triangle primitive PM102 including the information is transmitted via the broadcast bus 149 as shown in FIG.
40-0 to 140-3 area determination circuits 142-0 to 142
2-3 are supplied in parallel.

Each processing module 140-0 to 140-3
In the area determination circuits 142-0 to 142-3, the information about the triangle primitive PM102 including the variation data by the DDA setup circuit 141 input via the broadcast bus 149 is received, and its own module in which the triangle is defined in advance is received. Area in charge of RGN
~ It is determined whether or not it is included in RGN3. in this case,
As described above, the triangle primitive PM102 is assigned to the area RGN in charge of the processing modules 140-0 and 140-1.
0, included in RGN1, processing modules 140-2, 1
40-3 is not included in the responsible area RGN2, RGN3.
Therefore, as shown in FIG. 19, the assigned area RGN0,
Each area determination circuit 142-which is determined to be included in RGN1
The input information from 0, 142-1 is output to the DDA circuits 143-0, 143-1 of its own module. On the other hand, the area determination circuit 142- of the processing modules 140-2 and 140-3 determined to be not included in the assigned areas RGN2 and RGN3
2, 142-3, the input information is the DDA circuit 14 of the next stage.
It is discarded without being output to 3-2 and 143-3.

In parallel with this, the polygon rendering data S11 relating to the next triangle primitive PM103.
Is input to the DDA setup circuit 141. DDA
In the setup circuit 141, the polygon rendering data S11 relating to the triangle primitive PM103
Based on, the variation data indicating the difference between the sides of the triangle and the horizontal direction is generated. Specifically, using the values of the starting point and the ending point, and the distance between them, the variation that is the variation of the value to be obtained when the unit length is moved is calculated, and the variation data Information regarding the triangle primitive PM103 including the information is transmitted via the broadcast bus 149 to each processing module 1 as shown in FIG.
40-0 to 140-3 area determination circuits 142-0 to 142
2-3 are supplied in parallel.

Each processing module 140-0 to 140-3
In the area determination circuits 142-0 to 142-3, the information regarding the triangle primitive PM103 including the variation data by the DDA setup circuit 141 input via the broadcast bus 149 is received, and its own module in which the triangle is defined in advance is received. Area in charge of RGN
~ It is determined whether or not it is included in RGN3. in this case,
As described above, the triangle primitive PM103 is assigned to the processing area RG of all the processing modules 140-0 to 140-3.
Since it is included in N0 to RGN3, as shown in FIG. 20, the input information from each area determination circuit 142-0 to 142-3 is the DDA circuit 143-0 to 143-3 of its own module.
Is output to.

Each processing module 140-0 to 140-3
In the DDA circuits 143-0 to 143-3, the following processing is performed in the input order of the triangle primitives PM101 to PM103. That is, first, all DDA circuits 143-0
~ 143-3, the triangle primitive PM101
Is performed, and then the processing module 140-
The DDA circuits 143-0 and 143-1 of 0 and 140-1 perform processing on the triangle primitive PM102, and finally, all the DDA circuits 143-0 to 143-3.
In, the process for the triangle primitive PM103 is performed. Similarly, the DDA circuits 143-0 to 143-
3 following texture engine circuits 144-0-14
4-3, and memory I / F circuits 145-0 to 145-
3, the following processing is performed in the input order of the triangle primitives PM101 to PM103.

Specifically, all DDA circuits 143-0 to 143-1.
43-3 or DDA circuits 143-0 and 143-1
, The area determination circuits 142-0 to 142, respectively.
-3 was used to linearly interpolate (z, R, G, B, at each pixel inside the triangle).
s, t, q) data is calculated. Then, the calculated (z, R, G, B, s, t, q) data and the (x, y) data of each vertex of the triangle are texture engine circuits 144-0 to 144- as DDA data. 3 is output.

Texture engine circuits 144-0-14
4-3 or the texture engine circuits 144-0 and 144-1, the DDA circuits 143-0 to 143.
For the (s, t, q) data indicated by the DDA data of -3, an operation of dividing s data by q data and an operation of dividing t data by q data are performed. Then, the division results “s / q” and “t / q” are multiplied by the texture sizes USIZE and VSIZE, respectively, to generate texture coordinate data (u, v).

Next, the texture engine circuit 144-0
~ 144-3 or texture engine circuit 144-0
And 144-1 output a read request including the generated texture coordinate data (u, v) to the dedicated memory I / F circuit 146, and the dedicated memory I / F circuit 146 is output.
The (R, G, B) data stored in the graphics memory 147 is read via. Next, in the texture engine circuits 144-0 to 144-3 or the texture engine circuits 144-0 and 144-1,
It is included in the read (R, G, B) data and the DDA data from the DDA circuits 143-0 to 143-3 or DDA circuits 143-0 and 143-1 at the preceding stage (R, G, B).
G, B) data is multiplied to generate pixel data. This pixel data is stored in the memory I / F from the texture engine circuits 144-0 to 144-3 or the texture engine circuits 144-0 and 144-1.
Circuits 145-0 to 145-3 or memory I / F circuit 1
It is output to 45-0 and 145-1.

Then, the memory I / F circuits 145-0 to 1
45-3 or memory I / F circuits 145-0 and 14
In 5-1 the texture engine circuit 144-0.
144-3 or z data corresponding to the pixel data input from the texture engine circuits 144-0 and 144-1 and corresponding memory modules 147-0 to -1
47-3 or memory modules 147-0 and 14
The image drawn by the input pixel data is compared with the z data stored in 7-1 (z buffer), and the image drawn by the input pixel data is in front of the image written in the display buffer of the memory module (on the viewpoint side). ) Is determined. If the result of determination is that it is located in the front, the memory module 147-0 to 147-3 or the memory module 1 is determined by z data corresponding to image data.
The z data stored in 47-0 and 147-1 are updated.

Next, the memory I / F circuits 145-0 to 145-14
5-3 or memory I / F circuits 145-0 and 145
At -1, (R, G, B) data is written in the corresponding memory module 147-0 to 147-3 or memory modules 147-0 and 1471.

In the dedicated memory I / F circuit 146, the memory block storing the texture corresponding to the texture address of the pixel to be drawn is calculated by the texture address, and the predetermined value of the graphics memory 147 is calculated. A read request is issued only to the memory module of, and the texture data is read.

Further, the memory I / F circuits 145-0 to 145-14
5-3 or memory I / F circuits 145-0 and 145
-1, the memory module 147-0 to 147-3 or the memory modules 147-0 and 147-1 storing the pixel data corresponding to the pixel address to be drawn from the pixel address from the corresponding address. Modify write (Modify
It is read for writing, and after modification, it is written back to the same address.

Memory I / F circuits 145-0 to 145-3
Alternatively, when the hidden surface processing is performed in the memory I / F circuits 145-0 and 145-1, the memory module 147 that similarly stores the depth data corresponding to the pixel address to be drawn from now on.
-0 to 147-3 or the memory modules 147-0 and 147-1, the depth data is read from the corresponding address to perform the modify write (Modify Write), and if necessary, after the modify, write to the same address. Will be returned.

When displaying an image on a CRT (not shown), the CRT control circuit 148
A display address is generated in synchronization with the applied horizontal and vertical synchronization frequencies, and a request for display data transfer is issued to the dedicated memory I / F circuit 146. Dedicated memory I / F circuit 146
Then, according to the request, the display data is transferred to the CRT control circuit 148 in a fixed block. The CRT control circuit 148 stores the display data in a display FIFO (not shown),
RGB index values are generated at regular intervals. C
In the RT control circuit 148, the RGB values for the RGB indexes are stored in the RAM, and the RGB values for the index values are not shown in D /
Transferred to the A converter. Then, the RGB signal converted into the analog signal by the D / A converter is transferred to the CRT.

As described above, according to this embodiment, the same triangular data by the DDA setup circuit 141 is sent in parallel to each processing module 140-0 to 140-3, and each processing module 140-0 to 140-3 is sent. Is
Each processing module 140-0 to 140-3 is associated with each memory module 147-0 to 147-3.
Receives the information about the triangle including the variation data by the DDA setup circuit 141, and takes charge of the areas RGN0 to RG of its own module in which the triangle is defined in advance.
It is determined whether or not the input information is included in N3. If it is included, the input information is output to the DDA circuits 143-0 to 143-3 in the next stage. If it is not included, the input information is output in the next stage. DD
A circuit 143-0 to 143-3, which has area determination circuits 142-0 to 142-3 to discard without outputting to the circuit, draws only pixels included in the areas RGN0 to RGN3 handled by its own module and corresponds to the corresponding memory Module 147-0
Since the data is sent to 147-3, parallel processing can be performed regardless of the operation mode when a plurality of processing modules share processing data and perform parallel processing. Then, there is an advantage that parallel processing with high execution efficiency can be realized without being restricted by the number of pixels that can be processed in parallel, and that the performance can be improved. Further, in the present embodiment, the processing distribution can be directly connected to the processing modules 140-0 to 140-3 and the memory modules 147-0 to 147-3, and the number of wirings can be reduced and the size can be reduced. As a result, the design becomes easy, and the wiring cost and the wiring delay can be reduced.

It should be noted that in the embodiment described above, FIG.
As shown in 3 (A) to 3 (E), the case where the size of the area in charge of each processing module and the size of the rectangular area in which the DDA circuit generates pixels have been described as an example.
The present invention is not limited to this.

That is, the size of the area in charge and the size of the rectangular area do not have to match. For example, in FIG.
As shown in (A) to (E), the respective responsible areas RGN0 to RGN
It is also possible to hierarchically form a rectangular area in which pixels are generated in GN3 by 2 × 2. In this case, the movement is hierarchical. That is, the movement between the assigned areas and the movement within the assigned area in units of rectangular areas are performed. Then, in each processing module, areas in charge in a plurality of unit areas are scanned, and pixels are simultaneously generated hierarchically in units of divided areas. Also in this case, the same effect as that of the above-described embodiment can be obtained.

In addition, in the above-described embodiment, FIG.
3 (A) to (E), each processing module 14
The allocation of the assigned areas RGN0 to RGN3 of 0-0 to 140-3 is fixed. Specifically, the upper left of the 2 × 2 rectangular area is set as the assigned area of the processing module 140-0, and the upper right is set to the processing module 140-1. As an example, the case has been described where the lower left area is the area in charge of the processing module 140-2 and the lower right area is the area in charge of the processing module 140-3.
The present invention is not limited to this.

That is, the assigned area can be arbitrarily assigned. For example, as shown in FIG. 22B, in the upper left and lower left 2 × 2 rectangular areas,
As described above, the upper left is the area in charge of the processing module 140-0, the upper right is the area in charge of the processing module 140-1, the lower left is the area in charge of the processing module 140-2, and the lower right is the area of the processing module 140-3. To be in charge
In the upper right and lower right 2 × 2 rectangular areas, the lower left is the area in charge of the processing module 140-0, the lower right is the area in charge of the processing module 140-1, and the upper right is the area in charge of the processing module 140-2. , The upper right is the area in charge of the processing module 140-3, and various other modes are possible.

Movement between assigned areas is as shown in FIG.
This is performed as shown in (F). Processing module 140-
The DDA circuit 143-0 of 0 is 2 × 2 as described above.
The upper left area and the lower left area of the rectangular area are the areas in charge. In this example, as shown in FIG. 22C, since the processing start point indicated by the broken line is the area RGN0 in charge of the own module, the DDA circuit 143-0 next moves diagonally upward to the right and then Then, move diagonally upward to the left.

DDA circuit 1 of processing module 140-1
As described above, in 43-1, the upper right area and the lower right area of the 2 × 2 rectangular area are responsible areas. In this example, FIG.
As shown in FIG. 2 (D), scanning is performed in the X direction from the processing start point indicated by the broken line, and the area is moved to the assigned area RGN1 of the own module. Then, the DDA circuit 143-1 moves diagonally upward to the right and then diagonally upward to the left.

DDA circuit 1 of processing module 140-2
As for 43-2, as described above, the lower left area and the upper left area of the 2 × 2 rectangular area are the areas in charge. In this example, FIG.
As shown in 2 (E), scanning is performed in the Y direction (upward in the drawing) from the processing start point indicated by the broken line, and the area is moved to the assigned area RGN2 of the own module. Then, the DDA circuit 143-
2 then moves diagonally upward to the right.

DDA circuit 1 of processing module 140-3
In 43-3, as described above, the lower right area and the upper right area of the 2 × 2 rectangular area are the areas in charge. In this example, FIG.
As shown in FIG. 2 (F), from the processing start point indicated by the broken line, scanning is performed in the X direction and further in the Y direction to move to the assigned area RGN3 of the own module. Then, the DDA circuit 143-3 next moves diagonally upward to the right.

Also in this case, the same effect as that of the above-described embodiment can be obtained.

Further, in the above-described embodiment, the areas assigned to the same primitive are assigned to the plurality of processing modules 140-0 to 140-3 and processed in parallel. It can also be configured to process at the same time. Specifically, it is also possible to give different primitives (for example, triangles) to a plurality of processing modules to operate them in parallel.

FIG. 23 is a diagram for explaining another embodiment of the image processing apparatus according to the present invention, and is a diagram conceptually showing the parallel processing at the primitive level. FIG. 23
Image processing apparatus (rendering circuit in the correspondence of FIGS. 3 and 4) 14A includes processing modules 1 arranged in parallel.
Unit graphics (primitives) are provided in front of the 40A-0 to 140A-3 processing modules 140A-0 to 140A-3.
A unit figure distribution circuit 151 for distributing to each other is provided.

In this embodiment, each processing module 14
When primitives of relatively uniform size are given to 0A-0 to 140A-3, each processing module 1
The load on 40A-0 to 140A-3 is balanced, and efficient parallel processing can be performed. Further, in this embodiment, in the hardware that performs graphics processing, memory interleaving is performed using a plurality of memory modules in order to increase the memory bandwidth, so that each processing module 140A-0 to 140A-3 It is necessary to connect all the memory modules 147-0 to 147-3. Therefore, the crossbar circuit 152 is provided.

According to the circuit of FIG. 23, the number of wires and the wiring cost increase, but when a plurality of processing modules share processing data and perform parallel processing, parallel processing is performed regardless of the operation mode. You can Then, there is an advantage that parallel processing with high execution efficiency can be realized without being restricted by the number of pixels that can be processed in parallel, and that the performance can be improved.

In the three-dimensional computer graphics system 10 shown in FIG. 3, the main processor 1 performs the geometry processing for generating polygon rendering data.
Although the case where the process is performed by the example 1 is illustrated, the configuration may be performed by the rendering circuit 14.

[0141]

As described above, according to the present invention,
When a plurality of processing devices share processing data and perform parallel processing, parallel processing can be performed regardless of the operation mode. Further, according to the present invention, there is an advantage that parallel processing with high execution efficiency can be realized without being restricted by the number of pixels that can be processed in parallel, and the performance can be improved.

[Brief description of drawings]

FIG. 1 is a diagram conceptually illustrating a general image processing apparatus that performs graphics drawing.

FIG. 2 is a diagram conceptually showing primitive level parallelization processing based on a pixel level parallel processing method.

FIG. 3 is a system configuration diagram of a three-dimensional computer graphics system as an image processing apparatus according to the present invention.

FIG. 4 is a block diagram showing an embodiment of a rendering circuit according to the present embodiment.

FIG. 5 is a diagram for explaining the basic concept of parallelization processing according to the present embodiment.

FIG. 6 is a diagram for explaining the basic concept of parallelization processing according to the present embodiment.

FIG. 7 is a diagram for explaining the function of the DDA setup circuit according to the present embodiment.

FIG. 8 is a diagram showing a configuration example of a DDA setup circuit according to the present embodiment.

FIG. 9 is a diagram for explaining an area in charge of a processing module according to the present embodiment.

FIG. 10 is a diagram for conceptually explaining the determination process of the area determination circuit according to the present embodiment, and is a diagram showing an example in the case of four parallels.

FIG. 11 is a diagram for conceptually explaining the determination process of the area determination circuit according to the present embodiment, and is a diagram showing an example in the case of eight parallel circuits.

FIG. 12 is a flowchart for explaining a determination processing operation of the area determination circuit according to the present embodiment.

FIG. 13 is a diagram for explaining pixel generation processing of the DDA circuit according to this embodiment.

FIG. 14 is a flowchart for explaining a pixel generation processing operation of the DDA circuit according to this embodiment.

FIG. 15 is a diagram for explaining the operation of the circuit of FIG. 4 and is a diagram showing an example of a triangle primitive which is continuously processed.

16 is a diagram for explaining the operation of the circuit of FIG.

FIG. 17 is a diagram for explaining the operation of the circuit of FIG.

FIG. 18 is a diagram for explaining the operation of the circuit of FIG.

FIG. 19 is a diagram for explaining the operation of the circuit of FIG.

20 is a diagram for explaining the operation of the circuit in FIG.

FIG. 21: Size and DD of area in charge of each processing module
It is a figure for explaining an example in case the size of the rectangular field which A circuit generates a pixel does not correspond.

FIG. 22 is a diagram for explaining another example of allocation of areas in charge of each processing module.

FIG. 23 is a diagram for explaining another embodiment of the image processing apparatus according to the present invention.

[Explanation of symbols]

10 ... Image processing device, 11 ... Main processor, 12 ...
Main memory, 13 ... I / O interface circuit, 1
4, 14A ... Rendering circuit, 140-0 to 140-
3,140A-0 to 140A-3 ... Processing module, 1
42-0 to 142-3 ... Area determination circuit, 143-0 to 1
43-3 ... Triangle DDA circuit, 144-0 to 1
44-3 ... Texture engine circuit, 145-0-14
5-3 ... Memory interface (I / F) circuit, 146
... Dedicated memory I / F circuit, 147 ... Graphics memory, 147-0 to 147-3 ... Memory module, 14
8 ... CRT control circuit, 149 ... Setup data broadcast bus, 150 ... Texture bus, 151 ... Unit figure distribution circuit, 152 ... Crossbar circuit, RGN0 to RGN3 ... Area in charge.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yuji Yamaguchi             1-14-10 Higashi Gotanda, Shinagawa-ku, Tokyo Stock             Ceremony company Sony Kihara Laboratory F-term (reference) 5B045 DD03 GG11                 5B057 AA20 CA01 CA08 CA12 CA13                       CA17 CB01 CB08 CB12 CB16                       CC04 CH04 CH11                 5B080 AA14 CA03 CA09 FA02 GA22

Claims (31)

[Claims] 1. An image processing apparatus in which a plurality of processing modules share processing data, perform parallel processing, and draw in a memory, wherein each of the plurality of processing modules receives information regarding a primitive to be drawn, Area determination circuit that determines whether or not is included in the area in charge of its own module that is divided into interleaves in advance, and if it is determined by the area determination circuit that the area is included in the area in charge of the own module, based on the input information And a processing circuit that performs drawing processing on the area in charge. 2. The image processing apparatus according to claim 1, wherein the same information regarding the primitive to be drawn is broadcast to the area determination circuits of the plurality of processing modules. 3. The image processing apparatus according to claim 1, wherein the area determination circuits of the plurality of processing modules are respectively supplied with information regarding different primitives to be drawn. 4. The image processing apparatus according to claim 1, wherein the processing circuits of the plurality of processing modules draw only pixels included in an area in which the module is in charge. 5. The image processing apparatus according to claim 2, wherein the processing circuits of the plurality of processing modules draw only pixels included in the area in which the module is in charge. 6. An area in which a predetermined unit area is divided by the number of the processing modules is allocated to each processing module, and the processing circuits of the plurality of processing modules are in charge of the plurality of unit areas. The image processing apparatus according to claim 4, wherein pixels are generated while scanning the image. 7. An area in which a predetermined unit area is divided by the number of the processing modules is allocated to the area in charge of each processing module, and the processing circuits of the plurality of processing modules are in charge of the plurality of unit areas. The image processing apparatus according to claim 5, wherein the pixels are generated while scanning the image. 8. An area in which a predetermined unit area is divided by the number of the processing modules is allocated to the area in charge of each processing module, and the processing circuits of the plurality of processing modules are in charge of the area in the plurality of unit areas. 5. The image processing apparatus according to claim 4, wherein the pixels are scanned to simultaneously generate pixels in units of divided areas. 9. An area in which a predetermined unit area is divided by the number of the processing modules is allocated to the area in charge of each processing module, and the processing circuits of the plurality of processing modules are in charge of the area in the plurality of unit areas. 6. The image processing apparatus according to claim 5, wherein the pixels are scanned and pixels are simultaneously generated in a hierarchically divided area unit. 10. The memory includes a plurality of memory interleaved memory modules, the plurality of processing modules correspond to the plurality of memory modules in a one-to-one correspondence, and the processing circuits of the plurality of processing modules include: 2. The image processing apparatus according to claim 1, wherein only the processing result for the area in charge of its own module is drawn and output to the corresponding memory module. 11. The memory includes a plurality of memory interleaved memory modules, wherein the plurality of processing modules and the plurality of memory modules have a one-to-one correspondence, and the processing circuits of the plurality of processing modules include: 3. The image processing apparatus according to claim 2, wherein only the pixels included in the area in which the module is in charge are drawn and output to the corresponding memory module. 12. An area obtained by dividing a predetermined unit area by the number of the processing modules is allocated to each processing module, and the processing circuits of the plurality of processing modules are in charge of the plurality of unit areas. The image processing apparatus according to claim 10, wherein the pixels are generated while scanning the image. 13. An area in which a predetermined unit area is divided by the number of the processing modules is allocated to the area in charge of each processing module, and processing circuits of the plurality of processing modules are in charge of the plurality of unit areas. The image processing apparatus according to claim 11, wherein the pixels are generated while scanning the. 14. A region to which each processing module is assigned is assigned a region obtained by dividing a predetermined unit region by the number of the processing modules, and the processing circuits of the plurality of processing modules are assigned to the regions to be handled in the plurality of unit regions. 11. The image processing apparatus according to claim 10, wherein the pixels are scanned and pixels are simultaneously generated in a hierarchically divided area unit. 15. An area obtained by dividing a predetermined unit area by the number of the processing modules is assigned to the area in charge of each processing module, and the processing circuits of the plurality of processing modules are in charge of the area in the plurality of unit areas. 12. The image processing apparatus according to claim 11, wherein the pixels are scanned and pixels are simultaneously generated hierarchically in units of divided areas. 16. The area determination circuit outputs the input information to the processing circuit when it is determined that the primitive is included in the area of its own module, and the input information when it is determined that the primitive is not included. The image processing apparatus according to claim 1, wherein the image processing apparatus discards the image without outputting it to the processing circuit. 17. An image processing method in which a plurality of processing modules share processing data, perform parallel processing, and draw in a memory, wherein the plurality of processing modules are interleaved and processed by their own modules. Allocating an area in charge, supplying information on the primitives to be drawn to the above processing modules, and in each processing module, whether or not the primitives are included in the area in charge of its own module which is divided into interleaves in advance. When it is determined that the module is included in the area in charge of the own module,
An image processing method for performing drawing processing on a responsible area based on the supplied information. 18. The image processing method according to claim 17, wherein the same information about the primitive to be drawn is broadcast to the plurality of processing modules. 19. The image processing method according to claim 17, wherein information regarding different primitives to be drawn is supplied to each of the plurality of processing modules. 20. The image processing method according to claim 17, wherein each of the plurality of processing modules draws only a pixel included in an area in which the module is in charge. 21. The image processing method according to claim 18, wherein each of the plurality of processing modules draws only a pixel included in an area in which the module is in charge. 22. As the area in charge of each processing module,
21. The image processing method according to claim 20, wherein a predetermined unit area is divided by the number of the processing modules, each area is allocated, and the plurality of processing modules generate pixels while scanning areas in charge of the plurality of unit areas. . 23. As the area in charge of each processing module,
22. The image processing method according to claim 21, wherein each of predetermined areas is divided into a plurality of processing modules, and each of the areas is allocated, and the plurality of processing modules generate pixels while scanning areas in charge of the plurality of unit areas. . 24. As the area in charge of each processing module,
A predetermined unit area is divided by the number of the processing modules, and each area is allocated. In the plurality of processing modules, the areas in charge of the plurality of unit areas are scanned, and pixels are generated simultaneously in a hierarchically divided area unit. The image processing method according to claim 20. 25. As the area in charge of each processing module,
A predetermined unit area is divided by the number of the processing modules, and each area is allocated. In the plurality of processing modules, the areas in charge of the plurality of unit areas are scanned, and pixels are generated simultaneously in a hierarchically divided area unit. The image processing method according to claim 21. 26. The memory is interleaved with a plurality of memory modules so that the plurality of processing modules correspond to the plurality of memory modules in a one-to-one correspondence, and the plurality of processing modules are in charge of their own modules. 18. The image processing method according to claim 17, wherein only the processing result for the area is drawn and output to the corresponding memory module. 27. The memory is interleaved with a plurality of memory modules so that the plurality of processing modules correspond to the plurality of memory modules in a one-to-one correspondence, and the plurality of processing modules are in charge of their own modules. 19. The image processing method according to claim 18, wherein only the processing result for the area is drawn and output to the corresponding memory module. 28. As the area in charge of each processing module,
27. The image processing method according to claim 26, wherein predetermined areas are divided by the number of the processing modules, and respective areas are allocated, and the plurality of processing modules generate pixels while scanning areas in charge of the plurality of unit areas. . 29. As the area in charge of each processing module,
28. The image processing according to claim 27, wherein predetermined areas are divided by the number of the processing modules, and respective areas are allocated, and pixels are generated while scanning areas in charge of the plurality of processing areas in the plurality of processing modules. Method. 30. As the area in charge of each processing module,
Each of the areas obtained by dividing the predetermined unit area by the number of the processing modules is allocated, and in the plurality of processing modules, the areas in charge of the plurality of unit areas are scanned, and pixels are simultaneously generated in a hierarchically divided area unit. The image processing method according to claim 26. 31. As the area in charge of each processing module,
Each of the areas obtained by dividing the predetermined unit area by the number of the processing modules is allocated, and the plurality of processing modules scan the areas in charge in the plurality of unit areas and hierarchically generate pixels in the divided area units at the same time. The image processing method according to claim 27.