JPH11272548A - Storage circuit control device and graphic operation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a storage circuit control device which can efficiently use a storage area of a texture buffer and enables simultaneous processing of picture data of plural pixels. SOLUTION: Texture data including pixel element for indicating colors of plural pixels arranged in a matrix shape are stored in a texture buffer 20 of a DRAM 16 and the plural pixel data stored in the texture buffer 20 are simultaneously accessed by using two-dimensional addresses (U, V) corresponding to two-dimensional arrangement of the plural pixels. The texture buffer 20 stipulates a unit block including the plural pixel data simultaneously accessed and stores the plural unit blocks composing the texture data so that they are successively positioned inside one-dimensional address space.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage circuit control apparatus and method capable of simultaneously processing image data for a plurality of pixels and efficiently using a storage area of a storage circuit, a graphic operation apparatus and a graphic operation apparatus therefor. And how to.

[0002]

2. Description of the Related Art Various CAD (Computer Aided Design)
Computer graphics are often used in systems and amusement devices. In particular, with the development of image processing technology in recent years, systems using three-dimensional computer graphics are rapidly spreading. In such three-dimensional computer graphics, a CRT in which pixels are arranged in a matrix
When displaying on a display such as a (Cathode Ray Tube), rendering (Rendering) processing is performed. In this rendering process, color data of each pixel is calculated, and the obtained color data is written to a display buffer (frame buffer) corresponding to the pixel. One of rendering techniques is polygon rendering. In this method, the color of the display screen is determined by expressing a three-dimensional model as a combination of triangular unit figures (polygons) and drawing the polygons as a unit.

In such a three-dimensional computer graphic system using polygon rendering, a texture mapping process is performed at the time of drawing. This texture mapping processing is for reading out texture data indicating an image pattern from a texture buffer in units of triangles, pasting the read out texture data to the surface of the three-dimensional model, and obtaining image data with high reality.

In this texture mapping process, as shown below, a two-dimensional texture address for specifying a pixel for displaying an image corresponding to image data is calculated, and this is stored in a texture buffer using the texture address. Refer to texture data. Specifically, first, the homogeneous coordinates (s, t) and the homogeneous term q of each vertex of the triangle are shown as (s ₁ , t ₁ , q ₁ ), (s ₂ , t)
_{From (2} , q ₂ ) and (s ₃ , t ₃ , q ₃ ), (s, t, q) of each pixel inside the triangle is obtained by linear interpolation. Here, the homogenous term q simply indicates an enlargement / reduction ratio.

Next, for each pixel, (s)
/ Q, t / q) is calculated, and texture coordinate data (u, v) is generated by multiplying s / q and t / q by the texture sizes USIZE and VSIZE, respectively. Next, the texture coordinate data (u, v) is converted into a texture address (U, V) on the texture buffer, and the texture data is read from the texture buffer using the texture address (U, V).

In the three-dimensional computer graphic system described above, texture data is stored in the storage area of the texture buffer so that the texture buffer can be directly referenced using the texture address (U, V).
It may be stored in a two-dimensional arrangement corresponding to a coordinate system. That is, a two-dimensional texture address (U, V)
May be used directly to access the texture data stored in the texture buffer. According to this method, the processing for accessing the texture data can be simplified. However, in this method, when a plurality of types of texture data are stored in the texture buffer, the texture data cannot be effectively used as shown in FIG. 12 due to the relationship between the size of the texture data to be stored and the size of the free area. There is a problem that a free area is generated and the storage area cannot be used efficiently.

For example, as shown in FIG. 12, a plurality of pieces of texture data 400,
When 401, 402, 403, and 406 are stored in the address space of the texture buffer so that they can be directly referred to by the texture address (U, V), the two-dimensional size and free space of the texture data to be stored are reduced.
Due to the relationship with the dimensional size, free areas 410 and 411 in which texture data cannot be stored occur.

As a result, it is necessary to use a texture buffer having a very large storage capacity as compared with the amount of texture data to be stored, and there is a problem that the system becomes large-scale and expensive.

Therefore, conventionally, in order to efficiently use the storage area of the texture buffer, 2 bits are calculated based on “physical address A = V × (texture width) + U”.
A one-dimensional physical address A is calculated from the dimensional texture address (U, V), and the texture buffer is accessed using the physical address A. By doing so, as shown in FIG. 13, texture data can be stored without creating an empty area in the storage area of the texture buffer. The “texture width” indicates an address length in the U direction in the address space of the texture buffer.

FIG. 14 is a partial block diagram of a conventional three-dimensional computer graphic system. As shown in FIG. 14, in the address translation device 104 built in the texture mapping device 101, as described above, the vertices of the triangle (s ₁ , t ₁ , q ₁ ), (s ₂ , t ₂ ,
From q ₂ ) and (s ₃ , t ₃ , q ₃ ), the physical address A of each pixel is calculated. Then, using the calculated physical address A, the texture data (R,
G, B, α) are read out, and the texture data (R, G, B, α) is pasted on pixels corresponding to the surface of the three-dimensional model, and drawing data S101 is generated. The drawing data S101 is stored in the display buffer 103.
Is written to.

Further, a fast three-dimensional computer graphic system, for example, as shown in FIG. 15, a built-in address translator 104 ₁ -104 _n, respectively n
Texture mapping devices 101 _{1 to} 101 _n , and texture mapping processes are simultaneously performed on n pixels at the same time to generate drawing data S 101 _{1 to} S ₁ .
01 _n are simultaneously written to the display buffer.

[0012]

By the way, the aforementioned 3
In a three-dimensional computer graphic system, for example,
In some cases, image data of pixels arranged in a predetermined rectangle in a 2 × 2 or 4 × 4 matrix is simultaneously read and processed. However, as mentioned above,
“Physical address A = V × (texture width) + U”
When the physical address A generated by using is used, it becomes difficult to guarantee that image data to be read simultaneously is stored in different banks of the texture buffer. Therefore, in the conventional three-dimensional computer graphic system, when simultaneously processing image data of a plurality of pixels, a texture buffer is accessed using a two-dimensional texture address (U, V).
Therefore, as described above, there is a problem that the storage area of the texture buffer cannot be used efficiently.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has a small-sized circuit configuration, can efficiently use a storage area of a texture buffer, and can simultaneously process image data of a plurality of pixels. It is an object of the present invention to provide a storage circuit control device and a graphic operation device.
Another object of the present invention is to provide a storage circuit control method and a graphic calculation method that can efficiently use the storage area of the texture buffer and that can simultaneously process image data of a plurality of pixels.

[0014]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art and to achieve the above-mentioned object, a storage circuit control device of the present invention uses colors of a plurality of pixels arranged in a matrix. The two-dimensional image data including the pixel data shown is stored in a storage circuit, and the plurality of pixels stored in the storage circuit are stored using a two-dimensional address (U, V) corresponding to the two-dimensional arrangement of the plurality of pixels. A storage circuit control device for simultaneously accessing the pixel data for, defining a unit block including a plurality of pixel data to be simultaneously accessed, a plurality of unit blocks constituting the two-dimensional image data, The data is stored in the storage circuit so as to be continuously located in the one-dimensional address space of the storage circuit.

Preferably, the storage circuit control device of the present invention comprises:
The storage circuit includes at least banks of the number of pixel data to be simultaneously accessed, and a plurality of simultaneously accessed pixel data included in the unit block are stored in mutually different banks of the storage circuit. Is done.

Further, in the storage circuit control device according to the present invention, preferably, the plurality of pixel data which are simultaneously accessed include:
This is pixel data of a plurality of pixels arranged in a matrix.

Preferably, the storage circuit controller of the present invention further comprises a U address of the two-dimensional address (U, V) represented by n (n is an integer of 1 or more) bits, and m (m: 1
Address generation means for generating a (n + m) -bit one-dimensional address by combining bit data constituting each of the two-dimensional address (U, V) and the V address expressed by the (integer) bits; Data access means for accessing the storage circuit using the generated one-dimensional address.

Preferably, in the storage circuit control device according to the present invention, the integer n and the integer m are equal, and k is (n
-1) <k <0, and the U address is (U [n
-1],. . , U [k],. . , U

[0]), and the V address is represented by (V [n-1],.
[K],. . , V

[0]), the address generating means generates the bit data U [n-1],. . , U [k],. . , U

[0] and each bit data V [n-
1],. . , V [k],. . , V

[0] in combination with a 2n-bit one-dimensional address (V [n-1], U
[N-1],. . , V [k], U [k],. . , V

[0], U

[0]) is generated.

Further, in the graphic operation device according to the first aspect of the present invention, the three-dimensional model is represented by a combination of a plurality of unit figures, and is included in pixel data indicating a color of each pixel located inside the unit figure. Using the same coordinates (s, t) and an address corresponding to the same term q, a plurality of pieces of pixel data constituting texture data, which is image data to be attached to the unit figure, stored in the storage circuit are read out simultaneously. A graphic operation device for pasting to a unit graphic, wherein a unit block composed of a plurality of pixel data which are simultaneously accessed is specified, and a plurality of unit blocks constituting the texture data are defined in a one-dimensional address space. A storage circuit for storing the data so as to be continuously located; and a division result (s / q, s / t) obtained by dividing the homogeneous coordinate (s, t) by the homogeneous term q. 2-dimensional address (U corresponding to),
V), a one-dimensional address generating means for generating a one-dimensional address from the two-dimensional address (U, V), and a storage unit using the generated one-dimensional address. Data reading means for reading the texture data in units of the unit block and attaching the texture data to the unit graphic.

In the graphic operation device according to the first aspect of the present invention, the division result (s / t) obtained by dividing the homogeneous coordinates (s, t) by the homogeneous term q in the two-dimensional address generation means.
(q, s / t), a two-dimensional address (U, V) is generated. Next, in the one-dimensional address generation means,
A one-dimensional address is generated from the generated two-dimensional address. Next, in the data reading means, the texture data is read from the storage circuit using the generated one-dimensional address, and is pasted on the unit figure.

Further, the graphic operation device according to the second aspect of the present invention expresses a three-dimensional model by a combination of a plurality of unit figures and is included in pixel data indicating a color of each pixel located inside the unit figure. Using the same coordinates (s, t) and an address corresponding to the same term q, a plurality of pieces of pixel data constituting texture data, which is image data to be attached to the unit figure, stored in the storage circuit are read out simultaneously. A graphic operation device for pasting to a unit graphic, wherein a unit block composed of a plurality of pixel data which are simultaneously accessed is specified, and a plurality of unit blocks constituting the texture data are defined in a one-dimensional address space. A storage circuit that stores the data so as to be continuously located, and three-dimensional coordinates (x, y,
z), polygon rendering data generating means for generating polygon rendering data including R (red), G (green), B (blue) data, homogeneous coordinates (s, t) and homogeneous terms q; Interpolation data generating means for generating interpolation data of a pixel located in the unit figure by interpolating polygon rendering data of a vertex, and converting the homogeneous coordinates (s, t) included in the interpolation data into the homogeneous term q A two-dimensional address generating means for generating a two-dimensional address (U, V) corresponding to a division result (s / q, s / t) obtained by the above-mentioned division, and a one-dimensional address from the two-dimensional address (U, V) Reading the texture data from the storage circuit in units of the unit block by using the generated one-dimensional address and attaching the texture data to the unit figure. And a data reading means.

In the graphic operation device according to the second aspect of the present invention, first, in the polygon rendering data generating means, three-dimensional coordinates (x, y, z), R (red), G ( Polygon rendering data including (green), B (blue) data, homogeneous coordinates (s, t) and homogeneous terms q is generated. Next, interpolation data generating means interpolates the polygon rendering data of the vertices of the unit graphic to generate interpolation data of the pixels located in the unit graphic. Next, in a two-dimensional address generation means, a division result (s / t) obtained by dividing the homogeneous coordinates (s, t) included in the interpolation data by the homogeneous term q.
A two-dimensional address (U, V) corresponding to (q, s / t) is generated. Next, one-dimensional address generation means generates a one-dimensional address from the generated two-dimensional address. Next, in the data reading means, the texture data is read from the storage circuit using the generated one-dimensional address, and is pasted on the unit figure.

Further, the graphic operation device according to the third aspect of the present invention expresses a three-dimensional model by a combination of a plurality of unit figures, and is included in pixel data indicating a color of each pixel located inside the unit figure. Using the same coordinates (s, t) and an address corresponding to the same term q, a plurality of pieces of pixel data constituting texture data, which is image data to be attached to the unit figure, stored in the storage circuit are read out simultaneously. A graphic operation device for pasting a unit figure, wherein three-dimensional coordinates (x,
y, z), R (red), G (green), B (blue) data, polygon rendering data generating apparatus for generating polygon rendering data including homogeneous coordinates (s, t) and homogeneous terms q, and the polygon It has a rendering device that performs a rendering process using the rendering data, and a bus that connects the polygon rendering data generation device and the rendering device. Here, the rendering device defines a unit block composed of the plurality of pixel data which are simultaneously accessed, and positions the plurality of unit blocks constituting the texture data continuously in a one-dimensional address space. A memory circuit for storing
Interpolation data generating means for interpolating the polygon rendering data input from the polygon rendering data generating device via the bus to generate interpolation data of pixels located in the unit graphic, and A two-dimensional address generating means for generating a two-dimensional address (U, V) corresponding to a division result (s / q, s / t) obtained by dividing the homogeneous coordinate (s, t) by the homogeneous term q; A one-dimensional address generation unit for generating a one-dimensional address from a dimensional address (U, V); and reading the texture data from the storage circuit using the generated one-dimensional address in units of the unit block. Data reading means for attaching to a figure.

In the third graphic operation device of the present invention, first, in the polygon rendering data generation device, the three-dimensional coordinates (x, y,
z), R (red), G (green), B (blue) data, polygon rendering data including homogeneous coordinates (s, t) and homogeneous terms q are generated. This polygon rendering data is transferred to the rendering device via the bus. Next, the following processing is performed in the rendering device. That is, the interpolation data generating means interpolates the polygon rendering data of the vertices of the unit graphic input via the bus, and generates the interpolation data of the pixels located in the unit graphic. Next, in a two-dimensional address generation means, a division result (s / t) obtained by dividing the homogeneous coordinates (s, t) included in the interpolation data by the homogeneous term q.
(q, s / t), a two-dimensional address (U, V) is generated. Next, one-dimensional address generation means generates a one-dimensional address from the generated two-dimensional address. Next, in the data reading means, the texture data is read from the storage circuit using the generated one-dimensional address, and is pasted on the unit figure.

According to a storage circuit control method of the present invention, two-dimensional image data including pixel data indicating colors of a plurality of pixels arranged in a matrix is stored in a storage circuit, and the two-dimensional arrangement of the plurality of pixels is performed. Two-dimensional address (U,
V) a storage circuit control method for simultaneously accessing the pixel data for a plurality of pixels stored in the storage circuit, wherein a unit block including the plurality of pixel data to be simultaneously accessed is defined. Then, the plurality of unit blocks constituting the two-dimensional image data are stored in the storage circuit so as to be continuously located in the one-dimensional address space of the storage circuit.

Further, according to the graphic calculation method of the present invention, the three-dimensional model is represented by a combination of a plurality of unit figures, and the homogeneous coordinates (s) included in the pixel data indicating the color of each pixel located inside the unit figure are displayed. , T) and the homogeneous term q
A graphic calculation method for simultaneously reading out a plurality of pieces of pixel data constituting texture data which is image data to be pasted to the unit figure stored in the storage circuit and pasting to the unit figure, using an address corresponding to A unit block composed of a plurality of pixel data to be simultaneously accessed is defined, and a plurality of unit blocks constituting the texture data are stored in a storage circuit so as to be continuously located in a one-dimensional address space. , The result of dividing the homogeneous coordinate (s, t) by the homogeneous term q (s /
q, s / t), a two-dimensional address (U, V) is generated, a one-dimensional address is generated from the two-dimensional address (U, V), and the one-dimensional address is generated using the generated one-dimensional address. The texture data is read from the storage circuit in units of the unit block, and is attached to the unit graphic.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, in this embodiment, a three-dimensional image which is applied to a home game machine or the like and which displays a desired three-dimensional image of an arbitrary three-dimensional object model on a display such as a CRT at a high speed. The computer graphic system will be described. First Embodiment FIG. 1 is a system configuration diagram of a three-dimensional computer graphic system 1 of the present embodiment. The three-dimensional computer graphic system 1 expresses a three-dimensional model as a combination of triangles (polygons), which are unit figures, determines the color of each pixel on a display screen by drawing the polygon, and performs polygon rendering processing for display on a display. It is a system that performs. In addition, in the three-dimensional computer graphic system 1, in addition to the (x, y) coordinates representing the position on the plane, the z coordinates representing the depth are used for 3D computer graphics system 3.
A three-dimensional model is represented, and an arbitrary point in the three-dimensional space is specified by the three coordinates (x, y, z).

As shown in FIG. 1, in the three-dimensional computer graphic system 1, a main memory 2, an I / O interface circuit 3, a main processor 4, and a rendering circuit 5 are connected via a main bus 6.
Hereinafter, the function of each component will be described. The main processor 4, for example, according to the progress of the game,
The necessary graphic data is read from the main memory 2 and the graphic data is clipped (Cli
Performs pping) processing, lighting (lighting) processing, and geometry (Geometry) processing to generate polygon rendering data. The main processor 4 outputs the polygon rendering data S4 to the rendering circuit 5 via the main bus 6. I / O interface circuit 3
Inputs polygon rendering data from the outside as necessary, and outputs it to the rendering circuit 5 via the main bus 6.

Here, the polygon rendering data is
(X, y, z, R, G, B, α,
s, t, q, F). here,
The (x, y, z) data indicates the three-dimensional coordinates of the vertices of the polygon, and the (R, G, B) data indicates the red, green, and blue luminance values at the three-dimensional coordinates, respectively. The data α indicates a blending (mixing) coefficient of R, G, and B data of a pixel to be drawn and a pixel already stored in the display buffer 21. In the (s, t, q) data, (s, t) indicates the homogeneous coordinates of the corresponding texture, and q indicates the homogeneous term. here,
"S / q" and "t / q" are multiplied by the texture sizes USIZE and VSIZE, respectively, to obtain texture coordinate data (u, v). Texture buffer 2
The access to the texture data stored in 0 is performed using the texture coordinate data (u, v). The F data indicates the α value of the fog. That is, the polygon rendering data indicates physical coordinate values of each vertex of the triangle, and data of the color, texture, and fog value of each vertex.

Hereinafter, the rendering circuit 5 will be described in detail. As shown in FIG. 1, the rendering circuit 5
DDA (Digital Differential Anarizer) setup circuit 10, triangle DDA circuit 11, texture engine circuit 12, memory I / F circuit 13, CRT controller circuit 14, RAMDAC circuit 15, DRAM1
6 and SRAM 17.

FIG. 2 is a block diagram of the DRAM 16, the SRAM 17, and a block of the memory I / F circuit 13 having an access function to the DRAM 16 and the SRAM 17. As shown in FIG. 2, the DRAM 16 and the SRAM 17 shown in FIG.
Are the memory modules 200, 201, 202, 203
Having. The memory module 200 includes a memory 210,
211. The memory 210 includes banks 210 ₁ and 210 ₂ constituting a part of the DRAM 16 and an SRAM 17.
And banks 220 ₁ and 220 ₂ which constitute a part of. In addition, the memory 211 has banks 211 ₁ and 211 ₂ forming a part of the DRAM 16 and banks 221 ₁ and 221 ₂ forming a part of the SRAM 17. The banks 220 ₁ , 220 ₂ , 221 ₁ , and 221 ₂ can be simultaneously accessed. Note that the memory module 2
01, 202, and 202 have basically the same configuration as the memory module 200.

Here, the memory modules 200 and 20
1, 202, and 203 are a texture buffer 20, a display buffer 21, and a Z buffer 2 shown in FIG.
2 and all functions of the texture CLUT buffer 23. That is, the memory modules 200, 201,
Each of 202 and 203 stores all of the texture data, drawing data ((R, G, B) data), z data, and texture color look-up table data of the corresponding pixel. However, the memory modules 200, 20
Reference numerals 1, 202, and 203 store data on mutually different pixels. Here, texture data, drawing data, z data, and texture color look-up table data for 16 pixels that are simultaneously processed are stored in different banks 210 ₁ , 210 ₂ , 211 ₁ , and 21.
12 ₂ , 212 ₁ , 212 ₂ , 213 ₁ , 213 ₂ , 21
4 _1, 214 _2, 215 _1, 215 _2, 216 _1, 21
6 _2, 217 _1, 217 is ₂ in the storage. This allows
Data for 16 pixels can be simultaneously accessed to the DRAM 16.

The banks 220 ₁ , 220 ₂ , 221
₁ , 221 ₂ , 222 ₁ , 222 ₂ , 223 ₁ , 223
₂ , 224 ₁ , 224 ₂ , 225 ₁ , 225 ₂ , 226
₁ , 226 ₂ , 227 ₁ , and 227 ₂ have banks 210 ₁ , 210 ₂ , 211 ₁ , 211 ₂ , and 21, respectively.
21 ₁ , 212 ₂ , 213 ₁ , 213 ₂ , 214 ₁ , 21
4 _2, 215 _1, 215 _2, 216 _1, 216 _2, 21
7 _1, 217 ₂ copies of the texture data stored in the is stored.

Next, the storage pattern of the texture data in the texture buffer 20 will be described. Here, as shown in FIG.
A case will be described in which pixel data P _{0 to} P ₁₅ indicating color data of pixels arranged in a 2 × 8 matrix are simultaneously accessed. The pixel data P _{0 to} P ₁₅ need to be stored in different banks of the SRAM 17 constituting the texture buffer 20. In the present embodiment, the pixel data P ₀ , P ₁ , P ₈ , and P ₈ are stored in the banks 220 ₁ 220 ₂ of the memory 210 and the banks 221 ₁ 221 ₂ of the memory 211 shown in FIG. The pixel data P ₂ , P ₃ , P ₁₀ , and P ₁₁ are stored in the banks 222 ₁ 222 ₂ and the memory 21 of the memory 212 shown in FIG.
3 are stored in banks 223 ₁ and 223 ₂ . Further, the pixel data P ₄ , P ₅ , P ₁₂ , and P ₁₃ are stored in the banks 224 ₁ 224 ₂ of the memory 214 and the banks 225 ₁ , 225 ₂ of the memory 215 shown in FIG. 2, respectively. Further, the pixel data P ₆ , P ₇ , P ₁₄ , and P ₁₅ are stored in the banks 226 ₁ 226 ₂ of the memory 216 and the banks 227 ₁ , 227 ₂ of the memory 217 shown in FIG.

In the present embodiment, a set of pixel data P _{0 to} P ₁₅ of pixels located in a rectangular area to be processed at the same time is called a unit block R _i . For example, texture data representing one image As shown in FIG. 4, it is composed of unit blocks R _{0 to} R _BA-1 arranged in a B × A matrix. The unit blocks R _{0 to} R _BA-1 are, as shown in FIG.
The texture buffer 20 is stored in the SRAM 17 so as to have continuous addresses in a one-dimensional address space. The pixel data P _{0 to} P ₁₅ in each of the unit blocks R _{0 to} R _BA-1 are stored in different banks of the SRAM 17 so as to have continuous addresses in a one-dimensional address space. That is, the texture buffer 20 stores unit blocks of pixel data to be accessed simultaneously so as to have continuous addresses in a one-dimensional address space.

DDA Setup Circuit 10 The DDA setup circuit 10 linearly interpolates the values of the vertices of the triangle on the physical coordinate system in the subsequent triangle DDA circuit 11 to obtain the color and depth information of each pixel inside the triangle. Prior to obtaining, polygon rendering data S
For the (z, R, G, B, α, s, t, q, F) data 4 shown in FIG. 4, a setup operation for obtaining a difference between the side of the triangle and the horizontal direction is performed. Specifically, the setup calculation uses the values of the start point and the end point, and the distance between the start point and the end point, and calculates the variation of the value to be obtained when the unit length is moved. .

The DDA setup circuit 10 outputs the calculated variation data S10 to the triangle DDA circuit 11.

The triangle DDA circuit 11 triangle DDA circuit 11 uses the variation data S10 input from the DDA set-up circuit 10, the linearly interpolated at each pixel inside the triangle (z, R, G,
B, α, s, t, q, F) data are calculated. The triangle DDA circuit 11 calculates the (x, y) data of each pixel and the (z, R, G, B,
α, s, t, q, F) data and DDA data S11
To the texture engine circuit 12. In the present embodiment, the triangle DDA circuit 11 outputs the DDA data S11 to the texture engine circuit 12 in units of 8 (= 2 × 4) pixels located in a rectangle to be processed in parallel.

Texture engine circuit 12 The texture engine circuit 12 selects a reduction ratio of texture data, calculates “s / q” and “t / q”, calculates texture coordinate data (u, v), Calculation processing of one-dimensional texture address (U, V), generation of one-dimensional physical address A, reading of (R, G, B, tα) data from texture buffer 20, and mixing processing (texture α blending processing) ) Are sequentially performed in a pipeline manner. At this time, the texture engine circuit 12 simultaneously performs processing for eight pixels located within a predetermined rectangular area in parallel.

FIG. 6 is a configuration diagram of the texture engine circuit 12. As shown in FIG. 6, the texture engine circuit 12 includes a reduction ratio calculating circuit 304, a texture data reading circuit 305, and a texture α blending circuit 30.
6.

The reduction rate calculation circuit 304 calculates the DDA data S
(S, t, q) data S11 for eight pixels included in
by using a a ₁ ~S11a _8, calculates the reduction ratio lod of texture data. Here, the reduction ratio indicates how much the texture data of the original image has been reduced. When the reduction ratio of the original image is set to 1/1, the reduction ratio is 1/2, 1/4. , 1/8,. . . Becomes

For example, as shown in FIG. 7, the texture buffer 20 stores texture data 320, 321, 322, 323, and 324 of lod = 0, 1, 2, 3, and 4. As shown in FIG. 7, the address space of the storage area of the texture buffer 20 is expressed in the U and V coordinate systems, and the reference address (start address) of the storage area in which texture data corresponding to a plurality of reduction rates is stored. Address) is calculated based on the reduction ratio lod. In the example shown in FIG. 2, the texture data 320, 321, 32
2,323 reference addresses are (ubase ₀ , vba
se ₀ ), (ubase ₁ , vbase ₁ ), (uba
se ₂ , vbase ₂ ), (ubase ₃ , vbase
₃ ) The texture address (U, V) for each pixel in the texture data stored in the texture buffer 20 is a reference address (ubas).
e, vbase) and texture coordinate data (u, v)
Is added to the address.

[Texture Data Readout Circuit 305]
The texture data readout circuit 305 generates (s, t, q) data S1 for eight pixels included in the DDA data S11.
1a _{1 to} S11a ₈ , the reduction ratio lod from the reduction ratio calculation circuit 304, the texture sizes USSIZE and VS
Enter the IZE, corresponding to each of the 8 pixels to read out the texture data S17 ₁ ~S17 ₈ from the texture buffer 20, which texture α blending circuit 3
06 is output.

FIG. 8 shows a texture data read circuit 30.
5 is a configuration diagram of FIG. FIG. 9 is a flowchart of the process in the texture data reading circuit 305. FIG.
As shown in FIG.
Are a u / v calculation circuit 501, a U / V calculation circuit 502, a physical address generation circuit 503, and an access control circuit 50
4 Step S21: Texture data reading circuit 305
In First, u, in the v calculation circuit 501, the 8 pixels of (s, t, q) for each data S11a ₁ ~S11a _8, the operation for dividing the s data by the q data and the t data q An operation of dividing by data is performed to calculate division results “s / q” and “t / q”. And
The division results “s / q” and “t / q” are multiplied by the texture sizes USIZE and VSIZE, respectively, to obtain texture coordinate data (u ₁ , v ₁ ) corresponding to each pixel.
(U ₈ , v ₈ ) is calculated.

Step S22: U, V calculation circuit 502
Is a reference address (ubas) corresponding to the reduction ratio lod by referring to an address table prepared in advance, for example.
e, vbase). Then, the U and V calculation circuit 50
2 is a reference address (ubase, vbase);
A case where the texture coordinate data (u ₁ , v ₁ ) to (u ₈ , v ₈ ) input from the u, v calculation circuit 501 are added to represent the storage area of the texture buffer 20 in a two-dimensional UV coordinate system Texture addresses (U ₁ , V ₁ ) to (U
₈ , V ₈ ).

Step S23: Physical address generation circuit 5
03 indicates the texture addresses (U ₁ , V ₁ ) to (U ₈ , V ₈ ) input from the U, V calculation circuit 502 based on the following equation (1) for obtaining the physical address A _i . Conversion into one-dimensional physical addresses A _{1 to} A ₈ in the address space. Note that “A” shown on the right side of the following equation (1) corresponds to FIG.
The subscript “A” of the unit block _RBA shown in FIG.

[0047]

## EQU1 ## Physical address A _i = (V _i × A / 2 + U _i / 8) (1)

At this time, the physical addresses A _{1 to} A ₈ are continuous addresses in the address space shown in FIG. 5, and the SRs constituting the texture buffer 20 shown in FIG.
These are addresses of different banks of AM17. For example, physical addresses A ₁ , A ₂ , A ₃ , A ₄ , A ₅ , A ₆ ,
A ₇ and A ₈ are the banks 220 ₁ 22 shown in FIG.
0 ₂ , 221 ₁ , 221 ₂ , 222 ₁ , 222 ₂ , 22
3 _1, 223 pixel data P ₀ of the unit blocks R _2A shown in FIGS. 4 and 5 in the _second storage area, P _1, P _2, P
₃ , P ₄ , P ₅ , P ₆ , and P ₇ indicate the addresses at which they are stored.

Step S24: access control circuit 504
Outputs the one-dimensional physical addresses A _{1 to} A ₈ input from the physical address generation circuit 503 to the texture buffer 20 via the memory I / F circuit 13 shown in FIG. G, B, tα) data S1
7 ₁ ~S17 _8, i.e. reading out the pixel data P ₀ to P _7. At the same time, the pixel data P _{8 to} P ₁₅ are also read. At this time, the pixel data P _{0 to} P
₁₅ are stored in different banks, so that they can be read simultaneously. The SRAM 17 stores a copy of the texture data stored in the texture buffer 20, and stores the texture engine circuit 1
2 is actually SRA via the memory I / F circuit 13.
The texture data stored in M17 is read.

Step S25: access control circuit 504
Is read in step S24 (R, G, B, tα)
And it outputs the data S17 ₁ ~S17 ₈ texture α blending circuit 306.

[Texture α Blend Circuit 306] The texture α blend circuit 306 includes (R, G, B) data S11b ₁ to S8 for eight pixels included in the DDA data S11.
And S11b _8, the texture data reading circuit 305 is read out (R, G, B, tα ) data S17 ₁ ~S1
Type and 7 _8, respectively (R, G, B) data S11
and b ₁ ~S11b _8, included in the data _{S17 1 ~S17 8 (R, G} , B) and a data, the data S17 ₁ ~S1
Were mixed in a mixing value indicated by tα contained 7 _8, (R,
G, B) Data S306 _{1 to} S306 ₈ are generated. Then, α data S11d _{1 to} S11 included in the DDA data
11d ₈ and (R, G, B) data S306 _{1 to} S30
6 ₈ and is, (R, G, B, α) data S12a ₁ ~S1
As 2a _8, it is outputted to the memory I / F circuit 13.

The texture engine circuit 12 directly uses (R, G, B, tα) data read from the texture buffer 20 in the case of the full color system.
On the other hand, in the case of the index color system, the texture engine circuit 12 stores the color lookup table (CLUT) created in advance in the texture CLUT buffer 2.
3 is transferred to and stored in the built-in SRAM, and (R, G, B) data corresponding to the color index read from the texture buffer 20 is obtained using this color lookup table.

Memory I / F circuit 13 The memory I / F circuit 13 has (R, G, B, α) data S12a input from the texture engine circuit 12.
_{1 ~S12a 8,} that is, the z-data corresponding to the pixel data S12a, compares the z-data stored in the z-buffer 22, the image drawn by the pixel data S12a input, the previous display buffer 21
It is determined whether or not the image is located on the near side (viewpoint side) from the image written in the pixel data.
The z data stored in the z buffer 22 is updated with the z data corresponding to 12a. Further, the memory I / F circuit 13
The (R, G, B) data included in the pixel data S12a and the display buffer 2
1 is mixed with the (R, G, B) data stored in No. 1 using a mixed value indicated by the α data corresponding to the pixel data S12a, that is, a so-called α blending process is performed, and the mixed (R, G, B) is performed. The data is written (driven) into the display buffer 21.

The memory I / F circuit 13 simultaneously accesses the DRAM 16 for 16 pixels. FIG.
As shown in (1), the memory I / F circuit 13 has memory controllers 240, 241, 242, 243, address converters 250, 251, 252, 253, a distributor 260, and a read controller 262.

The distributor 260, for example, inputs (R, G, B) data for 16 pixels at the time of writing and converts them into four image data S260 ₀ , S260 ₁ , S260 each consisting of data for 4 pixels. ₂ , S26
0 ₃ is divided into an address converter 250, respectively,
251, 252, and 253. Here, (R, G, B) data and z data for one pixel are 3
It consists of 2 bits.

Address converters 250, 251, 25
2, 253, when writing, the distributor 26
Addresses corresponding to (R, G, B) data and z data input from 0 are respectively stored in the memory module 20.
0, 201, 202, and 203, and converted addresses S250, S251, and S25, respectively.
2, and S253 are output to the memory controller 240.

Memory controllers 240, 241, 24
2, 243 are wiring groups 270, 271, 27, respectively.
2, 273 via the memory modules 200, 201,
It is connected to the memory modules 202, 203 and controls access to the memory modules 200, 201, 202, 203 at the time of writing. Specifically, the memory controllers 240, 241, 242, and 243 transfer the (R, G, B) data and z data for four pixels input from the distributor 260 to the wiring groups 270, 271, 272, 2
73, the memory modules 200, 201, 20
2, 203 are written simultaneously. At this time, for example, in the memory module 200, the banks 210 ₁ , 210 ₂ ,
Each of the pixels 210 ₃ and 210 ₄ has (R, G,
B) Data and z data are stored. The same applies to the memory modules 201, 202, and 203. In the present embodiment, the wiring groups 270, 271, 272,
Each of the 273 is 256 bits.

The read controller 262 is connected to the wiring group 2
80, the memory modules 200, 201, 20
2, 203, and at the time of reading, from the memory modules 200, 201, 202, 203, texture data (R,
G, B) data, z data, and texture color look-up table data are read out via the wiring group 280. In the present embodiment, the wiring group 280 is 1024
Is a bit.

CRT Controller Circuit 14 The CRT controller circuit 14 generates an address to be displayed on a CRT (not shown) in synchronization with the given horizontal and vertical synchronization signals, and issues a request to read display data from the display buffer 21 to the memory I / O. Output to the F circuit 13. In response to this request, the memory I / F circuit 13 reads out display data from the display buffer 21 in a fixed chunk. The CRT controller circuit 14 stores the display data read from the display buffer 21 in F.
An IFO (First In First Out) circuit is built in, and an RGB index value is output to the RAMDAC circuit 15 at fixed time intervals.

RAMDAC circuit 15 The RAMDAC circuit 15 stores R, G, and B data corresponding to each index value, and stores digital R, G, and B data corresponding to the RGB index values input from the CRT controller circuit 14. The B data is transferred to the D / A converter to generate analog R, G, B data. The RAMDAC circuit 15 generates the generated R, G,
Output B data to CRT.

Hereinafter, the operation of the three-dimensional computer graphic system 1 will be described. In the three-dimensional computer graphic system 1 shown in FIG. 1, polygon rendering data S4 is output from the main processor 4 to the DDA setup circuit 10 via the main bus 6, and the DDA setup circuit 10 calculates the difference between the side of the triangle and the horizontal direction. Is generated. Then, the variation data S10 is output from the DDA setup circuit 10 to the triangle DDA circuit 11.

Next, in the triangle DDA circuit 11, based on the variation data S10, linear interpolation (z, R, G, B, α, s,
t, q, F) are generated. And triangle D
From the DA circuit 11 to the texture engine circuit 12, the (x, y) data of each pixel and the (z, R, G, B, α, s, t, q, F) data at the (x, y) coordinates are obtained. But,
It is output as DDA data S11.

Next, in the reduction ratio calculation circuit 304 of the texture engine circuit 12 shown in FIG.
(S, t, q) data S11 for eight pixels included in
using a ₁ ~S11a _8, the reduction ratio of the texture data is calculated, the reduction ratio lod is output to the texture data reading circuit 305.

Next, the texture data reading circuit 30
5, using the physical address A of the one-dimensional address space shown in FIG. 5 generated based on the above equation (1) based on the flow shown in FIG. 9, the texture data S17 from the texture buffer 20 (SRAM 17). ₁ to
S17 ₈ is read, the texture data S17 ₁ ~S17 ₈ read is output to the texture α blending circuit 306.

At this time, under the control of the read controller 262 shown in FIG.
16 pixels of the texture data including texture data S17 ₁ ~S17 ₈ is bank 220 _1, 220 ₂ constituting the SRAM 17, 221 _1, 221 _2, 222 _1,
222 ₂ , 223 ₁ , 223 ₂ , 224 ₁ , 224 ₂ ,
225 ₁ , 225 ₂ , 226 ₁ , 226 ₂ , 227 ₁ ,
227 _{2 are} read.

Next, in the texture α blending circuit 306, the (R, G, B) data S11b _{1 to} S11b ₈
When, in the data _{S17 1 ~S17 8 (R, G} ,
B) and data are mixed in a mixing value indicated by tα included in the data _{S17 1 ~S17 8, (R,} G, B) data S306 ₁ ~S306 ₈ is generated. And DD
Α data S11d _{1 to} S11d included in A data
And _{8, (R, G, B} ) data S306 ₁ ~S306 ₈ is, (R, G, B, α) data S12a ₁ ~S12
a ₈ , that is, as the pixel data S12a, the memory I
/ F circuit 13.

Then, in the memory I / F circuit 13,
Pixel data S input from the texture engine circuit 12
The z data corresponding to the pixel data S12a is compared with the z data stored in the z buffer 22, and the image drawn by the input pixel data S12a is located before the image previously written to the display buffer 21. It is determined whether or not it is located on the (viewpoint side). If it is located on the near side, the z data stored in the z buffer 22 is updated with the z data corresponding to the image data S12a.

Next, in the memory I / F circuit 13, the image data S12a includes (R, G,
B) data and the (R, G, B) data already stored in the display buffer 21 are the pixel data S12
The mixed data is mixed with the mixed value indicated by the α data corresponding to “a”, and the mixed (R, G, B) data is written to the display buffer 21.

At this time, under the control of the memory controllers 240, 341, 242 and 243 shown in FIG.
16 through the wiring groups 270, 271, 272, and 273.
The (R, G, B) data for the pixels are stored in the banks 210 ₁ , 21 constituting the display buffer 21 shown in FIG.
0 ₂ , 211 ₁ , 211 ₂ , 212 ₁ , 212 ₂ , 21
3 _1, 213 _2, 214 _1, 214 _2, 215 _1, 21
Written to 5 ₂ , 216 ₁ , 216 ₂ , 217 ₁ , 217 ₂

As described above, according to the three-dimensional computer graphic system 1, the one-dimensional physical address A is generated from the two-dimensional texture address (U, V) indicating the two-dimensional address space of the texture buffer 20. , Texture buffer 2 using this physical address.
By accessing 0, texture data can be stored in a continuous storage area. Therefore, a free area as shown in FIG. A1 does not occur, and the storage area of the texture buffer 20 can be used efficiently. As a result, the storage capacity of the texture buffer 20 can be reduced, and the device can be reduced in size and cost.

[0071] Further, according to the three-dimensional computer graphic system 1, a two-dimensional texture data as shown in FIG. 4, the unit blocks R _i which processes are performed simultaneously
Are stored in the texture buffer 20 so as to have a continuous address as shown in FIG. The pixel data P _{0 to} P ₁₅ in the unit block R _i are stored in mutually different banks. As a result, simultaneous access of the pixel data P ₀ to P ₁₅ in the unit block R _i stored in the texture buffer 20 is ensured.

Second Embodiment A three-dimensional computer graphic system according to the present embodiment uses a one-dimensional arrangement based on the arrangement of pixels corresponding to simultaneously accessed pixel data and the texture address (U, V) in a two-dimensional UV coordinate system. An address generation method for generating the physical address A of the first embodiment is different from the three-dimensional computer graphic system 1 of the first embodiment. The other configuration of the three-dimensional computer graphic system of the present embodiment is the same as that of the three-dimensional computer graphic system 1 of the first embodiment.

In this embodiment, as shown in FIG.
The texture buffer 20 is simultaneously accessed for the pixel data of 16 pixels arranged in a × 4 matrix. Hereinafter, the reading processing of the texture data in the three-dimensional computer graphic system of the present embodiment will be described with reference to FIGS. 8, 9 and 10. Step S21: Texture data reading circuit 305
In First, u, in the v calculation circuit 501, the 8 pixels (s, t, q) for each data S11a ₁ ~S11a _8, the operation for dividing the s data by the q data,
An operation of dividing t data by q data is performed to calculate division results “s / q” and “t / q”. Then, the division results “s / q” and “t / q” are multiplied by the texture sizes USIZE and VSIZE, respectively, to obtain texture coordinate data (u ₁ , v ₁ ) to (u) corresponding to each pixel.
_8, v ₈₎ is calculated.

Step S22: U, V calculation circuit 502
Is a reference address (ubas) corresponding to the reduction ratio lod by referring to an address table prepared in advance, for example.
e, vbase). Then, the U and V calculation circuit 50
2 is a reference address (ubase, vbase);
A case where the texture coordinate data (u ₁ , v ₁ ) to (u ₈ , v ₈ ) input from the u, v calculation circuit 501 are added to represent the storage area of the texture buffer 20 in a two-dimensional UV coordinate system Texture addresses (U ₁ , V ₁ ) to (U
₈ , V ₈ ). The texture addresses (U ₉ , V ₉ ) for other simultaneously processed pixel data
(U ₁₆ , V ₁₆ ) is also the texture address (U ₁ , V ₁ )
~ (U ₈ , V ₈ ) are generated at the same time as the generation or at a different timing. In the present embodiment, “i” is replaced by “1 ≦ i ≦
When set to an integer of 16 ", U _i and V _i of the texture address (U _i, V _i), respectively composed of 2 bits shown in the following (2) and (3).

[0075]

U _i = ｛U _i [1], U _i

[0]｝ ... (2)

[0076]

V _i = ３V _i [1], V _i

[0]｝ ... (3)

Step S23: Physical address generation circuit 5
Pattern 03, U, for each texture address input from V calculation circuit _{502 (U 1, V 1)} ~ (U 16, V 16), the bits constituting the U _i and V _i, shown below (4) To generate a physical address A. Since the generation of the physical address A is realized only by a simple bit replacement operation, it can be performed at a high speed with a small circuit configuration.

[0078]

## EQU4 ## Physical address A _i = (V _i [1], U _i [1], V _i

[0], U _i

[0]) ... (4)

The generation of the physical address A _i shown in the above (4) is shown in FIG. 11 shows the values of V _i the vertical axis V is represented by 2 bits, indicates the value of U _i of the horizontal axis U is represented by 2 bits, are arranged in a matrix form "0" to "15" This shows the value of the physical address _Ai . That is, a two-dimensional texture address (U) located in a matrix represented by 2-bit U _i and V _i
i , V _i ) are from “0” to “1” according to the above equation (4).
5 "is converted into a continuous one-dimensional physical address _Ai .

A specific example of the conversion of the above equation (4) will be described with reference to FIG. For example, U _i = (0,1), V _i =
In the case of (1, 0), the physical address A = (1, 0, 0, 1) according to the above equation (4), which is “9” when represented by a decimal number. Here, U _i = (0,1) = 1
And V _i = (1, 0) = 2, and in FIG. 11, the position A of U = 1 and V = 2 is “9”. When U _i = (1,1) and V _i = (0,1), the physical address A = (0,
1,1,1), which is "7" when represented by a decimal number. Here, U _i = (1,1) = 3 and V _i =
(0,1) = 1, and in FIG. 11, U = 1, V =
The position B of No. 2 is “7”.

Step S24: access control circuit 504
Outputs the one-dimensional physical addresses A _{1 to} A ₁₆ input from the physical address generation circuit 503 to the texture buffer 20 via the memory I / F circuit 13 shown in FIG. G, B, tα) data S1
Read the 7 ₁ ~S17 _8. In the SRAM 17,
A copy of the texture data stored in the texture buffer 20 is stored, and the texture engine circuit 12 actually sends the copy of the texture data via the memory I / F circuit 13.
The texture data stored in the RAM 17 is read.

Step S25: access control circuit 504
Is read in step S24 (R, G, B, tα)
And it outputs the data S17 ₁ ~S17 ₈ texture α blending circuit 306.

As described above, according to the three-dimensional computer graphic system of the present embodiment, the following effects can be obtained in addition to the effects of the three-dimensional computer graphic system 1 of the first embodiment. it can. That is, according to the three-dimensional computer graphic system of the present embodiment, the texture buffer 2
A one-dimensional physical address A can be generated by combining each bit constituting U and V of a two-dimensional texture address (U, V) indicating a two-dimensional address space of 0 based on the above equation (4). . Here, the physical address A _i
Can be realized by a simple bit operation, so that the generation of the physical address A can be realized at high speed with a small-scale circuit configuration.

The present invention is not limited to the above embodiment. In the above-described embodiment, the number of pixels that are simultaneously processed is eight, but this number is arbitrary, and may be four, for example. However, it is desirable that the number of pixels to be simultaneously processed is a power of two. In the above-described embodiment, the number of simultaneous accesses to the pixel data stored in the DRAM 16 and the SRAM 17 is set to 1
Although 6, the number may be 4 or 64, for example.

Further, in the three-dimensional computer graphic system 1 shown in FIG. 1 described above, the configuration using the SRAM 17 is exemplified, but the configuration without the SRAM 17 may be adopted. The texture buffer 20 and the texture CLUT buffer 23 shown in FIG.
May be provided outside.

Further, in the three-dimensional computer graphic system 1 shown in FIG. 1, the case where the geometry processing for generating the polygon rendering data is performed by the main processor 4 is illustrated, but the rendering circuit 5 may be used.

[0087]

As described above, according to the storage circuit control device and method of the present invention, simultaneous access of a plurality of pixel data is guaranteed and two-dimensional image data is efficiently stored in the storage circuit. it can. As a result, the storage area of the storage circuit can be used effectively. Further, according to the graphic operation device and the method thereof of the present invention, simultaneous access of a plurality of pixel data constituting the texture data is guaranteed, and the texture data can be efficiently stored in the storage circuit. As a result, the storage area of the storage circuit can be used effectively. According to the storage circuit control device and method and the graphic operation device of the present invention, a storage circuit is accessed by generating a one-dimensional address by combining bits constituting a two-dimensional address (U, V). Address conversion can be performed at high speed.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of a three-dimensional computer graphic system according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a DRAM, an SRAM, and a block having a function of accessing a DRAM and an SRAM of a memory I / F circuit shown in FIG. 1;

FIG. 3 is a diagram for explaining pixel data included in texture data and accessed at the same time;

FIG. 4 is a diagram for explaining a unit block included in texture data;

FIG. 5 is a diagram for explaining an address space of a texture buffer;

FIG. 6 is an internal configuration diagram of the texture engine circuit shown in FIG. 1;

FIG. 7 is a diagram for explaining texture data at a plurality of reduction rates stored in the texture buffer shown in FIG. 1 and subjected to MIPMAP filtering processing;

FIG. 8 is a configuration diagram of a texture data reading circuit.

FIG. 9 is a flowchart of a process in a texture data reading circuit shown in FIG. 6;

FIG. 10 is a diagram for explaining pixel data included in texture data and simultaneously accessed in the three-dimensional computer graphic system according to the second embodiment of the present invention;

FIG. 11 is a diagram showing a two-dimensional texture address (U, V) to a one-dimensional physical address A in the three-dimensional computer graphic system according to the second embodiment of the present invention;
FIG. 6 is a diagram for explaining a method of generating a.

FIG. 12 is a diagram for explaining a problem when a plurality of types of texture data are stored in a texture buffer by directly using a two-dimensional texture address (U, V).

FIG. 13 shows an example of using a one-dimensional physical address.
FIG. 4 is a diagram for explaining a storage state when a plurality of types of texture data are stored in a texture buffer.

FIG. 14 is a partial configuration diagram of a conventional three-dimensional computer graphic system.

FIG. 15 is a partial configuration diagram of a conventional three-dimensional computer graphic system capable of high-speed processing.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Three-dimensional computer graphic system, 2 ... Main memory, 3 ... I / O interface circuit, 4 ... Main processor, 5 ... Rendering circuit, 10 ... DDA setup circuit, 11 ... Triangle DDA circuit, 1
2 Texture engine circuit, 13 Memory I / F circuit, 14 CRT controller circuit, 15 RAMDA
C circuit, 16 DRAM, 17 SRAM, 20 texture buffer, 21 display buffer, 22
Z buffer, 23 ... texture CLUT buffer, 30
4, a reduction ratio calculation circuit, 305, a texture data readout circuit, 306, a texture α blend circuit, 200,
201, 202, 203 ... memory module, 210,
211, 212, 213, 214, 215, 216, 2
17: memory, 240, 241, 242, 243: memory controller, 250, 251, 252, 253: address converter, 260: distributor, 26
2, read controller, 270, 271, 272,
273, 280 ... wiring group

Claims (25)

[Claims] 1. A two-dimensional image data including pixel data indicating colors of a plurality of pixels arranged in a matrix is stored in a storage circuit, and a two-dimensional address (U, U) corresponding to the two-dimensional arrangement of the plurality of pixels is stored. V) a storage circuit control device for simultaneously accessing the pixel data for a plurality of pixels stored in the storage circuit, wherein a unit block including the plurality of pixel data to be simultaneously accessed is defined; A storage circuit control device that stores a plurality of unit blocks constituting the two-dimensional image data in the storage circuit so as to be continuously located in a one-dimensional address space of the storage circuit. 2. The storage circuit includes at least banks of the number of pixel data to be accessed at the same time. The storage circuit control device according to claim 1, wherein the storage circuit is stored in a different bank. 3. The storage circuit control device according to claim 1, wherein the plurality of pixel data accessed simultaneously is pixel data of a plurality of pixels arranged in a matrix. 4. A U-address of the two-dimensional address (U, V) represented by n (n is an integer of 1 or more) bits, and m
An address for generating a (n + m) -bit one-dimensional address by combining bit data constituting each of the two-dimensional address (U, V) and the V address represented by (m is an integer of 1 or more) bits The storage circuit control device according to claim 1, further comprising: a generation unit; and a data access unit configured to access the storage circuit using the generated one-dimensional address. 5. The integer n is equal to the integer m, k is an integer satisfying (n-1) <k <0, and the U address is (U [n-1],.
[K],. . , U [0]), and the V address is represented by (V [n−1],.
[K],. . , V [0]), the address generating means generates each bit data U [n−1],. . , U [k],. . , U [0]
And each bit data V [n-
1],. . , V [k],. . , V [0] in combination with a 2n-bit one-dimensional address (V [n−1], U
[N-1],. . , V [k], U [k],. . , V
5. The storage circuit control device according to claim 4, wherein [0], U [0]) are generated. 6. A three-dimensional model is represented by a combination of a plurality of unit figures, and a homogeneous coordinate (s, t) and a homogeneous term q included in pixel data indicating a color of each pixel located inside the unit figure. A graphic operation device for simultaneously reading out a plurality of pieces of pixel data constituting texture data, which is image data to be attached to the unit figure, stored in a storage circuit and using the corresponding address to attach to the unit figure; A storage circuit that defines a unit block composed of a plurality of pixel data to be processed, and stores the plurality of unit blocks constituting the texture data so as to be continuously located in a one-dimensional address space; A two-dimensional address (U, U) corresponding to a division result (s / q, s / t) obtained by dividing the next coordinate (s, t) by the homogeneous term q.
V) for generating a one-dimensional address from the two-dimensional address (U, V); and a one-dimensional address generating means for generating a one-dimensional address from the two-dimensional address (U, V). A graphic operation device comprising: a data reading unit that reads the texture data in units of the unit block and attaches the texture data to the unit graphic. 7. The storage circuit includes at least banks of the number of pixel data to be simultaneously accessed, and a plurality of simultaneously accessed pixel data included in the unit block are mutually stored in the storage circuit. The graphic operation device according to claim 6, wherein the graphic operation device is stored in a different bank. 8. The graphic operation device according to claim 6, wherein said plurality of pixel data accessed simultaneously is pixel data of a plurality of pixels arranged in a matrix. 9. The one-dimensional address generating means includes: a U address of the two-dimensional address (U, V) represented by n (n is an integer of 1 or more) bits; and m (m is an integer of 1 or more) 7. The graphic operation device according to claim 6, wherein bit data constituting each of the two-dimensional address (U, V) expressed in bits and the V address is combined to generate a (n + m) -bit one-dimensional address. . 10. The integer n is equal to the integer m, k is an integer satisfying (n-1) <k <0, and the U address is (U [n-1],.
[K],. . , U [0]), and the V address is represented by (V [n−1],.
[K],. . , V [0]), the one-dimensional address generation means generates each bit data U [n−1],. . , U [k],. . , U
[0] and each bit data V [n-
1],. . , V [k],. . , V [0] in combination with a 2n-bit one-dimensional address (V [n−1], U
[N-1],. . , V [k], U [k],. . , V
10. The graphic operation device according to claim 9, wherein [0], U [0]) are generated. 11. A three-dimensional model is represented by a combination of a plurality of unit figures, and a homogeneous coordinate (s, t) and a homogeneous term q included in pixel data indicating a color of each pixel located inside the unit figure. A graphic operation device for simultaneously reading out a plurality of pieces of pixel data constituting texture data, which is image data to be attached to the unit figure, stored in a storage circuit and using the corresponding address to attach to the unit figure; A storage circuit that defines a unit block composed of a plurality of pieces of pixel data, and stores the plurality of unit blocks constituting the texture data so as to be continuously located in a one-dimensional address space; The three-dimensional coordinates (x, y,
z), polygon rendering data generating means for generating polygon rendering data including R (red), G (green), B (blue) data, homogeneous coordinates (s, t) and homogeneous terms q; Interpolation data generating means for generating interpolation data of a pixel located in the unit graphic by interpolating polygon rendering data of a vertex; and calculating the homogeneous coordinates (s, t) included in the interpolation data by the homogeneous term q A two-dimensional address generating means for generating a two-dimensional address (U, V) according to the division result (s / q, s / t) obtained by the division by (1), and a one-dimensional address from the two-dimensional address (U, V) Using the generated one-dimensional address, reading the texture data from the storage circuit in units of the unit block, and attaching the texture data to the unit figure. Graphic operation device having data reading means for reading data. 12. The storage circuit includes at least banks of the number of pixel data to be accessed at the same time. 12. The graphic operation device according to claim 11, wherein the graphic operation device is stored in a different bank. 13. The graphic operation device according to claim 11, wherein said plurality of pixel data which are simultaneously accessed are pixel data of a plurality of pixels arranged in a matrix. 14. The one-dimensional address generation means, wherein n (n
Is a U address of the two-dimensional address (U, V) represented by 1 or more bits, and m (m is an integer of 1 or more)
12. The graphic operation device according to claim 11, wherein a one-dimensional address of (n + m) bits is generated by combining bit data constituting each of the two-dimensional address (U, V) expressed in bits and the V address. . 15. The integer n is equal to the integer m, k is an integer satisfying (n-1) <k <0, and the U address is (U [n-1],.
[K],. . , U [0]), and the V address is represented by (V [n−1],.
[K],. . , V [0]), the one-dimensional address generation means generates each bit data U [n−1],. . , U [k],. . , U
[0] and each bit data V [n-
1],. . , V [k],. . , V [0] in combination with a 2n-bit one-dimensional address (V [n−1], U
[N-1],. . , V [k], U [k],. . , V
15. The graphic operation device according to claim 14, wherein [0], U [0]) are generated. 16. A three-dimensional model is represented by a combination of a plurality of unit figures, and a homogeneous coordinate (s, t) and a homogeneous term q included in pixel data indicating a color of each pixel located inside the unit figure. A graphic operation device for simultaneously reading out a plurality of pieces of pixel data constituting texture data, which is image data to be attached to the unit figure, stored in a storage circuit and using the corresponding address to attach to the unit figure; , The three-dimensional coordinates (x, y,
a polygon rendering data generating device for generating polygon rendering data including z), R (red), G (green), B (blue) data, homogeneous coordinates (s, t) and homogeneous terms q; And a bus connecting the polygon rendering data generation device and the rendering device. The rendering device comprises: a unit block configured from the plurality of pixel data that are simultaneously accessed. And a storage circuit for storing a plurality of unit blocks constituting the texture data so as to be continuously located in a one-dimensional address space, and input from the polygon rendering data generating device via the bus. Interpolate the polygon rendering data and place it in the unit figure. Interpolation data generating means for generating interpolation data of a pixel to be processed, and a division result (s / q, s / t) obtained by dividing the homogeneous coordinates (s, t) included in the interpolation data by the homogeneous term q. Two-dimensional address generation means for generating the two-dimensional address (U, V), one-dimensional address generation means for generating a one-dimensional address from the two-dimensional address (U, V), And a data reading unit for reading the texture data from the storage circuit in units of the unit block and attaching the texture data to the unit graphic. 17. The storage circuit includes at least banks of the number of pixel data to be simultaneously accessed, and a plurality of simultaneously accessed pixel data included in the unit block are connected to each other by the storage circuit. 17. The graphic operation device according to claim 16, wherein the graphic operation device is stored in a different bank. 18. The graphic operation device according to claim 16, wherein said plurality of pixel data accessed simultaneously is pixel data of a plurality of pixels arranged in a matrix. 19. The one-dimensional address generation means, wherein n (n
Is a U address of the two-dimensional address (U, V) represented by 1 or more bits, and m (m is an integer of 1 or more)
17. The graphic operation device according to claim 16, wherein a bit data constituting each of the two-dimensional address (U, V) expressed in bits and the V address is combined to generate a (n + m) -bit one-dimensional address. . 20. The integer n is equal to the integer m, k is an integer satisfying (n-1) <k <0, and the U address is (U [n-1],.
[K],. . , U [0]), and the V address is represented by (V [n−1],.
[K],. . , V [0]), the one-dimensional address generation means generates each bit data U [n−1],. . , U [k],. . , U
[0] and each bit data V [n-
1],. . , V [k],. . , V [0] in combination with a 2n-bit one-dimensional address (V [n−1], U
[N-1],. . , V [k], U [k],. . , V
20. The graphic operation device according to claim 19, wherein [0], U [0]) is generated. 21. A two-dimensional image data containing pixel data indicating colors of a plurality of pixels arranged in a matrix is stored in a storage circuit, and a two-dimensional address (U, U) corresponding to the two-dimensional arrangement of the plurality of pixels is stored. V) a storage circuit control method for simultaneously accessing the pixel data for a plurality of pixels stored in the storage circuit, wherein a unit block including the plurality of pixel data to be simultaneously accessed is defined; A storage circuit control method for storing a plurality of unit blocks constituting the two-dimensional image data in the storage circuit so as to be continuously located in a one-dimensional address space of the storage circuit. 22. The storage circuit control method according to claim 21, wherein said plurality of pixel data accessed simultaneously is pixel data of a plurality of pixels arranged in a matrix. 23. A U address of the two-dimensional address (U, V) represented by n (n is an integer of 1 or more) bits, and m
(M is an integer of 1 or more) By combining bit data constituting each of the two-dimensional address (U, V) and the V address expressed by bits, a (n + m) -bit one-dimensional address is generated, 22. The storage circuit control method according to claim 21, further comprising accessing the storage circuit using the generated one-dimensional address. 24. The integer n is equal to the integer m, k is an integer satisfying (n-1) <k <0, and the U address is (U [n-1],.
[K],. . , U [0]), and the V address is represented by (V [n−1],.
[K],. . , V [0]), each bit data U [n−1],. . ,
U [k],. . , U [0] and each bit data V [n−1],. . , V [k],. . , V
[0] in combination with a 2n-bit one-dimensional address (V [n-1], U [n-1], ..., V [k], U
[K],. . , V [0], U [0]). 25. A solid model is represented by a combination of a plurality of unit figures, and a homogeneous coordinate (s, t) and a homogeneous term q included in pixel data indicating a color of each pixel located inside the unit figure. A graphic operation method for simultaneously reading out a plurality of pieces of pixel data constituting texture data which is image data to be pasted to said unit figure and stored in a storage circuit using said corresponding address and pasting said pixel data to said unit figure; A unit block composed of a plurality of pieces of pixel data to be stored, and storing the plurality of unit blocks constituting the texture data in a storage circuit so as to be continuously located in a one-dimensional address space; A two-dimensional address (U, U) corresponding to a division result (s / q, s / t) obtained by dividing the next coordinate (s, t) by the homogeneous term q.
V); generating a one-dimensional address from the two-dimensional address (U, V); reading the texture data from the storage circuit using the generated one-dimensional address in units of the unit block; A graphic operation method for pasting the unit figure.