JPH11288467A - Data transferring device and graphic arithmetic unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transferring device for suppressing the influence of cross-talk without making this device large-scaled. SOLUTION: Wiring 2701 -270256 , 2711 -271256 , 2721 -272256 , and 2731 -273256 through which read data are transferred, and wiring 2801 -2801024 through which write data are transferred are alternately arranged with a wiring pitch 1.6 μm. In this case, the transfer of the read data and the transfer of the write data are not simultaneously operated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device capable of suppressing the influence of crosstalk caused by data transfer between blocks without increasing the size of the device, and a graphic operation device capable of providing high-quality images. About.

[0002]

2. Description of the Related Art Various CAD (Computer Aided Design)
Computer graphics are often used in systems and amusement devices. In particular, with the development of image processing technology in recent years, systems using three-dimensional computer graphics are rapidly spreading. In such three-dimensional computer graphics, a CRT in which pixels are arranged in a matrix
When displaying on a display such as a (Cathode Ray Tube), rendering (Rendering) processing is performed. In this rendering process, color data of each pixel is calculated, and the obtained color data is written to a display buffer (frame buffer) corresponding to the pixel. One of rendering techniques is polygon rendering. In this method, the color of the display screen is determined by expressing a three-dimensional model as a combination of triangular unit figures (polygons) and drawing the polygons as a unit.

In polygon rendering, coordinates (x, y, z) of each vertex of a triangle in a physical coordinate system are used.
, Color data (R, G, B) and homogeneous coordinates (s, t) of texture data indicating an image pattern to be bonded
A process of interpolating the value of the same term q and the same term inside the triangle is performed. Here, the homogenous term q is simply a scale factor such as the UV of the actual texture buffer.
Coordinates in the coordinate system, that is, texture coordinate data (U, V) are obtained by dividing (s / q, t / q) = (u, v) by dividing homogeneous coordinates (s, t) by homogeneous terms q. It depends on the result of multiplication of the texture sizes USIZE and VSIZE.

In such a three-dimensional computer graphic system using polygon rendering, when rendering, texture data is read from a texture buffer, and the read texture data is pasted on the surface of a three-dimensional model to provide a high-reality image. A texture mapping process for obtaining data is performed.

[0005] Incidentally, the above-described three-dimensional computer graphic system contains a large number of arithmetic processing blocks and control blocks, and data transfer between these blocks is performed via a bus. Also,
In such a three-dimensional computer graphic system, operations on a plurality of pixels are performed simultaneously, and the bus width according to the data transfer amount per unit time is very large. In particular, when a DRAM is incorporated, the bus width is further increased in order to improve the performance.

[0006]

However, when data is transferred via such a bus, a problem of crosstalk occurs. When the crosstalk occurs, the reliability of the data transfer decreases, and the image quality of the image displayed on the display deteriorates.

As a method of suppressing such crosstalk, for example, there is a method of increasing a space between wirings for transferring data between blocks or using a transstate. However, the former method can be applied when the bus width is small. However, when the bus width is large as in a three-dimensional computer graphic system, if the wiring pitch is increased, the area associated with the wiring becomes very large. However, there is a problem that the system is enlarged. Further, there is a problem that the manufacturing cost increases and the yield decreases. Further, the latter method has a problem that it is very difficult to detect a failure.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and it is possible to suppress the influence of crosstalk without increasing the size of a device, and to detect data that does not involve difficulty in failure detection such as a transstate. It is an object to provide a transfer device and a graphic operation device.

[0009]

In order to solve the above-mentioned problems of the prior art and to achieve the above-mentioned object, a data transfer device according to the present invention uses a data transfer device from a first circuit block to a second circuit block. And a plurality of second wirings for transferring data from the second block to the first block are alternately arranged, and a plurality of first wirings for transferring data from the second block to the first block are arranged alternately. And the data transfer from the second circuit block to the first circuit block is performed at different timings.

In the data transfer device of the present invention, data is not transferred to the second wiring while data is being transferred to the first wiring.
During data transfer to the second wiring, no data is transferred to the first wiring. Therefore, during data transfer to the first wiring, the distance between the wirings at which data may change at the same time is the distance between the first wirings. Further, during data transfer to the second wiring, the distance between the wirings at which data may change simultaneously is the distance between the second wirings. Therefore, as compared with the case where the first wiring and the second wiring are arranged adjacent to each other, the distance between the wirings in which data may change simultaneously can be doubled, and the influence of crosstalk can be suppressed. .

Here, while one of the first wiring and the second wiring is transferring data, the other is held at a predetermined level.

Preferably, the data transfer device of the present invention outputs the input data to the first wiring when the transfer direction designating data for designating the direction of the data transfer is at a first level. A first logic circuit for holding the first wiring at a predetermined level when the transfer direction instruction data is at a second level, and a data input when the transfer direction instruction data is at a second level To the second wiring, and a second logic circuit for holding the second wiring at a predetermined level when the transfer direction instruction data is at the first level.

A graphic operation device according to a first aspect of the present invention expresses a three-dimensional model by a combination of a plurality of unit figures, and has homogeneous coordinates (s, t) and homogeneous terms q included in image data for each pixel. A graphics computing device that generates drawing data by associating texture data with the unit figure based on the texture data, and a storage unit that stores the texture data and the drawing data; and for each pixel, a texture corresponding to the pixel. Drawing data generating means for reading out data from the storage means via a plurality of first wirings to generate drawing data and writing the generated drawing data to the storage means via a plurality of second wirings; Then, the first wirings and the second wirings are alternately arranged.

In the data transfer device according to the first aspect of the present invention, first, texture data is read from the storage means via the first wiring by the drawing means. At this time,
No data is transferred to the second wiring, and the distance between the wirings at which data may change simultaneously is the distance between the first wirings. Then, drawing data is generated in the drawing means, and the generated drawing data is transferred to the storage means via the second wiring and stored in the storage means. At this time, data is not transferred to the first wiring, and the distance between the wirings at which data may change simultaneously is the distance between the second wirings.

The graphic operation device according to the second aspect of the present invention performs operations on a plurality of pixels at the same time in order to represent a predetermined shape to be displayed on a display by a combination of unit figures, and becomes a processing target. A graphic operation device that performs processing using an operation result of a pixel located inside the unit graphic as an effective one, wherein three-dimensional coordinates (x, y, z), A polygon rendering data generating device for generating polygon rendering data including R (red), G (green), B (blue) data, homogeneous coordinates (s, t) and homogeneous terms q, and using the polygon rendering data A rendering device for performing a rendering process; a bus connecting the polygon rendering data generation device and the rendering device; The rendering device has a storage unit for storing texture data and drawing data, and for each pixel, reads out the texture data corresponding to the pixel from the storage unit via a plurality of first wirings to read the drawing data. Drawing data generation means for generating and writing the generated drawing data to the storage means via a plurality of second wirings, wherein the first wirings and the second wirings are alternately arranged. ing.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, in this embodiment, a three-dimensional image which is applied to a home game machine or the like and which displays a desired three-dimensional image of an arbitrary three-dimensional object model on a display such as a CRT at a high speed. The computer graphic system will be described. FIG. 1 is a system configuration diagram of a three-dimensional computer graphic system 1 of the present embodiment. 3D computer graphic system 1
Is a system that expresses a three-dimensional model as a combination of triangles (polygons), which are unit figures, determines the color of each pixel on a display screen by drawing the polygon, and performs a polygon rendering process for displaying on a display.
In addition, in the three-dimensional computer graphic system 1, a three-dimensional object is represented using z coordinates representing a depth in addition to (x, y) coordinates representing a position on a plane, and the (x, y, z) An arbitrary point in the three-dimensional space is specified by the three coordinates.

As shown in FIG. 1, in a three-dimensional computer graphic system 1, a main memory 2, an I / O interface circuit 3, a main processor 4 and a rendering circuit 5 are connected via a main bus 6.
Hereinafter, the function of each component will be described. The main processor 4, for example, according to the progress of the game,
The necessary graphic data is read from the main memory 2 and the graphic data is clipped (Cli
Performs pping) processing, lighting (lighting) processing, and geometry (Geometry) processing to generate polygon rendering data. The main processor 4 outputs the polygon rendering data S4 to the rendering circuit 5 via the main bus 6. I / O interface circuit 3
Inputs polygon rendering data from the outside as necessary, and outputs it to the rendering circuit 5 via the main bus 6.

Here, the polygon rendering data is
(X, y, z, R, G, B, α,
s, t, q, F). here,
The (x, y, z) data indicates the three-dimensional coordinates of the vertices of the polygon, and the (R, G, B) data indicates the red, green, and blue luminance values at the three-dimensional coordinates, respectively. The data α indicates a blending (mixing) coefficient of R, G, and B data of a pixel to be drawn and a pixel already stored in the display buffer 21. In the (s, t, q) data, (s, t) indicates the homogeneous coordinates of the corresponding texture, and q indicates the homogeneous term. here,
"S / q" and "t / q" are multiplied by the texture sizes USIZE and VSIZE, respectively, to obtain texture coordinate data (u, v). Texture buffer 2
The access to the texture data stored in 0 is performed using the texture coordinate data (u, v). The F data indicates the α value of the fog. That is, the polygon rendering data indicates physical coordinate values of each vertex of the triangle, and data of the color, texture, and fog value of each vertex.

Hereinafter, the rendering circuit 5 will be described in detail. As shown in FIG. 1, the rendering circuit 5
DDA (Digital Differential Anarizer) setup circuit 10, triangle DDA circuit 11, texture engine circuit 12, memory I / F circuit 13, CRT controller circuit 14, RAMDAC circuit 15, DRAM1
6 and SRAM 17. The DRAM 16 functions as a texture buffer 20, a display buffer 21, a z buffer 22, and a texture CLUT buffer 23.

DDA Setup Circuit 10 The DDA setup circuit 10 linearly interpolates the values of the vertices of the triangle on the physical coordinate system in the subsequent triangle DDA circuit 11 to obtain the color and depth information of each pixel inside the triangle. Prior to obtaining, polygon rendering data S
For the (z, R, G, B, α, s, t, q, F) data 4 shown in FIG. 4, a setup operation for obtaining a difference between the side of the triangle and the horizontal direction is performed. Specifically, the setup calculation uses the values of the start point and the end point, and the distance between the start point and the end point, and calculates the variation of the value to be obtained when the unit length is moved. .

The DDA setup circuit 10 outputs the calculated variation data S10 to the triangle DDA circuit 11.

The triangle DDA circuit 11 triangle DDA circuit 11 uses the variation data S10 input from the DDA set-up circuit 10, the linearly interpolated at each pixel inside the triangle (z, R, G,
B, α, s, t, q, F) data are calculated. The triangle DDA circuit 11 calculates the (x, y) data of each pixel and the (z, R, G, B,
α, s, t, q, F) data and DDA data S11
To the texture engine circuit 12. In the present embodiment, the triangle DDA circuit 11 outputs the DDA data S11 to the texture engine circuit 12 in units of 8 (= 2 × 4) pixels located in a rectangle to be processed in parallel.

Texture engine circuit 12 The texture engine circuit 12 selects a reduction ratio of the texture data, calculates “s / q” and “t / q”, calculates texture coordinate data (u, v), The process of calculating the address (U, V), the process of reading (R, G, B, tα) data from the texture buffer 20, and the mixing process (texture α blending process) are sequentially performed by a pipeline method. At this time, the texture engine circuit 12 simultaneously performs processing for eight pixels located within a predetermined rectangular area in parallel.

FIG. 2 is a configuration diagram of the texture engine circuit 12. As shown in FIG. 2, the texture engine circuit 12 includes a reduction ratio calculation circuit 304, a texture data readout circuit 305, and a texture α blend circuit 30.
6.

The reduction ratio calculation circuit 304 calculates the DDA data S
(S, t, q) data S11 for eight pixels included in
by using a a ₁ ~S11a _8, calculates the reduction ratio lod of texture data. Here, the reduction ratio indicates how much the texture data of the original image has been reduced. When the reduction ratio of the original image is set to 1/1, the reduction ratio is 1/2, 1/4. , 1/8,. . . Becomes

The texture buffer 20 stores, for example, texture data 320, 321, 322, 323 and 324 of lod = 0, 1, 2, 3 and 4 as shown in FIG. As shown in FIG. 3, the address space of the storage area of the texture buffer 20 is expressed by a U, V coordinate system, and the reference address (start address) of the storage area in which texture data corresponding to a plurality of reduction rates is stored. Address) is calculated based on the reduction ratio lod. In the example shown in FIG. 6, the texture data 320, 321, 32
2,323 reference addresses are (ubase ₀ , vba
se ₀ ), (ubase ₁ , vbase ₁ ), (uba
se ₂ , vbase ₂ ), (ubase ₃ , vbase
₃ ) The texture address (U, V) for each pixel in the texture data stored in the texture buffer 20 is a reference address (ubas).
e, vbase) and texture coordinate data (u, v)
Is added to the address.

[Texture data read circuit 305]
The texture data readout circuit 305 generates (s, t, q) data S1 for eight pixels included in the DDA data S11.
1a _{1 to} S11a ₈ , the reduction ratio lod from the reduction ratio calculation circuit 304, the texture sizes USSIZE and VS
Enter the IZE, corresponding to each of the 8 pixels to read out the texture data S17 ₁ ~S17 ₈ from the texture buffer 20, which texture α blending circuit 3
06 is output.

FIG. 4 shows a texture data read circuit 3
It is a flowchart of the process in 05. Step S21: Texture data reading circuit 305
Is of 8 pixels (s, t, q) data S11a ₁ ~S1
For each 1a _8, the operation for dividing the s data by the q data, performs the operation for dividing the t data by the q data, calculates the division results "s / q" and "t / q".
Then, the division results “s / q” and “t / q” are multiplied by the texture sizes USIZE and VSIZE, respectively, to obtain texture coordinate data (u ₁ ,
v ₁₎ is calculated - a (u _8, v _8).

Step S22: The texture data reading circuit 305 obtains a reference address (ubase, vbase) corresponding to the reduction ratio lod, for example, by referring to an address table prepared in advance. Then, the texture data read circuit 305 outputs the reference address (uba).
(se, vbase) and the texture coordinate data (u ₁ , v ₁ ) to (u ₈ , v ₈ ) calculated in step S21, and the texture address (physical address of the texture buffer 20 in the UV coordinate system) is obtained. U ₁ ,
V ₁ ) to (U ₈ , V ₈ ).

[0030] Step S23: the texture data reading circuit 305, the texture address generated in step S22 the _{(U 1, V 1) ~} (U 8, V 8), via the memory I / F circuit 13 shown in FIG. 1 , Is output to the texture buffer 20 and is texture data (R, G, B,
tα) reads the data S17 ₁ ~S17 _8. Note that S
A copy of the texture data stored in the texture buffer 20 is stored in the RAM 17, and the texture engine circuit 12 actually stores the texture data stored in the SRAM 17 via the memory I / F circuit 13. read out.

Step S24: The texture data read circuit 305 reads (R,
G, and B, t alpha) data S17 ₁ ~S17 ₈ texture α blending circuit 306.

[Texture α blend circuit 306]
The Sture α blend circuit 306 converts the DDA data S11
(R, G, B) data S11b for eight pixels included₁~
S11b₈And the texture data reading circuit 305
Read (R, G, B, tα) data S17₁~ S1
7₈And (R, G, B) data S11
b₁~ S11b₈And data S17 ₁~ S17₈Included in
(R, G, B) data to be transferred to data S17.₁~ S1
7₈Are mixed at a mixing value represented by tα contained in (R,
G, B) Data S306₁~ S306₈Generate So
Then, α data S11d included in the DDA data₁~ S
11d₈And (R, G, B) data S306₁~ S30
6₈Is (R, G, B, α) data S12a₁~ S1
2a₈Is output to the memory I / F circuit 13.

The texture engine circuit 12 directly uses (R, G, B, tα) data read from the texture buffer 20 in the case of the full color system.
On the other hand, in the case of the index color system, the texture engine circuit 12 stores the color lookup table (CLUT) created in advance in the texture CLUT buffer 2.
3 is transferred to and stored in the built-in SRAM, and (R, G, B) data corresponding to the color index read from the texture buffer 20 is obtained using this color lookup table.

FIG. 5 is a configuration diagram of the DRAM 16, the SRAM 17, and a block of the memory I / F circuit 13 having a function of accessing the DRAM 16 and the SRAM 17. As shown in FIG. 5, the DRAM 16 and the SRAM 17 shown in FIG.
Are the memory modules 200, 201, 202, 203
Having. The memory module 200 includes a memory 210,
211. The memory 210 includes banks 210 ₁ and 210 ₂ constituting a part of the DRAM 16 and an SRAM 17.
And banks 220 ₁ and 220 ₂ which constitute a part of. In addition, the memory 211 has banks 211 ₁ and 211 ₂ forming a part of the DRAM 16 and banks 221 ₁ and 221 ₂ forming a part of the SRAM 17. The banks 220 ₁ , 220 ₂ , 221 ₁ , and 221 ₂ can be simultaneously accessed. Note that the memory module 2
01, 202, and 202 have basically the same configuration as the memory module 200.

[0035]
1 Here, the memory modules 200, 201, 202, 2
03 has all the functions of the texture buffer 20, display buffer 21, Z buffer 22, and texture CLUT buffer 23 shown in FIG. That is, the memory modules 200, 201, 202, 203
Store all of texture data, drawing data ((R, G, B) data), z data, and texture color look-up table data of the corresponding pixel. However, the memory modules 200, 201, 202,
Reference numeral 203 stores data on mutually different pixels. Here, texture data, drawing data, z data, and texture color look-up table data for 16 pixels that are simultaneously processed are stored in mutually different banks 210 ₁ , 210 ₂ , 211 ₁ , 211 ₂ , and 212.
₁ , 212 ₂ , 213 ₁ , 213 ₂ , 214 ₁ , 214
₂ , 215 ₁ , 215 ₂ , 216 ₁ , 216 ₂ , 217
_1, 217 is ₂ in the storage. Thereby, the DRAM 16
, Data for 16 pixels can be simultaneously accessed.

The banks 220 ₁ , 220 ₂ , 221
₁ , 221 ₂ , 222 ₁ , 222 ₂ , 223 ₁ , 223
₂ , 224 ₁ , 224 ₂ , 225 ₁ , 225 ₂ , 226
₁ , 226 ₂ , 227 ₁ , and 227 ₂ have banks 210 ₁ , 210 ₂ , 211 ₁ , 211 ₂ , and 21, respectively.
21 ₁ , 212 ₂ , 213 ₁ , 213 ₂ , 214 ₁ , 21
4 _2, 215 _1, 215 _2, 216 _1, 216 _2, 21
7 _1, 217 ₂ copies of the texture data stored in the is stored.

Memory I / F circuit 13 The memory I / F circuit 13 has (R, G, B, α) data S12a input from the texture engine circuit 12.
_{1 ~S12a 8,} that is, the z-data corresponding to the pixel data S12a, compares the z-data stored in the z-buffer 22, the image drawn by the pixel data S12a input, the previous display buffer 21
It is determined whether or not the image is located on the near side (viewpoint side) from the image written in the pixel data.
The z data stored in the z buffer 22 is updated with the z data corresponding to 12a. Further, the memory I / F circuit 13
The (R, G, B) data included in the pixel data S12a and the display buffer 2
1 is mixed with the (R, G, B) data stored in No. 1 using a mixed value indicated by the α data corresponding to the pixel data S12a, that is, a so-called α blending process is performed, and the mixed (R, G, B) is performed. The data is written (driven) into the display buffer 21.

The memory I / F circuit 13 simultaneously accesses the DRAM 16 for 16 pixels. FIG.
As shown in (1), the memory I / F circuit 13 has memory controllers 240, 241, 242, 243, address converters 250, 251, 252, 253, a distributor 260, and a read controller 262.

The distributor 260, for example, inputs (R, G, B) data for 16 pixels at the time of writing and converts them into four image data S260 ₀ , S260 ₁ , S260 each consisting of data for 4 pixels. ₂ , S26
0 ₃ is divided into an address converter 250, respectively,
251, 252, and 253. Here, (R, G, B) data and z data for one pixel are 3
It consists of 2 bits.

Address converters 250, 251, 25
2, 253, when writing, the distributor 26
Addresses corresponding to (R, G, B) data and z data input from 0 are respectively stored in the memory module 20.
0, 201, 202, and 203, and converted addresses S250, S251, and S25, respectively.
2, and S253 are output to the memory controller 240.

Memory controllers 240, 241, 24
2, 243 are wiring groups 270, 271, 27, respectively.
2, 273 via the memory modules 200, 201,
It is connected to the memory modules 202, 203 and controls access to the memory modules 200, 201, 202, 203 at the time of writing. Specifically, the memory controllers 240, 241, 242, and 243 transfer the (R, G, B) data and z data for four pixels input from the distributor 260 to the wiring groups 270, 271, 272, 2
73, the memory modules 200, 201, 20
2, 203 are written simultaneously. At this time, for example, in the memory module 200, the banks 210 ₁ , 210 ₂ ,
Each of the pixels 210 ₃ and 210 ₄ has (R, G,
B) Data and z data are stored. The same applies to the memory modules 201, 202, and 203. In the present embodiment, the wiring groups 270, 271, 272,
Each of the 273 is 256 bits.

The read controller 262 is connected to the wiring group 2
80, the memory modules 200, 201, 20
2, 203, and at the time of reading, from the memory modules 200, 201, 202, 203, texture data (R,
G, B) data, z data, and texture color look-up table data are read out via the wiring group 280. In the present embodiment, the wiring group 280 is 1024
Is a bit.

In the memory I / F circuit 13, the memory controllers 240, 241, 242, 243 and the DRAM 16
Groups 270, 2 connecting between the semiconductor device and the SRAM 17
71, 272, 273 and read controller 262
And a wiring group 280 connecting between the DRAM 16 and the SRAM 17 are alternately arranged as shown in FIG. Specifically, constituting 256 wirings 270 _{1-270 256} constituting the wiring group 270, a wiring group 271 2
56 wires 271 _{1-271 256,} the wiring group 272 and 256 of the wiring 272 _{1-272 256} constituting the 256 wires 273 ₁ forming the wiring group 273 to 273
A total of 1024 wirings of ₂₅₆ are arranged in order, and a wiring group 280 is formed between these adjacent wirings.
The configuration is such that 24 wires 280 _{1 to} 280 ₁₀₂₄ are arranged in order. That is, the wirings 270 _{1 to} 270 ₂₅₆ , 2
71 _{1 to} 271 ₂₅₆ , 272 _{1 to} 272 ₂₅₆ , 273 ₁
273 ₂₅₆ and wirings 280 _{1 to} 280 ₁₀₂₄ are alternately arranged at a wiring pitch of 1.6 μm.

As described above, at the time of writing, the wiring 2
70 _{1 to} 270 ₂₅₆ , wires 271 _{1 to} 271 ₂₅₆ , wires 272 _{1 to} 272 _256, and wires 273 _{1 to} 273 ₂₅₆
Via the memory controllers 240, 241, 24
2, 243 to the memory modules 200, 201, 20
Data is transferred to 2,203. On the other hand, at the time of reading, data is transferred from the memory modules 200, 201, 202, and 203 to the reading controller 262 via the wirings 280 _{1 to} 280 ₁₀₂₄ .

Here, the write operation and the read operation are as follows.
Since they are not performed at the same time, the distance between wirings where signal changes occur
Is every other, that is, 3.2 μm. Therefore, at the same time
Wiring for transmitting data that causes a signal change
Significantly reduces crosstalk effects compared to placement
Can be reduced. Specifically, at the time of writing, the wiring 270₁
~ 270₂₅₆, Wiring 271₁~ 271₂₅₆, Wiring 272
₁~ 272₂₅₆And wiring 273₁~ 273₂₅₆Has a
Data flows (signal changes occur), but the wiring 280₁~
280₁₀₂₄No data flows (no signal change
No). Therefore, the interval between the wirings where a signal change occurs is determined by the wiring 2
70₁~ 270₂₅₆, 271₁~ 271₂₅₆, 272₁
~ 272₂₅₆, 273₁~ 273₂₅₆The distance between each other
3.2 μm. On the other hand, at the time of reading,
0₁~ 280₁₀₂₄Data flows (signal changes occur
), But the wiring 270₁~ 270₂₅₆, Wiring 271₁~ 2
71₂₅₆, Wiring 272₁~ 272₂₅₆And wiring 273
₁~ 273₂₅₆Does not flow data (signal change occurs
Absent). Therefore, the distance between wirings where signal changes occur
280 ₁~ 280₁₀₂₄3.2 μm, which is the distance between
Become.

CRT controller circuit 14 The CRT controller circuit 14 generates an address to be displayed on a CRT (not shown) in synchronization with the given horizontal and vertical synchronization signals, and issues a request to read display data from the display buffer 21 to the memory I / O. Output to the F circuit 13. In response to this request, the memory I / F circuit 13 reads out display data from the display buffer 21 in a fixed chunk. The CRT controller circuit 14 stores the display data read from the display buffer 21 in F.
An IFO (First In First Out) circuit is built in, and an RGB index value is output to the RAMDAC circuit 15 at fixed time intervals.

RAMDAC Circuit 15 The RAMDAC circuit 15 stores R, G, and B data corresponding to each index value, and stores digital R, G, and B data corresponding to the RGB index values input from the CRT controller circuit 14. The B data is transferred to the D / A converter to generate analog R, G, B data. The RAMDAC circuit 15 generates the generated R, G,
Output B data to CRT.

Hereinafter, the operation of the three-dimensional computer graphic system 1 will be described. The polygon rendering data S4 is output from the main processor 4 to the DDA setup circuit 10 via the main bus 6, and
In the A setup circuit 10, variation data S10 indicating the difference between the side of the triangle and the horizontal direction is generated. Then, from the DDA setup circuit 10, the triangle D
The variation data S10 is output to the DA circuit 11.

Next, the triangle DDA circuit 11 linearly interpolates (z, R, G, B, α, s, s) at each pixel inside the triangle based on the variation data S10.
t, q, F) are generated. And triangle D
From the DA circuit 11 to the texture engine circuit 12, the (x, y) data of each pixel and the (z, R, G, B, α, s, t, q, F) data at the (x, y) coordinates are obtained. But,
It is output as DDA data S11.

Next, in the reduction ratio calculation circuit 304 of the texture engine circuit 12 shown in FIG.
(S, t, q) data S11 for eight pixels included in
using a ₁ ~S11a _8, the reduction ratio of the texture data is calculated, the reduction ratio lod is output to the texture data reading circuit 305.

Next, the texture data reading circuit 30
5, the texture data S is transferred from the texture buffer 20 (SRAM 17) based on the flow shown in FIG.
17 ₁ ~S17 ₈ is read, the texture data S17 ₁ ~S17 ₈ read is output to the texture α blending circuit 306.

At this time, under the control of the read controller 262 shown in FIG. 5 and FIG.
Via the wiring 280 _{1-280 1024} constituting the bank 220 16 pixels of the texture data including texture data S17 ₁ ~S17 ₈ is, to configure the SRAM17
₁ , 220 ₂ , 221 ₁ , 221 ₂ , 222 ₁ , 222
₂ , 223 ₁ , 223 ₂ , 224 ₁ , 224 ₂ , 225
₁ , 225 ₂ , 226 ₁ , 226 ₂ , 227 ₁ , 227
Read from ₂ .

Next, in the texture α blending circuit 306, (R, G, B ) data S11b ₁ ~S11b ₈
When, in the data _{S17 1 ~S17 8 (R, G} ,
B) and data are mixed in a mixing value indicated by tα included in the data _{S17 1 ~S17 8, (R,} G, B) data S306 ₁ ~S306 ₈ is generated. And DD
Α data S11d _{1 to} S11d included in A data
And _{8, (R, G, B} ) data S306 ₁ ~S306 ₈ is, (R, G, B, α) data S12a ₁ ~S12
a ₈ , that is, as the pixel data S12a, the memory I
/ F circuit 13.

Then, in the memory I / F circuit 13,
Pixel data S input from the texture engine circuit 12
The z data corresponding to the pixel data S12a is compared with the z data stored in the z buffer 22, and the image drawn by the input pixel data S12a is located before the image previously written to the display buffer 21. It is determined whether or not it is located on the (viewpoint side). If it is located on the near side, the z data stored in the z buffer 22 is updated with the z data corresponding to the image data S12a.

Next, in the memory I / F circuit 13, the image data S12a includes (R, G,
B) data and the (R, G, B) data already stored in the display buffer 21 are the pixel data S12
The mixed data is mixed with the mixed value indicated by the α data corresponding to “a”, and the mixed (R, G, B) data is written to the display buffer 21.

At this time, under the control of the memory controllers 240, 341, 242, and 243 shown in FIGS. 5 and 6, the wirings 270 ₁ to 270 ₂₅₆ and 271 ₁ to constituting the wiring groups 270, 271, 272, and 273, respectively.
271 ₂₅₆ , 272 _{1 to} 272 ₂₅₆ , 273 _{1 to} 273
Through ₂₅₆ , (R, G, B) data for 16 pixels is
The banks 210 ₁ , 210 ₂ , 211 ₁ , 211 ₂ , 212 ₁ , and 210 constituting the display buffer 21 shown in FIG.
212 ₂ , 213 ₁ , 213 ₂ , 214 ₁ , 214 ₂ ,
215 ₁ , 215 ₂ , 216 ₁ , 216 ₂ , 217 ₁ ,
Written to 217 ₂

As described above, according to the three-dimensional computer graphic system 1, the memory controllers 240, 241, 242, 243 and the read controller 262 shown in FIG.
By alternately arranging the wirings to the M17 as shown in FIG. 6, the distance between the wirings to which data is transferred at the same time can be increased as compared with the case where the wirings are not alternately arranged. As a result, the effect of crosstalk can be suppressed, and a high-quality image can be provided. Further, according to the three-dimensional computer graphic system 1, the failure detection can be easily performed because the tri-state bus is not used. Further, according to the three-dimensional computer graphic system 1, the influence of crosstalk can be suppressed without increasing the physical pitch between wirings, that is, without increasing the chip area.

Second Embodiment The three-dimensional computer graphic system of the present embodiment has the same structure as that of the first embodiment except for the wiring structure between the memory controllers 240 to 243 and the read controller 262 shown in FIG.
This is the same as the three-dimensional computer graphic system of the embodiment. FIG. 7 illustrates the memory controllers 240 to 243 and the read controller 26 according to the present embodiment.
2 is a diagram for explaining a wiring structure between a DRAM 2 and an SRAM 17; FIG. As shown in FIG. 7, also in the present embodiment, the wirings 270 _{1 to} 270 ₂₅₆ and 271 ₁ to 2
71 ₂₅₆ , 272 _{1 to} 272 ₂₅₆ , 273 _{1 to} 273
₂₅₆ and wirings 280 _{1 to} 280 ₁₀₂₄ are alternately arranged at a wiring pitch of 1.6 μm. However, in the present embodiment, a two-input one-output AN is provided at the output end of each wiring.
The output terminal of the D gate is connected. As the AND data, output data and R / W data are input.

Specifically, the wirings 270 _{1 to} 270 ₂₅₆ ,
271 _{1 to} 271 ₂₅₆ , 272 _{1 to} 272 ₂₅₆ , 273
The output side of _{1 to} 273 ₂₅₆ has an AND gate 500 ₁ to
500 ₁₀₂₄ output terminals are connected. Write data S270 _{1 to} S270 ₂₅₆ and S271 ₁ are respectively applied to one input terminals of the AND gates 500 _{1 to} 500 _{1024.
~S271 256, S272 1 ~S272 256,} S273
_{1 to} S273 ₂₅₆ are input. The other input terminal is connected to R gates via NOT gates 511 _{1 to} 511 _1024.
/ W data S550 is input. R / W data S55
0 becomes a low level at the time of writing and becomes a high level at the time of reading.

The output terminals of the AND gates 520 _{1 to} 520 ₁₀₂₄ are connected to the output side of the wirings 280 _{1 to} 280 ₁₀₂₄ . One input terminal of each of AND gates 520 _{1 to} 520 ₁₀₂₄ has read data S280
_{1 ~S280 1024} is input. Also, the R / W data S550 is input to the other input terminal.

Next, the operation of the wiring structure shown in FIG. 7 will be described. First, the write operation will be described. In the write operation, the R / W data S550 goes low, and the other input terminals of the AND gates 500 _{1 to} 500 ₁₀₂₄ are kept high. Therefore, the AND gate 5
From the output terminals of 00 _{1 to} 500 ₁₀₂₄ , wiring 27
0 _{1 to} 270 ₂₅₆ , 271 _{1 to} 271 ₂₅₆ , 272 ₁ to
Write data S to 272 ₂₅₆ , 273 _{1 to} 273 ₂₅₆
270 _{1 to} S270 ₂₅₆ , S271 _{1 to} S271 ₂₅₆ ,
S272 _{1 to} S272 ₂₅₆ , S273 _{1 to} S273 ₂₅₆
Is applied. At this time, AND gates 520 _{1 to} 52 ₁
The other input terminal of 0 ₁₀₂₄ is held at a low level by the R / W data S550, and its output terminal is at a low level. As a result, the wirings 280 _{1 to} 280 ₁₀₂₄ are held at a low level, and the wirings 270 _{1 to} 270 ₂₅₆ and 271
_{1 to} 271 ₂₅₆ , 272 _{1 to} 272 ₂₅₆ , 273 ₁ to 2
Wiring 280 ₁ holding a low level between 73 ₂₅₆
280 ₁₀₂₄ are located, and the influence of crosstalk is suppressed.

Next, the read operation will be described. In the write operation, the R / W data S550 goes high, the other input terminals of the AND gates 520 _{1 to} 520 ₁₀₂₄ are held at the high level by the R / W data S550, and the output terminals of the AND gates 520 _{1 to} 520 ₁₀₂₄ are connected to the wiring 280 ₁ to 280 ₁₀₂₄
To read data S280 ₁ ~S280 ₁₀₂₄ is applied. On the other hand, the other input terminals of the AND gates 500 _{1 to} 500 ₁₀₂₄ are held at low level by the R / W data S550. Therefore, the AND gates 500 ₁ to 50 ₁
0 ₁₀₂₄ output terminal becomes low level, and wiring 270 _1-
270 ₂₅₆ , 271 _{1 to} 271 ₂₅₆ , 272 _{1 to} 272
₂₅₆ , 273 _{1 to} 273 ₂₅₆ are held at the low level. Thereby, between the wirings 280 _{1 to} 280 ₁₀₂₄ ,
Wiring 270 ₁ to 270 ₂₅₆ , 27 holding low level
1 _{1-271 256,} 272 _{1-272 256,} 273 ₁ -
273 ₂₅₆ are located, and the influence of crosstalk is suppressed.

In the wiring structure shown in FIG. 7, an AND gate is provided at the output end of the wiring. However, since a buffer is provided at the output end of the wiring, the buffer is connected to the AND gate. This means that there is almost no increase in the number of gates.

The present invention is not limited to the above embodiment. For example, in the above-described embodiment, the memory controllers 240, 241, 242, 243 and the read controller 262 shown in FIG.
The case where the wiring structure shown in FIGS. 6 and 7 is applied to the AM 17 has been exemplified.
And the texture engine circuit 12 shown in FIG. 1.

In the above-described embodiment, the number of pixels to be simultaneously processed is eight, but this number is arbitrary, and may be four, for example. However, it is desirable that the number of pixels to be simultaneously processed is a power of two.

Further, in the three-dimensional computer graphic system 1 shown in FIG. 1 described above, the configuration using the SRAM 17 is exemplified, but a configuration without the SRAM 17 may be adopted. The texture buffer 20 and the texture CLUT buffer 23 shown in FIG.
May be provided outside.

Further, in the three-dimensional computer graphic system 1 shown in FIG. 1, the case where the geometry processing for generating polygon rendering data is performed by the main processor 4 is exemplified, but the configuration may be such that the rendering circuit 5 performs.

[0068]

As described above, according to the data transfer device and the graphic processing device of the present invention, the influence of crosstalk can be suppressed without increasing the size of the device. Further, according to the data transfer device and the graphic operation device of the present invention, since no transstate is used, failure detection does not involve difficulty.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of a three-dimensional computer graphic system according to an embodiment of the present invention.

FIG. 2 is an internal configuration diagram of a texture engine circuit shown in FIG. 1;

FIG. 3 is a diagram for explaining texture data at a plurality of reduction rates stored in the texture buffer shown in FIG. 1 and subjected to MIPMAP filtering processing;

FIG. 4 is a flowchart of a process in a texture data reading circuit shown in FIG. 2;

5 is a configuration diagram of a DRAM, an SRAM, and a block of a memory I / F circuit having a function of accessing the DRAM and the SRAM shown in FIG. 1;

FIG. 6 is a diagram for explaining a wiring structure between a read controller and a memory controller shown in FIG. 5 and a DRAM and an SRAM;

FIG. 7 is a diagram for explaining another wiring structure between the read controller and the memory controller shown in FIG. 5 and the DRAM and the SRAM;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Three-dimensional computer graphic system, 2 ... Main memory, 3 ... I / O interface circuit, 4 ... Main processor, 5 ... Rendering circuit, 10 ... DDA setup circuit, 11 ... Triangle DDA circuit, 1
2 Texture engine circuit, 13 Memory I / F circuit, 14 CRT controller circuit, 15 RAMDA
C circuit, 16 DRAM, 17 SRAM, 20 texture buffer, 21 display buffer, 22
Z buffer, 23 ... texture CLUT buffer, 30
4, a reduction ratio calculation circuit, 305, a texture data readout circuit, 306, a texture α blend circuit, 200,
201, 202, 203 ... memory module, 210,
211, 212, 213, 214, 215, 216, 2
17: memory, 240, 241, 242, 243: memory controller, 250, 251, 252, 253: address converter, 260: distributor, 26
2, read controller, 270, 271, 272,
273, 280 ... wiring group

Claims (10)

[Claims] 1. A data transfer device for performing data transfer from a first circuit block to a second circuit block and data transfer from the second circuit block to the first circuit block. A plurality of first wires for transferring data from the circuit block to the second circuit block and a plurality of second wires for transferring data from the second block to the first block are alternately arranged. Transferring data from the first circuit block to the second circuit block; and transferring data from the second circuit block to the first circuit block.
A data transfer device for performing data transfer to a circuit block at a different timing. 2. The data transfer device according to claim 1, wherein one of said first wiring and said second wiring is held at a predetermined level while data is being transferred. 3. When the transfer direction designating data for designating the direction of data transfer is at a first level, the input data is output to the first wiring, and the transfer direction designating data is at a second level. A first logic circuit for holding the first wiring at a predetermined level; and outputting the input data to the second wiring when the transfer direction instruction data is at a second level. 3. The data transfer device according to claim 2, further comprising a second logic circuit that holds the second wiring at a predetermined level when the transfer direction instruction data is at the first level. 4. The data transfer device according to claim 1, wherein said first circuit block is a control circuit for reading and writing data, and said second circuit block is a storage circuit for storing data. . 5. A three-dimensional model is represented by a combination of a plurality of unit figures, and texture data is represented by said unit figures based on homogeneous coordinates (s, t) and homogeneous terms q included in image data for each pixel. In a graphic operation device for generating drawing data in association with each other, a storage means for storing the texture data and the drawing data; and for each pixel, storing the texture data corresponding to the pixel via a plurality of first wirings. Means for generating drawing data by reading from the means, and writing the generated drawing data to the storage means via a plurality of second wirings, wherein the first wiring and the second wiring A graphic operation device in which wiring and wiring are arranged alternately. 6. The graphic operation device according to claim 5, wherein one of said first wiring and said second wiring is held at a predetermined level while data is being transferred. 7. When the transfer direction designating data for designating the direction of data transfer is at a first level, the input data is output to the first wiring, and when the transfer direction designating data is at a second level. A first logic circuit for holding the first wiring at a predetermined level; and outputting the input data to the second wiring when the transfer direction instruction data is at a second level. 7. The graphic operation device according to claim 6, further comprising: a second logic circuit that holds the second wiring at a predetermined level when the direction indication data is at the first level. 8. In order to represent a predetermined shape to be displayed on the display by a combination of unit figures, operations on a plurality of pixels are simultaneously performed, and a calculation is performed on pixels located inside the unit figure to be processed. In a graphic operation device that performs a process using an operation result as an effective result, a three-dimensional coordinate (x, y,
a polygon rendering data generating device for generating polygon rendering data including z), R (red), G (green), B (blue) data, homogeneous coordinates (s, t) and homogeneous terms q; And a bus connecting the polygon rendering data generating device and the rendering device. The rendering device has a storage unit for storing texture data and drawing data. Reading the texture data corresponding to the pixel from the storage unit via a plurality of first wirings to generate drawing data, and writing the generated drawing data to the storage unit via a plurality of second wirings Drawing data generating means, wherein the first wirings and the second wirings are alternately arranged. And Graphic computing device. 9. The graphic operation device according to claim 8, wherein one of said first wiring and said second wiring is held at a predetermined level while data is being transferred. 10. When the transfer direction designating data for designating the direction of data transfer is at the first level, the input data is output to the first wiring, and the transfer direction designating data is set to the second level.
A first logic circuit that holds the first wiring at a predetermined level when the transfer direction instruction data is at the second level, and outputs input data to the second wiring when the transfer direction instruction data is at the second level 10. The graphic operation device according to claim 9, further comprising: a second logic circuit that holds the second wiring at a predetermined level when the transfer direction instruction data is at a first level.