JPH0621179A - Erasing method for eliminated area of ic chip - Google Patents
Erasing method for eliminated area of ic chipInfo
- Publication number
- JPH0621179A JPH0621179A JP22883691A JP22883691A JPH0621179A JP H0621179 A JPH0621179 A JP H0621179A JP 22883691 A JP22883691 A JP 22883691A JP 22883691 A JP22883691 A JP 22883691A JP H0621179 A JPH0621179 A JP H0621179A
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- Japan
- Prior art keywords
- chip
- stored
- chips
- wafer
- removal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、ウエハの異物検査装
置において、ＩＣチップの除去エリアに対するマップ表
示を消去する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for erasing a map display for an IC chip removal area in a wafer foreign matter inspection apparatus.
【０００２】[0002]
【従来の技術】半導体ＩＣの製造においてはシリコンな
どの素材のウエハに対して、同一のパターンを有する多
数のＩＣチップ（以下単にチップという）が形成され、
この段階で異物検査が行われる。異物検査はレーザビー
ムをウエハ面に投射し、その反射または散乱光を受光し
てなされるが、異物とともにパターンからも散乱光が散
乱されるので、これらを区別して異物のみを検出するこ
とが必要、かつ重要である。これに適応する方法には各
種のものが開発されているが、その一つとして互いに隣
接した２個のチップを相互に比較する方法がある。2. Description of the Related Art In the manufacture of semiconductor ICs, a large number of IC chips (hereinafter simply referred to as chips) having the same pattern are formed on a wafer made of a material such as silicon.
A foreign matter inspection is performed at this stage. The foreign matter inspection is performed by projecting a laser beam on the wafer surface and receiving the reflected or scattered light, but since scattered light is scattered from the pattern along with the foreign matter, it is necessary to distinguish them and detect only the foreign matter. , And is important. Various methods have been developed to adapt to this, and one of them is a method of comparing two chips adjacent to each other.
【０００３】図２(a) 〜(c) は上記の異物検査装置の概
略構成と隣接チップの比較による異物検出方法を示す。
(a) に示すようにウエハ１の表面には、同一パターンを
有する多数のチップ11がマトリックス状に形成されてい
る。(b) において、ウエハは移動ステージ２に載置さ
れ、これに対して検査光学系３の光源３a よりレーザビ
ームＬx をウエハの表面に照射する。ウエハはＸ方向に
往復移動されてレーザビームが各チップ列を順次に走査
し、その散乱光が対物レンズ３b を経てＣＣＤセンサ３
c （他の光センサでも可）に入力する。ここで、チップ
列中の隣接した任意の２個のチップを(c) の(イ) のよう
に11a,11b とし、チップ11b には図示の位置に異物ｐ1,
ｐ2 が付着しているとする。まずチップ11a の散乱光を
受光し、ＣＣＤセンサの各画素の出力信号（以下単に画
素信号という）は逐次に画素信号処理部４に入力し、Ａ
／Ｄ変換器４a によりデジタル化され、メモリ（ＭＥ
Ｍ）４b に記憶される。ついでチップ11b の散乱光より
同様にえられる各画素信号が差分回路４c に入力し、Ｍ
ＥＭに記憶されているチップ11a の各画素信号との差分
データが出力される。(c) の(ロ) は両チップのパターン
ＰT および異物ｐ1,ｐ2に対する各画素信号ｇn （ｎは
画素番号）よりなる画素データＳa,Ｓb を示し、両チッ
プのパターンの無い基板面Ｋは値が低く、パターンＰT
は反射率が大きいので値が大きい。また、異物ｐ1,ｐ2
の画素信号ｇはデータＳb の上方に突出している。前記
したように両パターンＰT は同一であるので、両画素デ
ータのパターン部分はほぼ同一となり、差分データ（Ｓ
b −Ｓa ）ではこれがほぼ消去されて、(ハ) に例示した
残留パターンＲと異物ｐ1,ｐ2 よりなる差分データがえ
られる。差分データは異物検出部４d において検出閾値
Ｖthと比較されて異物ｐ1,ｐ2 のみが検出される。な
お、チップ11a にある異物は差分データ（Ｓb −Ｓa)で
は負極となるので、絶対値をとることにより正極として
上記と同様に検出される。以上により検出された異物デ
ータはコンピュータ（ＣＰＵ）４e により編集されて表
示器４f にマップ表示される。2 (a) to 2 (c) show a schematic structure of the above-described foreign substance inspection apparatus and a foreign substance detecting method by comparing adjacent chips.
As shown in (a), a large number of chips 11 having the same pattern are formed in a matrix on the surface of the wafer 1. In (b), the wafer is placed on the moving stage 2, and the surface of the wafer is irradiated with the laser beam L x from the light source 3 a of the inspection optical system 3. The wafer is reciprocally moved in the X direction, the laser beam sequentially scans each chip row, and the scattered light passes through the objective lens 3b and the CCD sensor 3
Input to c (other optical sensors are acceptable). Here, arbitrary two adjacent chips in the chip row are referred to as 11a and 11b as shown in (c) (a), and the foreign matter p 1 and
It is assumed that p 2 is attached. First, the scattered light from the chip 11a is received, and the output signals (hereinafter simply referred to as pixel signals) of each pixel of the CCD sensor are sequentially input to the pixel signal processing unit 4, where A
It is digitized by the / D converter 4a, and the memory (ME
M) stored in 4b. Then, each pixel signal similarly obtained from the scattered light of the chip 11b is input to the difference circuit 4c, and M
Difference data from each pixel signal of the chip 11a stored in the EM is output. (b) in (c) shows the pixel data S a and S b consisting of the pattern P T of both chips and the pixel signals g n (n is a pixel number) for the foreign substances p 1 and p 2 , respectively. The value of the substrate surface K which does not exist is low and the pattern P T
Has a large value because it has a high reflectance. In addition, foreign matter p 1 , p 2
Pixel signal g of the above signal is projected above the data S b . As described above, since both patterns P T are the same, the pattern portions of both pixel data are almost the same, and the difference data (S
In b- S a ), this is almost erased, and difference data composed of the residual pattern R and the foreign matter p 1 and p 2 illustrated in (c) is obtained. The difference data is compared with the detection threshold value V th in the foreign matter detector 4d to detect only the foreign matter p 1 and p 2 . Incidentally, foreign matter in the tip 11a so becomes negative in the difference data (S b -S a), it is detected in the same manner as described above as a positive electrode by taking the absolute value. The foreign matter data detected as described above is edited by the computer (CPU) 4e and displayed on the display 4f as a map.
【０００４】[0004]
【発明が解決しようとする課題】さて、各チップ11のパ
ターンＰT は、形成プロセスの段階が進行するに伴って
厚さが厚くなり、また単なる配線パターンのみでなく、
コンデンサなどの回路部品が付加して形成される。この
ような回路部品が形成されたパターン部分はマット部と
よばれているが、この部分は反射率が大きくて散乱光が
異常に強い場合があり、これに妨害されて異物の検出が
困難である。従ってそのマップ表示は無用であるばかり
でなく、他の部分のマップ表示の観察に支障する。そこ
で、反射率の強いマット部を除去エリアとしてマップ表
示を消去することが望ましい。その方法は、除去エリア
に対して値の大きい除去閾値を設定して除去し、他の部
分に対しては別途に定められた適切な検出閾値を設定し
て異物の検出を行うことが有効である。しかし、除去エ
リアがチップのどの位置にあるのか、また除去閾値はい
くらがよいのかについては、事前には的確に判明してい
ない。この発明は以上に鑑みてなされたもので、予めの
テストにより除去エリアを特定し、これを除去できる大
きさの除去閾値を作って各チップを検査し、除去エリア
のマップ表示を消去する方法を提供することを目的とす
る。The pattern P T of each chip 11 becomes thicker as the steps of the formation process progress, and is not limited to a simple wiring pattern.
It is formed by adding circuit components such as a capacitor. The pattern part where such circuit parts are formed is called the mat part, but this part has a large reflectance and the scattered light may be abnormally strong, which makes it difficult to detect foreign matter. is there. Therefore, the map display is not only useless, but also obstructs the observation of the map display of other parts. Therefore, it is desirable to erase the map display by using the mat portion having a high reflectance as a removal area. As a method, it is effective to set a large removal threshold value for the removal area to remove the foreign matter, and to set an appropriate detection threshold value separately set for other areas to detect the foreign matter. is there. However, it is not known in advance exactly where the removal area is on the chip and what the removal threshold is. The present invention has been made in view of the above, and a method of identifying a removal area by a preliminary test, making a removal threshold of a size that can remove the removal area, inspecting each chip, and erasing the map display of the removal area is provided. The purpose is to provide.
【０００５】[0005]
【課題を解決するための手段】この発明は上記の目的を
達成する除去エリアの消去方法であって、上記のウエハ
異物検査装置において、ウエハの任意のチップ列をテス
トチップ列とし、これに対してレーザビームを走査して
各隣接チップに対する各差分データを逐次に求める。各
チップの同一位置に対する各差分データの画素信号の絶
対値を、逐次に加算してマップメモリの各画素メモリに
それぞれ記憶する。記憶された中の一定値より大きい加
算データを、反射率が異常に大きい除去エリアに対する
除去閾値とし、この除去閾値とそのマップメモリのアド
レスをＲＡＭに記憶する。各チップの検査においては、
記憶されたアドレスに対応する画素信号に対してこの除
去閾値を設定して除去し、除去エリアのマップ表示が消
去される。SUMMARY OF THE INVENTION The present invention is a method of erasing a removed area for achieving the above-mentioned object, wherein in the above-mentioned wafer foreign matter inspection apparatus, an arbitrary chip row of a wafer is used as a test chip row, Then, the laser beam is scanned to sequentially obtain each difference data for each adjacent chip. The absolute value of the pixel signal of each difference data for the same position of each chip is sequentially added and stored in each pixel memory of the map memory. The added data larger than a fixed value among the stored values is set as a removal threshold value for the removal area having an abnormally large reflectance, and the removal threshold value and its map memory address are stored in the RAM. In the inspection of each chip,
This removal threshold value is set and removed for the pixel signal corresponding to the stored address, and the map display of the removal area is erased.
【０００６】[0006]
【作用】上記の方法においては、テストチップ列に対す
る各差分データの、各チップの同一位置の画素信号の絶
対値が逐次に加算されてマップメモリの各画素メモリに
記憶される。一定値より大きい加算データが除去エリア
に対する除去閾値とされ、これがそのアドレスとともに
ＲＡＭに記憶される。各チップの検査においては、記憶
されたアドレスに対応する画素信号に対してこの除去閾
値を設定して除去し、そのマップ表示が消去されて他の
エリアの異物の観察が容易となるものである。In the above method, the absolute values of the pixel signals at the same position of each chip of each differential data for the test chip row are sequentially added and stored in each pixel memory of the map memory. The addition data larger than a certain value is used as the removal threshold for the removal area, and this is stored in the RAM together with its address. In the inspection of each chip, this removal threshold value is set to the pixel signal corresponding to the stored address to remove the pixel signal, and the map display is erased to facilitate observation of foreign matter in other areas. .
【０００７】[0007]
【実施例】図１はこの発明の一実施例を示し、(a) は概
略のブロック構成図、(b) はマップメモリの図、(c) は
３次元に表現した加算データの分布図である。図１の
(a) において、前記した図２(b) の異物検査装置に対し
て、除去閾値設定部５とスイッチ６とを付加する。除去
閾値設定部５は、加算回路５a,マップメモリ５b,ＲＡＭ
５c,および閾値選択回路５d よりなる。なお、図２(b)
と同一構成要素は同一番号で示す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention. (A) is a schematic block diagram, (b) is a map memory diagram, and (c) is a distribution diagram of addition data expressed in three dimensions. is there. Figure 1
In (a), a removal threshold setting unit 5 and a switch 6 are added to the foreign matter inspection apparatus of FIG. 2 (b) described above. The removal threshold setting unit 5 includes an adder circuit 5a, a map memory 5b, and a RAM.
5c and a threshold value selection circuit 5d. Note that Fig. 2 (b)
The same components as are indicated by the same numbers.
【０００８】まず、除去エリアとこれに対する除去閾値
ＶD を求める。ウエハに形成されたＸ方向の任意のチッ
プ列 (Ａ), (Ｂ), (Ｃ),……（Ｎ）をテストチップ列と
し、これに対してレーザビームＬX を往復走査する。走
査による各チップの画素データＳa,Ｓb,Ｓc ……Ｓn
は、逐次に差分回路４c に入力して各隣接チップに対す
る差分データ（Ｓb −Ｓa)，（Ｓc −Ｓb)［以下便宜
上、これらをＱab，Ｑbcで示す］などが出力され、絶対
値回路４g によりそれぞれの絶対値｜Ｑab｜，｜Ｑbc｜
などがえられる。各絶対値はスイッチ６を経て加算回路
５a に逐次に入力し、それぞれに対する前回値と加算さ
れて加算データΣ｜Ｑ｜がえられ、マップメモリ５b に
記憶される。マップメモリは(b) に示すように、チップ
の各画素信号に対応したマトリックス状のメモリ素子Ｍ
（ｉ，ｊ）よりなり、（ｉ，ｊ）はアドレス番号を示す
ものとする。一方、ウエハを載置した移動ステージ２が
ＣＰＵ４e に制御されて移動すると、その位置がＸＹエ
ンコーダ２a により検出され、その位置信号がマップメ
モリ５b のアドレスを指定し、上記の加算データが指定
されたアドレスに記憶される。(c) はマップメモリに記
憶された加算データを３次元で表示した例を示す。各メ
モリＭ（ｉ，ｊ）のデータはいわばランダムに起伏して
いるが、その中には山状に高い部分があり、その高さは
各画素信号の和であるから非常に高い。この高さをＣＰ
Ｕ４e によりチェックし、これが一定値以上を示すエリ
アを除去エリアと特定し、その高さを除去閾値ＶD とす
る。除去エリアの位置はメモリ素子のアドレスより判明
する。以上によりえられた除去エリアのアドレスと除去
閾値ＶD は、テストの終了時点でＲＡＭ５c に転送され
て記憶される。First, the removal area and the removal threshold V D for the removal area are obtained. An arbitrary chip array (A), (B), (C), ... (N) in the X direction formed on the wafer is used as a test chip array, and a laser beam L X is reciprocally scanned with respect to this. Pixel data S a , S b , S c ... S n of each chip by scanning
The difference data for each adjacent chips are sequentially input to the difference circuit 4c (S b -S a), (S c -S b) [ hereinafter for convenience, these Q ab, indicated by Q bc] etc. are output , Absolute value circuit 4g uses respective absolute values | Q ab |, | Q bc |
And so on. Each absolute value is sequentially input to the adder circuit 5a via the switch 6, added with the previous value for each, and added data Σ | Q | is obtained and stored in the map memory 5b. As shown in (b), the map memory is a matrix-shaped memory element M corresponding to each pixel signal of the chip.
It is composed of (i, j), and (i, j) indicates an address number. On the other hand, when the moving stage 2 on which the wafer is placed is moved under the control of the CPU 4e, its position is detected by the XY encoder 2a, and the position signal specifies the address of the map memory 5b and the above-mentioned addition data is specified. Stored in the address. (c) shows an example in which the addition data stored in the map memory is displayed three-dimensionally. The data in each memory M (i, j) undulates in a random manner, but there is a mountain-like high portion in it, and the height is very high because it is the sum of each pixel signal. This height is CP
It is checked by U4e, the area showing a certain value or more is specified as the removal area, and its height is set as the removal threshold V D. The position of the removed area is known from the address of the memory element. The address of the removal area and the removal threshold value V D obtained as described above are transferred to the RAM 5c and stored at the end of the test.
【０００９】次に、各チップの検査においては、移動ス
テージによりウエハが移動し、その全面がレーザビーム
により往復走査され、各隣接チップに対する差分データ
Ｑが差分回路４c より逐次に出力され、差分データの各
画素信号は絶対値回路４g により絶対値化され、スイッ
チ６の切り替えにより異物検出部４d に入力する。これ
に対して、ＲＡＭに記憶されたアドレスと、ＸＹエンコ
ーダの位置信号の示すアドレスとが一致するとＲＡＭよ
り除去閾値ＶD が読出され、閾値選択回路５dによりこ
れが選択されて異物検出部に与えられ、上記により入力
した除去エリアの画素信号が除去される。なお、除去エ
リア以外の他のエリアに対する検出閾値Ｖthは、予め閾
値選択回路などに設定され、他のエリアの画素信号に対
して異物検出部に与えられて異物が検出される。以上の
除去閾値設定部５の構成は一例であって、細部がこれと
異なるものであっても、これと同様な作用をなし同一の
目的の構成はこの発明に含まれるものである。Next, in the inspection of each chip, the wafer is moved by the moving stage, the entire surface thereof is reciprocally scanned by the laser beam, and the difference data Q for each adjacent chip is sequentially output from the difference circuit 4c. Each pixel signal is converted into an absolute value by the absolute value circuit 4g, and is input to the foreign matter detection unit 4d by switching the switch 6. On the other hand, when the address stored in the RAM and the address indicated by the position signal of the XY encoder match, the removal threshold value V D is read from the RAM, and the removal threshold value Vd is selected by the threshold selection circuit 5d and given to the foreign matter detection unit. The pixel signals in the removal area input as described above are removed. The detection threshold V th for areas other than the removal area is set in advance in a threshold selection circuit or the like, and is applied to the foreign matter detection unit with respect to pixel signals in other areas to detect foreign matter. The above-described configuration of the removal threshold setting unit 5 is an example, and even if the details are different from this, configurations having the same operation and having the same purpose are included in the present invention.
【００１０】[0010]
【発明の効果】以上の説明のとおり、この発明による除
去エリアの消去方法においては、テストチップ列のテス
トによりえられる加算データが、一定値より大きいと
き、これを除去エリアと特定し、その値を除去閾値とし
て除去エリアの画素信号を除去してそのマップ表示を消
去するもので、除去エリアの位置が的確に特定され、ま
た適正な除去閾値により無益有害なマップ表示が消去さ
れるもので、他のエリアの異物の観察が容易となり、隣
接チップの比較方法による異物検査に寄与するところに
は大きいものがある。As described above, in the removal area erasing method according to the present invention, when the addition data obtained by the test of the test chip row is larger than a certain value, this is specified as the removal area and the value is determined. Is used as a removal threshold to remove the pixel signals in the removal area to erase the map display, and the position of the removal area is accurately specified, and the useless harmful map display is erased by an appropriate removal threshold. Observation of foreign matter in other areas becomes easy, and there is a great contribution to foreign matter inspection by a method of comparing adjacent chips.
【図１】 この発明の一実施例を示し、(a) は概略のブ
ロック構成図、(b)はマップメモリの図、(c) は３次元
に表現した加算データの分布図である。FIG. 1 shows an embodiment of the present invention, (a) is a schematic block diagram, (b) is a map memory diagram, and (c) is a distribution diagram of addition data expressed in three dimensions.
【図２】 (a) はウエハに形成されるＩＣチップを示す
図、(b) は隣接チップの比較方法による異物検査装置の
概略の構成図、(c) は比較される隣接チップとそれぞれ
の画素データ、および差分データを示す図である。2A is a diagram showing an IC chip formed on a wafer, FIG. 2B is a schematic configuration diagram of a foreign substance inspection apparatus by a method of comparing adjacent chips, and FIG. It is a figure which shows pixel data and difference data.
１…ウエハ、11…ＩＣチップ、チップ、11a,11b …隣接
チップ、２…移動ステージ、２a …ＸＹエンコーダ、３
…検査光学系、３a …光源、３b …対物レンズ、３c …
ＣＣＤセンサ、４…画素信号処理部、４a …Ａ／Ｄ変換
器、４b …コンピュータ（ＣＰＵ）、４f …表示器、４
g …絶対値回路、５…除去閾値設定部、５a …加算回
路、５b …マップメモリ、５c …ＲＡＭ、５d …閾値選
択回路、６…スイッチ、Ｓa,Ｓb,Ｓc …画素データ、Ｑ
…差分データ、Σ｜Ｑ｜…加算データ、Ｍ（ｉ，ｊ）…
マップメモリのメモリ素子、（ｉ，ｊ）…そのアドレ
ス、Ｖth…異物に対する検出閾値、ＶD …除去エリアに
対する除去閾値。1 ... Wafer, 11 ... IC chip, chip, 11a, 11b ... Adjacent chip, 2 ... Moving stage, 2a ... XY encoder, 3
... Inspection optical system, 3a ... Light source, 3b ... Objective lens, 3c ...
CCD sensor, 4 ... Pixel signal processing unit, 4a ... A / D converter, 4b ... Computer (CPU), 4f ... Display device, 4
g ... absolute value circuit, 5 ... removal threshold setting unit, 5a ... adder circuit, 5b ... map memory, 5c ... RAM, 5d ... threshold selection circuit, 6 ... switch, S a, S b, S c ... pixel data, Q
... difference data, Σ | Q | ... addition data, M (i, j) ...
Memory device of map memory, (i, j) ... that address detection threshold for V th ... foreign matter, V D ... removal threshold for removal area.
Claims (1)
を有する複数のＩＣチップを検査対象とし、該ウエハに
対してレーザビームを走査し、互いに隣接した２個の前
記ＩＣチップの反射光を光センサにより受光し、該光セ
ンサの出力した該隣接チップの対応する画素信号の差分
データを、検出閾値に比較して異物を検出してマップ表
示するウエハ異物検査装置において、前記ウエハの任意
のチップ列をテストチップ列とし、該テストチップ列に
対して前記レーザビームを走査して各隣接チップに対す
る各差分データを逐次に求め、前記ＩＣチップの同一位
置に対する該各差分データの画素信号の絶対値を、逐次
に加算してマップメモリの各画素メモリにそれぞれ記憶
し、該記憶された中の一定値より大きい加算データを、
反射率が異常に大きい除去エリアに対する除去閾値と
し、該除去閾値とそのマップメモリのアドレスをＲＡＭ
に記憶し、前記各ＩＣチップの検査において、該記憶さ
れたアドレスに対応する画素信号に対して該除去閾値を
設定して除去し、前記除去エリアのマップ表示を消去す
ることを特徴とする、ＩＣチップの除去エリアの消去方
法。1. A plurality of IC chips having the same pattern formed on the surface of a wafer are inspected, a wafer is scanned with a laser beam, and light reflected by two IC chips adjacent to each other is emitted. A wafer foreign matter inspection apparatus for detecting foreign matter by comparing difference data of corresponding pixel signals of the adjacent chips output by the sensor with a detection threshold value, and displaying a map on the wafer. An array is a test chip array, the test chip array is scanned with the laser beam to sequentially obtain each difference data for each adjacent chip, and the absolute value of the pixel signal of each difference data for the same position of the IC chip. Are sequentially added and stored in each pixel memory of the map memory, and the addition data larger than a fixed value in the stored
The removal threshold is set for the removal area having an abnormally large reflectance, and the removal threshold and the address of the map memory are stored in the RAM.
In the inspection of each of the IC chips, the removal threshold is set and removed for the pixel signal corresponding to the stored address, and the map display of the removal area is erased. Method of erasing IC chip removal area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3228836A JP2996264B2 (en) | 1991-08-14 | 1991-08-14 | Method for erasing IC chip removal area |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3228836A JP2996264B2 (en) | 1991-08-14 | 1991-08-14 | Method for erasing IC chip removal area |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0621179A true JPH0621179A (en) | 1994-01-28 |
| JP2996264B2 JP2996264B2 (en) | 1999-12-27 |
Family
ID=16882624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3228836A Expired - Fee Related JP2996264B2 (en) | 1991-08-14 | 1991-08-14 | Method for erasing IC chip removal area |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2996264B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08156870A (en) * | 1994-12-07 | 1996-06-18 | Tomizou Yoshikawa | Bicycle with electric motor |
| JP2012251935A (en) * | 2011-06-06 | 2012-12-20 | Fujitsu Semiconductor Ltd | Inspection device and inspection method |
| US11247620B2 (en) * | 2020-01-17 | 2022-02-15 | Yazaki Corporation | Wire harness including wire bundle having relay line with connector, and protector covering wire bundle and holding connector |
-
1991
- 1991-08-14 JP JP3228836A patent/JP2996264B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08156870A (en) * | 1994-12-07 | 1996-06-18 | Tomizou Yoshikawa | Bicycle with electric motor |
| JP2012251935A (en) * | 2011-06-06 | 2012-12-20 | Fujitsu Semiconductor Ltd | Inspection device and inspection method |
| US11247620B2 (en) * | 2020-01-17 | 2022-02-15 | Yazaki Corporation | Wire harness including wire bundle having relay line with connector, and protector covering wire bundle and holding connector |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2996264B2 (en) | 1999-12-27 |
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