JP2012251935A - Inspection device and inspection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inspection method for extracting a target defect among defects acquired from an image.SOLUTION: The inspection method has processing which acquires image data of a plurality of inspection object regions, compares luminance of the same position of regions to each other of forming the same structure among the plurality of inspection object regions to calculate luminance difference distribution of the luminance by use of the luminance difference, sets threshold distribution such that the threshold of a priority detection region desired to be preferentially inspected becomes lower than thresholds of the other regions in each of the plurality of inspection object regions, and determines a position becoming more than the threshold distribution among the luminance difference distribution as an object defect occurrence position.

Description

  The present invention relates to an inspection apparatus and an inspection method.

  In the defect inspection, for example, foreign matters adhering to the semiconductor wafer or defects in the semiconductor pattern in the manufacturing process of the semiconductor device are in-line inspected. In such an inspection process, a coordinate such as a foreign object or a defect is acquired using a defect inspection apparatus. And after manufacturing a semiconductor circuit on a semiconductor wafer, an electrical characteristic is tested and operation | movement of a semiconductor circuit is confirmed. A semiconductor circuit in which an abnormality is found is observed in detail using an optical microscope or a scanning electron microscope. And check the correlation of foreign matter and defects acquired by the defect inspection device, identify the process and manufacturing equipment that caused the abnormality of the semiconductor circuit, and the judgment materials for reviewing the production conditions and carrying out equipment maintenance To do.

  Here, as a method for determining the presence / absence of a defect, it is known to capture the appearance of the surface of a semiconductor wafer and use a luminance signal obtained based on the image signal. This luminance signal is represented by 256 gradations, for example, with the luminance value (gradation value) of the darkest dark part being “0” and the luminance value of the brightest bright part being “255”. In this defect determination method, the luminance signal of the portion to be inspected is compared with the luminance signal of the portion to be compared, and if the difference is equal to or greater than a predetermined threshold value for defect detection, the defect is determined. Is determined.

  For example, one uniform threshold value is set for the entire wafer, image data on the wafer surface is acquired, and the difference between the gradation value when there is no defect and the data when there is no defect is calculated. If the difference between the gradation values exceeds the threshold value, it is determined that there is a defect and the number is counted.

  In order to improve the efficiency of defect inspection, a method is known in which image data of a semiconductor wafer is divided into image blocks of a predetermined size for inspection. In this case, if the luminance difference in the image block is greater than or equal to a predetermined threshold, it is determined that the circuit pattern is densely arranged in the image block. Such a defect in the region is classified as having a high possibility of affecting the result of the electrical test because the circuit pattern is dense. On the other hand, if the luminance difference in the image block is less than a predetermined threshold value, it is determined that the circuit block has a sparse circuit pattern.

  Such a sparse region defect is classified as having a low possibility of affecting the result of the electrical test because the circuit pattern is sparse. In contrast, defects in image block areas where circuit patterns are densely arranged are considered to be highly likely to affect the results of electrical tests, so these areas are preferentially inspected with an optical microscope. To do. Thereby, the efficiency of the analysis of the cause of the abnormality of the semiconductor circuit can be improved.

JP 2004-138563 A JP 2003-329611 A JP 2009-283396 Gazette

The sensitivity of an image detection apparatus such as a scanning electron microscope (SEM) used for detecting the appearance of a semiconductor wafer is gradually improved. However, as the sensitivity is improved, many unnecessary defects are detected. An unnecessary defect is a defect excluding a target defect to be evaluated, and is a defect that is desired to be excluded from the evaluation target. As an unnecessary defect, there exists a defect which has arisen in the layer below the layer used as the object of evaluation, for example.

  Therefore, it is necessary to remove the target defect from the defect detected by the detection device and extract the target defect, but when detecting defects in different layers at the same time, it is not possible to extract the target defect from the detected defect. Not done. For this reason, it is difficult to select whether the detected defect is a target defect or an unnecessary defect.

  An object of the present invention is to provide an inspection apparatus and an inspection method for extracting a target defect from a defect acquired from an image.

According to one aspect of the embodiment, image data of a plurality of inspection target regions is acquired, and the luminance difference is compared by comparing the luminance at the same position between regions forming the same structure among the plurality of inspection target regions. Determining a luminance difference distribution from each of the plurality of inspection target areas, and setting a threshold distribution so that a threshold of a priority detection area to be preferentially inspected is lower than a threshold of other areas, A defect inspection method is provided in which a position where the threshold distribution is equal to or higher than the threshold distribution is determined as a target defect occurrence position.
The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It is understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not intended to limit the invention.

  According to the embodiment, image information of a plurality of inspection target areas displayed in a dark field image is created as a gray scale luminance distribution, and the luminance distributions of the plurality of inspection target areas having the same structure are compared with each other to determine the brightness of each other. Find the difference distribution. Further, as a threshold value used for defect determination, a threshold value of an area where defects are desired to be detected with priority is set lower than that of other areas. Then, in the luminance difference distribution, the luminance position that is equal to or higher than the threshold value is determined as the target defect. This facilitates extraction of the target defect.

FIG. 1 is a configuration diagram illustrating an example of a semiconductor device inspection apparatus according to an embodiment. FIG. 2 is a plan view illustrating a semiconductor wafer on which a semiconductor device to be inspected by the semiconductor device inspection apparatus according to the embodiment is formed. FIG. 3 is an example of a flowchart of a defect inspection method for a semiconductor device according to the embodiment. 4A and 4B are cross-sectional views illustrating a process for forming a semiconductor device to be inspected by the semiconductor device inspection method according to the embodiment. 4C to 4E are cross-sectional views illustrating a process of forming a semiconductor device to be inspected by the semiconductor device inspection method according to the embodiment. 4F to 4H are cross-sectional views illustrating a process for forming a semiconductor device to be inspected by the semiconductor device inspection method according to the embodiment. 5A and 5B are diagrams illustrating a first example of a luminance distribution acquired in the method for inspecting a semiconductor device according to the embodiment. FIG. 6 is a diagram illustrating a first example of defect distribution and threshold values obtained based on FIGS. 5A and 5B. 7A and 7B are diagrams illustrating a second example of the luminance distribution acquired in the semiconductor device inspection method according to the embodiment. FIG. 8 is a diagram showing an example of the defect distribution and threshold values obtained based on FIGS. 7A and 7B. 9A and 9B are diagrams illustrating a third example of the luminance distribution acquired in the semiconductor device inspection method according to the embodiment. FIG. 10 is a diagram illustrating an example of the defect distribution and threshold values obtained based on FIGS. 9A and 9B. 11A and 11B are diagrams illustrating a fourth example of the luminance distribution acquired in the semiconductor device inspection method according to the embodiment. FIG. 12 is a diagram illustrating an example of the defect distribution and threshold values obtained based on FIGS. 11A and 11B. 13A and 13B are diagrams illustrating a fifth example of the luminance distribution acquired in the semiconductor device inspection method according to the embodiment. FIG. 14 is a diagram illustrating an example of the defect distribution and threshold values obtained based on FIGS. 13A and 13B.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the drawings, similar components are given the same reference numerals.
FIG. 1 shows the configuration of an inspection apparatus for a semiconductor device according to the first embodiment.
A semiconductor device inspection apparatus (hereinafter referred to as an inspection apparatus) 1 includes an appearance inspection unit 2 that acquires an image of a semiconductor wafer 5 and a data processing unit 3 that performs data processing.

  The appearance inspection unit 2 includes a stage 10 on which the semiconductor wafer 5 is placed. The stage 10 includes an X stage 11 and a Y stage 12 that can horizontally move the semiconductor wafer 2 in two orthogonal directions, that is, the X direction and the Y direction, respectively. A holder 13 attached on the stage 10 is provided with positioning pins 14 for positioning the semiconductor wafer 5.

  The appearance inspection unit 2 includes an illumination unit 15 that emits light toward the semiconductor wafer 5 and an imaging unit 16 that includes a light receiving element that receives light reflected from the semiconductor wafer 5, for example, a CCD (Charge Coupled Device) sensor. Have. The imaging unit 16 is connected to the data processing unit 3, and imaging (image) data from the imaging unit 16 is input to the data processing unit 3. Note that the configuration of the appearance inspection unit 2 is not limited to the illustrated configuration, and may have a structure in which, for example, the stage 10 on which the semiconductor wafer 5 is placed is fixed and the imaging unit 16 is moved.

  The data processing unit 3 includes a control unit 21 including a central processing unit (CPU), a read only memory (ROM), and a random access memory (RAM). The data processing unit 3 further includes a display unit 22, a storage unit 23, an input / output unit 24, and an image processing unit 30. The display unit 22 includes a display unit 22 that displays an image based on image data sent from the imaging unit 16 via the bus 20, a storage unit 23 that stores data and programs, and the presence or absence of defects by processing the image data. And an image processing unit 30 for determining the position.

  The control unit 21 controls the display unit 22, the storage unit 23, the input / output unit 24, and the image processing unit 30 via the bus 20, and executes various types of defect inspection programs stored in the storage unit 23. Realize the function. Examples of the input / output unit 24 include a keyboard and mouse operated by an operator, a communication control device that communicates with a server, a drive device that controls input and output of data to an external recording device, and a printer. The unit 24 is connected to the bus 20.

  The image processing unit 30 can be functionally divided into a signal conversion unit 31, a luminance distribution creation unit 32, a region luminance comparison unit 33, a threshold setting unit 34, and a defect determination unit 35. The image processing unit 30 may be incorporated in the control unit 21.

  Based on the imaging data of the semiconductor wafer 5 imaged by the imaging unit 16, the signal conversion unit 31 grayscales the luminance at each pixel of the captured image, for example, with 256 gradations, and based on this, the semiconductor wafer 5 Create a luminance distribution. For example, the black gradation value is “0” and the white gradation value is “255”.

  The luminance distribution creating unit 32 determines the positions of the plurality of semiconductor device formation regions 6 from the xy coordinates based on the pixel position and luminance image data input from the signal converting unit 31 and the notches, orientation flats, alignment marks, and the like of the semiconductor wafer 5. Determine. The luminance distribution creating unit 32 creates luminance distribution data for each of the plurality of semiconductor device forming regions 6 arranged on the semiconductor wafer 5 shown in FIG.

  The luminance comparison unit 33 sequentially selects a plurality of semiconductor formation regions 6 in which the same structure is to be formed in the semiconductor wafer 5. Further, the luminance comparison unit 33 compares the luminance levels of the same coordinate position or the same structure between the semiconductor device formation regions 6 based on the data created by the luminance distribution creation unit 32 and compares the levels. The key difference is calculated to determine which is greater.

  Further, the luminance comparison unit 33 calculates the number of defects for which the difference in gradation is larger than a predetermined value for the priority detection region where the defect is to be found preferentially with respect to the defect in the semiconductor device formation region 6 and other regions. measure. Further, the luminance comparison unit 33 obtains the defect density of the priority detection area and the number of other defects, and if the difference between these defect densities is within a predetermined error range, the defect is detected in the entire semiconductor wafer 5. It is determined that the defect is a common defect, and the inspection is terminated. Otherwise, the process is continued.

  The threshold value setting unit 34 sets different threshold values for defect determination on the coordinates for each of the priority detection area and the other areas for the defects in the semiconductor device formation area 6 to create a threshold distribution. The defect discriminating unit 35 inputs the luminance gradation difference obtained by the luminance distribution creating unit 32, the data of the coordinate position where the difference occurs, and the threshold value data set by the threshold setting unit 34. Furthermore, the defect determination unit 35 specifies a position where the difference in luminance gradation between the plurality of selected semiconductor device formation regions 6 is equal to or greater than a threshold value based on the data, and thus a defect position, that is, a target defect. And determine other positions as unnecessary defects.

Next, a method for inspecting a conductor device for defects using the above-described inspection apparatus 1 will be described with reference to FIG.
First, the semiconductor wafer 5 is mounted on the stage 10 of the appearance inspection unit 2, and then an image of the entire top surface of the semiconductor wafer 5 is taken by the imaging device 16 (a in FIG. 2). Image data of an image captured by the imaging device 16 is input to the image processing unit 30 via the bus 20.

  In the signal conversion unit 31 of the image processing unit 30, the luminance at each pixel of the image is converted to gray scale based on the imaging data (b in FIG. 2), and the luminance distribution of the image viewed from above the semiconductor wafer 5 is calculated. It is created (c in FIG. 2). Further, the luminance distribution creating unit 32 sets the notches, orientation flats, alignment marks, and the like of the semiconductor wafer 5 as reference positions, and determines the positions of the plurality of semiconductor device forming regions 6 on the semiconductor wafer 5 (d in FIG. 2). ). Each semiconductor device formation region 6 is a region where a semiconductor integrated circuit or the like having the same structure is to be formed based on the design.

  Thereafter, the luminance distribution creating unit 32 creates luminance distribution data for each semiconductor device forming region 6 by superimposing the position of the semiconductor device forming region 6 and the luminance distribution of the semiconductor wafer 5 (e in FIG. 2). ). When there is no pattern defect in each of the plurality of semiconductor device formation regions 6, the luminance distributions are basically the same.

  Next, the area luminance comparison unit 33 compares the luminance distributions of the semiconductor device formation regions 6 with each other, and calculates the luminance difference at the same position in each of the semiconductor device formation regions 6 based on the gray scale gradation. (F in FIG. 2). In this case, the position in the semiconductor device formation region 6 may be indicated by a pixel position or an XY coordinate.

  As a general rule, there is a high possibility that a defect has occurred at a position where a difference in luminance has occurred as a result of such comparison (g in FIG. 2). When detecting the occurrence position of the defect, the plurality of semiconductor device formation regions 6 are compared with each other, and the defect is generated in the semiconductor device formation region 6 where the defect is frequently generated at the same position. (H in FIG. 2).

  Next, the defect density in the priority detection area where defects are to be found preferentially is compared with the defect density in other areas (h in FIG. 2). If the difference in defect density is within the error range, the defect is determined as a defect occurring in the entire semiconductor wafer 5, for example, a defect due to generation of dust originating from the apparatus, and the process is terminated. If it is outside the error range, the process proceeds to the next process (i in FIG. 2).

  The defect positions obtained by the difference in luminance between the semiconductor formation regions include defects that are found due to noise and defects that can be ignored in addition to the defects that have actually occurred. Further, at the defect position, there is a defect having a high importance existing in a region where the defect is to be detected, while there is a defect having a low importance existing in a region other than the region where the defect is to be detected.

  Therefore, the threshold setting unit 34 distinguishes among defects in the semiconductor device formation region 6 that are in the priority detection region where defects are to be found preferentially and those in other regions, and also eliminates noise. Further, different threshold values are set for the priority detection area and other areas (j in FIG. 2). For example, the threshold value set for the priority detection area is set to be smaller than the threshold value set for the other areas, a position where a luminance difference equal to or greater than the threshold value is set as the target defect occurrence position, and the other areas are set as unnecessary defects. The threshold value is set to a value higher than at least the luminance difference caused by the predicted noise.

  Next, the defect determination unit 35 compares the luminance difference at the selected position in the semiconductor device formation region 6 with a threshold value, and determines a position where a luminance difference equal to or larger than the threshold value is a defect occurrence position (k, l in FIG. 2). , M, n). In this case, even in areas other than the inspection priority area, if there is a difference in luminance that exceeds the threshold, it is necessary to investigate the cause of the difference, so that the position where the difference occurs is also defective. Judge as position. The detection of the defect is finished by judging the presence or absence of the defect in the selected position, for example, all or a part of the semiconductor device formation region 6 (o in FIG. 2).

  Next, the inspection method according to the present embodiment will be described more specifically with reference to the manufacturing steps of the semiconductor device shown in FIGS. 4A to 4H.

  For example, a silicon wafer 41 is used as the semiconductor wafer 5 on which the semiconductor device 6 shown in FIG. 3 is formed. On each surface of the semiconductor device formation region 6 of the silicon wafer 41, as shown in FIG. 4A, an element isolation insulating layer 42 surrounding a plurality of active regions is formed. In each of the active regions, ions of p-type impurities and n-type impurities are implanted, whereby P wells 43 and N wells 44 are formed.

A gate insulating film 45a is formed on the P well 43, and first and second gate electrodes 46a and 46b are formed on the gate insulating film 45a at intervals in the lateral direction. A gate insulating film 45b is formed on the N well 44, and third and fourth gate electrodes 46c and 46d are formed on the gate insulating film 45b at intervals in the lateral direction. The first to fourth gate electrodes 46a to 46d are formed, for example, by patterning a polysilicon film.

  Thereafter, a photoresist 61 is applied on the silicon wafer 41, and is exposed and developed, whereby a first well having an opening 61a exposing the P well 43 and the first and second gate electrodes 46a and 46b. A resist pattern 61 is formed. In this case, the N well 44 and the third and fourth gate electrodes 46 c and 46 d are covered with the first resist pattern 61.

  Thereafter, the silicon wafer 41 is placed on the stage 10 of the appearance inspection unit 3 in order to inspect defects on the silicon wafer 41 using the inspection apparatus 1 described above. Next, for example, UV light is irradiated from the illumination unit 15 toward the silicon wafer 41, and the light reflected from the silicon wafer 14 is imaged by the imaging unit 16, whereby the entire image data viewed from above the silicon wafer 41 is obtained. get. The imaging data is processed according to the flow of FIG.

  Thereby, the gray scale distributions of the luminances of the semiconductor forming regions 6 created based on the imaging data of the silicon wafer 41 are compared. In this case, in one selected semiconductor device formation region 6, a defect is generated in a portion indicated by broken lines n and v in FIG. 4A, and no defect is generated in the other semiconductor device formation region 6. Become.

  The brightness gradation distribution of the image data obtained by imaging the portion shown in FIG. 4A from above in the selected semiconductor device formation region 6 is as shown in FIG. 5B. On the other hand, in the other semiconductor device formation region 6 in which no defect has occurred, the luminance gradation distribution of the image data obtained by imaging the same portion as shown in FIG. 4A is as shown in FIG. 5A. Here, the priority detection region in which the occurrence of a defect is inherently desired to be detected is in the opening 61 a of the first resist pattern 61, that is, on the P well 43.

  The luminance gray scale distribution based on the UV light irradiation is highest in the edge portion on the first resist pattern 61 as illustrated in FIG. On the P well 43, the luminance of the gate electrodes 46a and 46b is higher than that of the surface of the silicon wafer 41. Further, it is locally higher on the gate electrodes 46 c and 46 d on the N well 44 in the region covered with the first resist pattern 61. In addition, in a defect occurrence location where contamination is attached to the locations indicated by the wavy circles v and m in FIG. 4A, the luminance protrudes in a pulse shape, for example, as shown in FIG. 5B.

  Therefore, when the difference in luminance distribution between the N well 43 and the P well 44 in the semiconductor formation region 6 to be compared and the peripheral region thereof is calculated, the result shown in FIG. 6 is obtained. That is, a luminance pulse protrudes on the exposed side position of the second gate electrode 46b on the P well 43 and on the first resist pattern 46, and further on the side of the fourth gate electrode 46d of the N well 44. A luminance distribution is obtained in which a luminance pulse is also generated at the position. Therefore, a defect has occurred in the selected semiconductor device formation region 6.

  Next, as shown in FIG. 6, the distribution of the absolute value of the luminance including the pulsed luminance is compared with the distribution of the preset threshold, and the portion of the pulsed luminance lower than the threshold is determined as an unnecessary defect. A pulse-like luminance portion that is equal to or higher than the threshold is defined as a target defect. As shown by the broken line in FIG. 6, the threshold value is set low in the priority detection area where defects are to be detected preferentially, and is set higher in other areas. Thereby, it is determined that a defect is generated only in the P well 43 region.

5A, 5B, and 6 may be displayed on the display unit 22 illustrated in FIG. 1, and only the target defect after comparison with the threshold value may be finally displayed. Of course, when there is no defect, the defect is not displayed. In addition, there is a defect in which a large pinhole is formed as an example in which there is a portion where the absolute value of the luminance greater than or equal to the threshold appears in the first resist pattern 46 other than the priority detection region.

  As described above, when there is no target defect, the process is further advanced to form the structure shown in FIG. 4B. That is, using the first and second gate electrodes 46a and 46b and the first resist pattern 61 as a mask, n-type impurity ions such as phosphorus ions or arsenic ions are formed on both sides of the first and second gate electrodes 46a and 46b. Is injected into the P-well 43. Thus, first to third n-type extension regions 47a to 47c are formed on both sides of the first and second gate electrodes 46a and 46b. A common second n-type extension region 47b is formed between the first gate electrode 46a and the second gate electrode 46b. Thereafter, the first resist pattern 61 is removed.

Next, steps required until a structure shown in FIG. 4C is formed will be described.
First, a photoresist is applied onto the silicon wafer 41 and the first to fourth gate electrodes 46a to 46d, and this is exposed and developed to form a second resist pattern 62. The second resist pattern 62 has an opening 62 a that exposes the N well 44 and has a shape that covers the P well 43.

  Thereafter, using the third and fourth gate electrodes 46c and 46d and the second resist pattern 62 as a mask, p-type impurity ions such as boron ions are formed on both sides of the third and fourth gate electrodes 46c and 46d. Ions are implanted into the N well 44. Thus, first to third p-type extension regions 48a to 48c are formed on both sides of the third and fourth gate electrodes 46c and 46d. A common second p-type extension region 48b is formed in the N well 44 in the region between the third gate electrode 46c and the fourth gate electrode 46d. Thereafter, defect inspection is performed according to the flow shown in FIG. Thereafter, the second resist pattern 62 is removed.

Next, steps required until a structure shown in FIG. 4D is formed will be described.
First, an insulating film such as a silicon oxide film is formed on the silicon wafer 41 and the first to fourth gate electrodes 46a to 46d by the CVD method. Subsequently, the insulating film is etched in the vertical direction to leave the insulating film on the side walls of the first to fourth gate electrodes 46a to 46d. Thus, the insulating films on the side walls of the first to fourth gate electrodes 46a to 46d are used as the side walls 51a to 51d.

  Subsequently, a third resist pattern (not shown) having the same shape as the first resist pattern 61 in FIG. 4A is formed on the silicon wafer 41. The third resist pattern has an opening that exposes the P well 43 and a region that covers the N well 44.

  Thereafter, n-type impurities are ion-implanted into the P well 43 using the first and second gate electrodes 46a and 46b, the sidewalls 51a and 51b, and the third resist pattern (not shown) as a mask. Thus, n-type source / drain regions 49a to 49d connected to the n-type extension regions 47a to 47c under the sidewalls 51a and 51b are formed.

Thus, the first and second n-type MOS transistors T ₁ and T ₂ and the first and second p-type MOS transistors T ₃ and T ₄ are formed. The first n-type MOS transistors _{T 1} has a first gate electrode 46a and both sides of the source / drain regions 49a, and 49b, and the like. The second n-type MOS transistor _{T 2} are, has a second gate electrode 46b of the both sides of the source / drain region 49b, a 49c like. The first p-type MOS transistor _{T 3} has a third gate electrode 46c of the both sides of the source / drain regions 50a, and 50b and the like. The second p-type MOS transistor _{T 4} is the fourth gate electrode 46d and both sides of the source / drain regions 50
b, 50c, etc.

  Further, after removing the third resist pattern (not shown), a fourth resist pattern (not shown) having an opening for exposing the N well 44 and a region covering the P well 43 is formed on the silicon wafer 41. . Thereafter, p-type impurity ions are implanted into the N well 44 using the fourth resist pattern, the third and fourth gate electrodes 46c and 46d, and the sidewalls 51c and 51d as a mask. Thereby, p-type source / drain regions 50a to 50c connected to the p-type extension regions 48a to 48c under the sidewalls 51c and 51d are formed.

Next, steps required until a structure shown in FIG. 4E is formed will be described.
First, on the silicon wafer 41, for example, a silicon oxide film is formed as the first interlayer insulating film 52 covering the first to fourth gate electrodes 46a to 46d by the CVD method. Subsequently, a photoresist is applied on the first interlayer insulating film 52, and this is exposed and developed to form a fifth resist pattern (not shown). The fifth resist pattern has openings on the first to third n-type source / drain regions 49a to 49c and the first to third p-type source / drain regions 50a to 50c. Further, by etching the first interlayer insulating film 52 through the opening of the fifth resist pattern, the first to third n-type source / drain regions 49a to 49c, the first to third p-type source / First to sixth contact holes 52a to 52f are formed on the drain regions 50a to 50c, respectively. Thereafter, the fifth resist pattern is removed.

  Thereafter, the silicon wafer 41 is placed on the stage 10 of the appearance inspection unit 3 in order to inspect the presence or absence of defects on the silicon wafer 41 using the inspection apparatus 1 described above. Next, for example, UV light is irradiated from the illumination unit 15 toward the silicon wafer 41, and the light reflected from the silicon wafer 41 is imaged by the imaging unit 16. The imaging data is processed according to the flow of FIG.

  Thereby, the luminance gradation distributions of the plurality of semiconductor formation regions 6 created based on the imaging data of the silicon wafer 41 are compared. In this case, in one semiconductor device formation region 6, a defect is generated in a portion indicated by wavy circles v and n in FIG. 4E, and no defect is generated in the other semiconductor device formation region 6.

  When the portion illustrated in FIG. 4E in the semiconductor device formation region 6 where the defect is generated is imaged from above, the luminance distribution of the image data is as shown in FIG. 7B. On the other hand, the luminance distribution of the image data obtained by imaging the same portion as that shown in FIG. 4E in the other semiconductor device formation region 6 where no defect has occurred is as shown in FIG. 7A. Here, the priority detection region in which the occurrence of a defect is to be originally detected is in the first to sixth contact holes 52a to 52f.

  As illustrated in FIG. 7A, the common distribution of luminance gradations based on UV light irradiation is locally low in the first to sixth contact holes 52a to 52f.

  When the difference in luminance distribution in each of the first interlayer insulating film 52 and the first to sixth contact holes 52a to 52f in the two semiconductor formation regions 6 to be compared is calculated, a result indicated by a solid line in FIG. 8 is obtained. It is done. According to FIG. 8, there is a luminance protrusion in the first contact hole 52a, and a luminance protrusion is generated between the first and second contact holes 52a and 52b in the first interlayer insulating film 52. It turns out that the defect has occurred in those places.

Next, as shown in FIG. 8, the distribution of the absolute value of the luminance including the defective portion is compared with the distribution of the threshold value set in advance, and the portion having the pulsed luminance lower than the threshold is determined as an unnecessary defect. On the other hand, a pulse-like luminance portion that is equal to or higher than the threshold is set as a target defect. As shown by the broken line in FIG. 8, the threshold value is set low in the regions of the first to sixth contact holes 52a to 52b where defects are to be detected preferentially, and is set higher in the other regions. As a result, it is determined that a defect has occurred only in the first contact hole 52a.

  7A, 7B, and 8 may be displayed on the display unit 22 illustrated in FIG. 1, and only the target defect may be finally displayed. Of course, when there is no defect, the defect is not displayed. In addition, when there is a portion where the luminance higher than the threshold appears on the first interlayer insulating film 52, for example, the first interlayer insulating film in a region excluding the first to sixth contact holes 52a to 52f. When a large pinhole (not shown) is formed in 52, the position is displayed on the display unit 22 as a defect.

  If there is no target defect as described above, the process proceeds further to form the structure shown in FIG. 4F by the following method.

  First, a titanium nitride film is formed as a barrier layer on the inner surfaces of the first to sixth contact holes 52 a to 52 f and the upper surface of the first interlayer insulating film 52. Subsequently, a tungsten film is formed on the titanium nitride film to embed the tungsten film in the first to sixth contact holes 52a to 52f. Thereafter, the tungsten film and the titanium nitride film on the first interlayer insulating film 52 are removed by a chemical mechanical polishing (CMP) method. Thereby, the tungsten film and titanium nitride film left in the first to sixth contact holes 52a to 52f are used as the first to sixth contact plugs 53a to 53f.

  Thereafter, the silicon wafer 41 is placed on the stage 10 of the appearance inspection unit 3 in order to inspect the presence or absence of defects on the silicon wafer 41 using the inspection apparatus 1 described above. Next, for example, UV light is irradiated from the illumination unit 15 toward the silicon wafer 41, and the light reflected from the silicon wafer 41 is imaged by the imaging unit 16. The imaging data is processed according to the flow of FIG.

  Thereby, the luminance gradation distributions of the plurality of semiconductor forming regions 6 created based on the imaging data of the silicon wafer 41 are compared with each other. In this case, in one selected semiconductor device formation region 6, a defect occurs in a portion indicated by wavy circles v and n in FIG. 4F, and no defect occurs in the other semiconductor device formation region 6.

  When the portion illustrated in FIG. 4F in the semiconductor device formation region 6 where the defect is generated is imaged from above, the luminance distribution of the image data is as shown in FIG. 9B. On the other hand, the luminance distribution of the image data obtained by imaging the same part as shown in FIG. 4F of the other semiconductor device formation region 6 where no defect has occurred is as shown in FIG. 9A. Here, the priority detection areas where it is desired to detect the occurrence of defects inherently are on the first to sixth contact plugs 53a to 53f.

  In the common part of the luminance gradation distribution in the semiconductor device formation region 6, the first to sixth contact plugs 53a to 53f are higher than the first interlayer insulating film 52 as illustrated in FIG. 9A. ing.

Accordingly, when the difference in luminance distribution between the first interlayer insulating film 52 and the first to sixth contact plugs 53a to 53f in the two semiconductor formation regions 6 to be compared is calculated, the result shown by the solid line in FIG. Is obtained. According to FIG. 10, there is a decrease in luminance in the first contact plug 53 a, and a luminance projection is generated between the first and second contact plugs 53 a and 53 b in the first interlayer insulating film 52. It turns out that the defect has occurred in those places.

  Next, as shown in FIG. 10, the distribution of the absolute value of the luminance that becomes the detected defect is compared with the distribution of the threshold, and the protrusion having the luminance lower than the threshold is determined as an unnecessary defect. To do. As shown by the broken line in FIG. 10, the threshold value is set low in the regions of the first to sixth contact plugs 53a to 53b where defects are to be detected preferentially, and is set higher in the other regions. Thereby, it is determined that a defect is generated only on the first contact plug 52a. As such a defect, for example, there is a defect having a defective metal filling at the edge of the first contact plug 52a.

  9A, 9B, and 10 may be displayed on the display unit 22 illustrated in FIG. 1, and only the target defect may be finally displayed. Of course, when there is no defect, the defect is not displayed. Further, as an example in which there is a portion where the first interlayer insulating film 52 has a luminance higher than the threshold, for example, the first interlayer insulating film 52 in the region excluding the first to sixth contact plugs 53a to 53f. When a large metal residue exists on the upper surface, the position is also a target defect. A large metal residue becomes a problem because it causes a short circuit of the wiring formed on the first interlayer insulating film.

As described above, when there is no defect based on the threshold, the structure shown in FIG. 4G is formed by the following method.
First, the second interlayer insulating film 54 is formed on the first interlayer insulating film 52 and the first to sixth contact plugs 53a to 53f by the CVD method. As the second interlayer insulating film 54, for example, a silicon oxide film is formed by a CVD method. Thereafter, the second interlayer insulating film 54 is patterned to form first to sixth wiring grooves 54a to 54f connected to the first to sixth contact plugs 53a to 53f, respectively.

  Thereafter, in order to inspect defects on the silicon wafer 41 using the above-described inspection apparatus 1, the silicon wafer 41 is placed on the stage 10 of the appearance inspection unit 3. Next, for example, UV light is irradiated from the illumination unit 15 toward the silicon wafer 41, and the light reflected from the silicon wafer 41 is imaged by the imaging unit 16. The imaging data is processed according to the flow of FIG.

  Thereby, the luminance gradation distributions of the plurality of semiconductor formation regions 6 created based on the imaging data of the silicon wafer 41 are compared. In this case, in the selected semiconductor device formation region 6, defects are generated in the portions indicated by the wavy circles v and n in FIG. 4G, and no defects are generated in the other semiconductor device formation regions 6.

  When the portion illustrated in FIG. 4G in the semiconductor device formation region 6 where the defect is generated is imaged from above, the luminance distribution of the image data is as shown in FIG. 11B. On the other hand, the luminance distribution of the image data obtained by imaging the same part as shown in FIG. 4G of the other semiconductor device formation region 6 where no defect has occurred is as shown in FIG. 11A. Here, the priority detection area in which the occurrence of a defect is inherently desired to be detected is in the first to sixth wiring grooves 54a to 54f.

  As shown in FIG. 11A, the defect-free portion of the luminance gradation distribution in the semiconductor device formation region 6 based on the UV light irradiation has the second interlayer insulation in the first to sixth wiring grooves 54a to 54f. It is lower than that on the film 54.

Therefore, when the difference in luminance distribution between the second interlayer insulating film 54 and the first to sixth wiring grooves 54a to 54f in the two semiconductor formation regions 6 to be compared is calculated, the result shown by the solid line in FIG. Is obtained. According to FIG. 12, there is a pulse-like luminance protrusion in the first wiring groove 54a, and the luminance between the first and second wiring grooves 54a and 54b in the second interlayer insulating film 54 is further increased. It can be seen that protrusions are generated. Therefore, a defect has occurred at the location of these protrusions. The defect in the first wiring groove 54a is, for example, a defect that is partially narrowed due to a patterning defect.

  Next, as shown in FIG. 12, the distribution of the absolute value of the luminance that becomes the detected defect is compared with the distribution of the threshold, and the protrusion having the luminance lower than the threshold is determined as an unnecessary defect. To do. As shown by the broken line in FIG. 12, the threshold value is set low in the areas of the first to sixth wiring grooves 54a to 54f where defects are to be detected preferentially, and is set higher in the other areas. As a result, it is determined that a defect has occurred only on the first wiring groove 54a.

  11A, 11B, and 12 may be displayed on the display unit 22 illustrated in FIG. 1, and only the target defect may be finally displayed. Of course, when there is no defect, the defect is not displayed. In addition, as an example in which the absolute value of the luminance equal to or higher than the threshold value appears in the second interlayer insulating film 54, a large pinhole may exist in the second interlayer insulating film 54.

When the above-described target defect does not exist, the structure shown in FIG. 4H is formed by the following method.
First, a barrier metal film and a copper seed layer are sequentially formed on the inner surfaces of the first to sixth wiring grooves 54a to 54f and the upper surface of the second interlayer insulating film 54 by, for example, sputtering. Subsequently, using the copper seed layer and the barrier metal film as electrodes, a copper film is formed on the copper seed film by electrolytic plating. A tantalum film is formed as the barrier metal film.

  Thereafter, the copper film, the copper seed film, and the copper film on the upper surface of the second interlayer insulating film 54 are removed by a CMP method. Thereby, the copper film, the copper seed film, and the copper film left in the first to sixth wiring grooves 54a to 54f are used as the first to sixth wirings 55a to 55f having a damascene structure.

  Thereafter, the silicon wafer 41 is placed on the stage of the appearance inspection unit 3 in order to inspect defects on the silicon wafer 41 using the inspection apparatus 1 described above. Next, for example, UV light is irradiated from the illumination unit 15 toward the silicon wafer 41, and the light reflected from the silicon wafer 41 is imaged by the imaging unit 16. The imaging data is processed according to the flow of FIG.

  Thereby, the luminance gradation distributions of the plurality of semiconductor formation regions 6 created based on the imaging data of the silicon wafer 41 are compared. In this case, in one selected semiconductor device formation region 6, a defect occurs in a portion indicated by broken lines v and n in FIG. 4H, and no defect occurs in the other semiconductor device formation region 6.

  When the portion illustrated in FIG. 4H in the semiconductor device formation region 6 in which a defect has occurred is imaged from above, the luminance distribution of the image data is as shown in FIG. 13B. On the other hand, the luminance distribution of the image data obtained by imaging the same part as shown in FIG. 4H of the other semiconductor device formation region 6 where no defect has occurred is as shown in FIG. 13A. Here, the priority detection area where it is originally desired to detect the occurrence of a defect is on the first to sixth wirings 55a to 55f.

  The portion of the semiconductor device formation region 6 based on UV light irradiation where there is no defect in the luminance distribution is the first to sixth wirings 55a to 55f as compared to the second interlayer insulating film 54 as illustrated in FIG. 13A. It is getting higher.

Accordingly, when the difference in luminance distribution between the second interlayer insulating film 54 and the first to sixth wirings 55a to 55f in the two semiconductor formation regions 6 to be compared is calculated, the result shown by the solid line in FIG. 14 is obtained. can get. According to FIG. 14, there is a decrease in luminance on the first wiring 55 a, and a luminance protrusion is generated between the first and second wirings 55 a and 55 b in the second interlayer insulating film 54. It turns out that the defect has occurred in those places. As an example of the decrease in luminance, for example, there is a case where the first wiring groove 54a is formed narrower than designed, or a void is generated in the first wiring 55a.

  Next, as shown in FIG. 14, the distribution of the absolute value of the luminance that becomes the detected defect is compared with the distribution of the threshold value set in advance, and the protrusion having the luminance lower than the threshold value is determined as an unnecessary defect. Defective objective. As shown by the broken line in FIG. 14, the threshold value is set low in the areas of the first to sixth wirings 55a to 55f where the defect is to be detected preferentially, and is set higher in the other areas. Thereby, it is determined that a defect is generated only on the first wiring 55a.

13A, 13B, and 14 may be displayed on the display unit 22 illustrated in FIG. 1, and only the target defect may be finally displayed. Of course, when there is no defect, the defect is not displayed. In addition, when there is a portion where the luminance higher than the threshold appears in the second interlayer insulating film 54, for example, when a large metal residue exists in the second interlayer insulating film 54, the position is displayed as a defect. Displayed on the unit 22.
If there is no defect based on such a threshold value, the process of further forming an interlayer insulating film and wiring is continued, but the details are omitted.

  As described above, in a defect inspection method in a desired process among a plurality of processes for forming a semiconductor device, priority is given to a defect when determining the defect by comparing the brightness level of the defect occurrence portion with a threshold value. As for the area to be discovered, the threshold is set lower than other areas.

  This makes it easy to find the target defect in the priority inspection area where you want to find defects preferentially, and also makes it easy to find serious defects in other areas. This makes it easier to analyze the cause of defects used. In addition, when a target defect has occurred in an area other than the priority inspection area, the defect is a high-level defect, so that a separate investigation can be promoted.

  In the above description, the target defect is determined by comparing the luminance distributions between the semiconductor device formation regions. However, the luminance distributions of a plurality of regions where the same structure is formed in one semiconductor device formation region are mutually compared. You may determine by comparing and calculating | requiring those differences.

  All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, such examples and It is interpreted without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. While embodiments of the present invention have been described in detail, it will be understood that various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the invention.

Next, features of the embodiment of the present invention will be described.
(Supplementary Note 1) Obtaining image data of a plurality of inspection target areas, comparing the luminance at the same position between areas forming the same structure among the plurality of inspection target areas, obtaining a luminance difference distribution from the difference in luminance, In each of the plurality of inspection target areas, a threshold distribution is set so that a threshold of a priority detection area to be preferentially inspected is lower than a threshold of other areas, and the threshold distribution of the luminance difference distribution is equal to or higher than the threshold distribution. A defect inspection method characterized by determining a position as a target defect occurrence position. (Appendix 2) Determining the existence of the target defect occurrence position in one inspection target area in which the target defect occurrence position is determined for two or more of the inspection target areas among the plurality of inspection target areas The defect inspection method according to appendix 1, wherein:
(Supplementary Note 3) The defect inspection method according to Supplementary Note 1 or Supplementary Note 2, wherein the distribution of the luminance difference is obtained as an absolute value.
(Supplementary note 4) The defect inspection method according to any one of supplementary notes 1 to 3, wherein the plurality of inspection target regions are different semiconductor device formation regions.
(Supplementary Note 5) The defect inspection method according to any one of Supplementary Notes 1 to 3, wherein the plurality of inspection target regions are different regions in which the same structure is formed in the same semiconductor formation region.
(Appendix 6) Before determining the target defect occurrence position, the respective defect densities of the priority detection area and the other areas are obtained based on the luminance difference distribution, and the difference between the defect densities is preset. The defect inspection method according to appendix 1, wherein if it is within the error range, it is determined that the defect is a common defect common to the entirety.
(Appendix 7)
A region discriminating unit that discriminates a plurality of inspection target regions in which the same structure is formed, a luminance comparison unit that compares the luminance distributions of the plurality of inspection target regions to obtain a difference in the luminance distribution, and preferentially And a threshold setting unit that sets a threshold lower than the other regions, and a defect determination unit that determines a position that is a value equal to or higher than the threshold in the luminance distribution as a target defect occurrence position. Defect inspection equipment.
(Additional remark 8) The defect inspection apparatus of Additional remark 7 characterized by having a signal conversion part which makes the said brightness | luminance in the said test | inspection area | region into gray scale.
(Additional remark 9) It has an irradiation part which irradiates light to the said test object area | region, and an imaging part which images the said test object area | region based on the reflection of the said light, The appendix 7 or appendix 8 characterized by the above-mentioned Defect inspection equipment.

DESCRIPTION OF SYMBOLS 1 Inspection apparatus 2 Appearance inspection part 3 Data processing part 5 Semiconductor wafer 6 Semiconductor device formation area 10 Wafer stage 15 Illumination part 16 Imaging part 5, 41 Semiconductor wafer 20 Bus 21 Control part 22 Display part 23 Storage part 24 Input / output part 30 Data Processing unit 31 Signal conversion unit 32 Region determination unit 33 Region luminance comparison unit 34 Threshold setting unit 35 Defect determination unit

Claims (5)

Acquire image data of multiple inspection areas,
The luminance difference distribution is obtained from the luminance difference by comparing the luminance at the same position between the regions forming the same structure among the plurality of inspection target regions,
In each of the plurality of inspection target areas, a threshold distribution is set so that the threshold of the priority detection area to be preferentially inspected is lower than the thresholds of the other areas,
A defect inspection method, wherein a position that is equal to or greater than the threshold distribution in the luminance difference distribution is determined as a target defect occurrence position.   The presence of the target defect occurrence position is determined in one inspection target area in which the target defect occurrence position is determined for two or more of the inspection target areas among the plurality of inspection target areas. The defect inspection method according to claim 1. Before determining the target defect occurrence position,
Obtain the defect density of each of the priority detection area and the other area based on the luminance difference distribution,
2. The defect inspection method according to claim 1, wherein if the difference between the defect densities is within a preset error range, it is determined that the defect is a common common defect as a whole. . A region discriminating unit for discriminating a plurality of inspection target regions in which the same structure is formed;
A luminance comparison unit that compares the luminance distribution of each of the plurality of inspection target areas to obtain a difference in the luminance distribution;
A threshold setting unit that sets a threshold so that a priority detection area to be preferentially inspected with respect to the difference in luminance distribution has a lower threshold than other areas;
The defect inspection apparatus which has a defect determination part which determines the position used as the value more than the said threshold value among the distribution of the said brightness | luminance as a target defect occurrence position.   The defect inspection apparatus according to claim 4, further comprising a signal conversion unit configured to grayscale the luminance in the inspection target region.

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