JP3621222B2 - Pattern arrangement recognition method for semiconductor substrate - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for recognizing a pattern arrangement of a semiconductor substrate for recognizing the arrangement of patterns formed on the semiconductor substrate, and more particularly, to a pattern arrangement recognition for a semiconductor substrate capable of performing automatic pattern arrangement recognition in a short time and simply. Regarding the method.
[0002]
[Prior art]
In the manufacture of semiconductor ICs, various patterns are formed on a semiconductor substrate. Since the positions of these patterns need to be accurate with respect to each other, the amount of positional deviation between patterns is measured every time the pattern is formed. (See JP-A-6-258826 and JP-A-8-115874).
[0003]
Here, the measurement of the amount of positional deviation requires pattern arrangement information indicating the arrangement in which the pattern (chip portion) is formed on a semiconductor substrate such as a wafer. In general, information on the pattern arrangement is manually input based on the actual pattern arrangement on the semiconductor substrate.
[0004]
[Problems to be solved by the invention]
However, as described above, there is a problem that the work efficiency is poor in the method of manually inputting the pattern arrangement information as described above, and as a method of automatically recognizing the pattern arrangement, an imaging optical system having a wide field of view is used. There has been a method of inspecting the presence or absence of a pattern by scanning the entire surface of a semiconductor substrate.
[0005]
However, in the configuration in which the entire surface of the semiconductor substrate is scanned as described above, there is a problem that it takes time to complete the entire surface scanning, and as a result, it takes time to recognize the pattern arrangement. Since it is necessary to recognize the boundary of the pattern area from the field of view, the processing is complicated, and further, there is a problem that a large memory capacity is required for recording the scanning result by performing the entire scanning.
[0006]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for recognizing a pattern arrangement of a semiconductor substrate that can cope with such problems and can perform automatic pattern arrangement recognition in a short time and simply.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor substrate pattern arrangement recognition method according to the present invention virtually sets a pattern arrangement on a semiconductor substrate based on a chip pitch size, and a pattern that is outside the semiconductor substrate from the pattern arrangement. And a pattern overlapping the boundary is deleted based on the size of the semiconductor substrate, and then an attention point for optically detecting the presence or absence of the pattern is set at the outermost part of the pattern array, which corresponds to the attention point of the semiconductor substrate. Based on the result of optically detecting the portion to be corrected, the presence or absence of the pattern at the outermost part of the pattern array is corrected and the final pattern array recognition result is output.
[0008]
Here, the point of interest is set only on one side of the axially symmetric pattern arrangement, the presence or absence of a pattern is optically detected, and the detection result of the presence or absence of the pattern on one side is applied to the other side in an axisymmetric manner. A configuration that corrects the presence or absence of a pattern is preferable.
Moreover, it is preferable to set the said attention point based on the combination of the presence or absence of the pattern in an adjacent chip | tip part.
[0009]
Furthermore, it is preferable to set the attention point as a lattice point at the chip boundary.
Further, the reflected light of the light irradiated to the semiconductor substrate is detected within a visual field range centering on the lattice point as the attention point and including the corner of the chip portion around the lattice point, and the detected reflection It can be configured to detect the presence or absence of a pattern around the lattice point based on light.
[0010]
Further, the visual field range is divided into four regions along the pattern arrangement, and the histogram information of the reflected light level is obtained for each of the four regions, and the presence / absence of the pattern in the four regions around the lattice points is detected based on the histogram information. It can be set as the structure to do.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a diagram showing an outline of an optical apparatus for carrying out a pattern arrangement recognition method for a semiconductor substrate according to the present invention.
[0012]
In FIG. 1, a wafer 11 as a semiconductor substrate is placed on an XY table 12. Illumination light from the light source 13 is deflected by the half mirror 14 and irradiated to the wafer 11 via the microscope objective lens 15, and reflected light from the wafer 11 is CCD or the like via the microscope objective lens 15 and the half mirror 14. The image is formed on the image sensor 16. An image signal from the image sensor 16 is output to the image processing unit 17, and the presence or absence of a pattern is determined by image processing in the image processing unit 17.
[0013]
FIG. 2 schematically shows a procedure of a pattern arrangement recognition method performed using the optical apparatus shown in FIG. 1. According to the procedure shown in FIG. Whether a pattern corresponding to each chip is formed in such an arrangement is automatically recognized.
[0014]
In FIG. 2, first, in (a), based on the pitch size of the chip, a pattern arrangement having a predetermined number of vertical and horizontal patterns that include the wafer size is virtually set. Here, the pattern is formed so that the lattice point at the center of the pattern array coincides with the center of the wafer. Correspondingly, the pattern array to be virtually set also includes the center of the wafer and the lattice point. Are set to match. Information such as the pitch size and wafer size is input to the image processing unit 17 via communication with an external device or a man-machine interface.
[0015]
Next, in FIG. 2B, on the virtually set pattern arrangement, the pattern outside the wafer size and the pattern overlapping the boundary (the pattern indicated by the diagonal lines in FIG. 2B) are deleted. . In this state, only the non-existent pattern is deleted, and the portion where the pattern is not actually formed (the pattern indicated by the diagonal lines in FIG. 2C) remains in the array. May have been.
[0016]
Therefore, in FIG. 2C, the point of interest for detecting the presence or absence of the pattern by optical detection of the pattern on the actual wafer on the pattern arrangement narrowed down to the wafer size in the above (b) is shown in the pattern arrangement. Set to the outermost. Then, from the optical detection result in the visual field range centering on the coordinate position corresponding to this point of interest, the portion where the pattern is not actually formed although it is within the wafer size (indicated by the oblique lines in FIG. 2C) The pattern shown) is discriminated from the actual wafer, and this is deleted from the pattern array. By the above procedure, a final pattern arrangement recognition result as shown in FIG. 2D is obtained.
[0017]
Here, since the pattern arrangement on the wafer is generally set to be axially symmetrical (right and left symmetrical in FIG. 2), if optical detection of the pattern is performed only on one side of the axial symmetry, Since the result can be directly applied to the other side in an axially symmetrical manner, in the procedure shown in FIG. 2, the point of interest is set and optically detected only for the left half, and the result is also applied to the right pattern arrangement in the axially symmetrical manner. It is made to reflect. As a result, the number of points that require optical detection can be halved, and the time required for automatic recognition of the pattern arrangement can be reduced.
[0018]
Also, since the pattern (chip portion) boundary is predicted by virtually setting the pattern arrangement in advance, it is not necessary to scan the wafer 11 to detect the presence or absence of the pattern, and the pattern may not be formed. Optical detection may be performed in a distributed manner with a certain portion as a point of interest, and in this embodiment, the presence or absence of a pattern in four regions around the lattice point can be detected with a lattice point of the pattern array as a point of interest. It is. Specifically, in FIG. 2C, a lattice corresponding to a corner on the wafer center side of the deleted pattern at the outermost portion that is stepped by the deleted pattern that overlaps the wafer size boundary. The points are set as the attention points 1 to 3, and the presence or absence of the pattern in the four regions around the attention point is detected from the information in the same visual field range by optical detection with the attention points 1 to 3 being the center of the visual field range. I can do it.
[0019]
As shown in FIGS. 2E and 2F, the visual field range only needs to include corners of four regions adjacent to each other through a point of interest (lattice point). And the presence or absence of a pattern in each of the four regions is detected based on the difference in the reflected light level depending on the presence or absence of the pattern.
[0020]
From the optical detection results at the points of interest 1 and 2 (FIG. 2E), there are actually three patterns around the points of interest 1 and 2 except for the patterns that have been deleted in advance as overlapping the wafer size boundary. Since it is determined that the pattern is deleted, the pattern is not deleted. However, at the point of interest 3 (FIG. 2 (f)), the pattern adjacent to the right and above the pattern deleted as overlapping the wafer size boundary ( As a result of detecting that the pattern (indicated by diagonal lines in FIG. 2 (f)) does not actually exist, both the patterns are deleted.
[0021]
According to the pattern arrangement recognition method having such a configuration, since the optical detection of the pattern may be performed within a relatively narrow field of view at a limited number of points of interest, the entire surface of the wafer is optically scanned to check for the presence or absence of the pattern. The processing time for optical detection is shorter compared to the case of detecting the boundary, and boundary detection is performed by performing optical detection in the visual field range centering on the lattice point on the virtually set pattern array. Such a complicated process is not required, and the memory capacity for recording the optical detection result may be small.
[0022]
Next, the detailed contents of the pattern arrangement recognition method schematically described above will be described with reference to the flowcharts of FIGS.
First, in S1, the coordinates of the wafer size are converted into coordinates from the wafer center, and in the next S2, a chip matrix (pattern arrangement) composed of a coordinate system from the wafer center is created based on the pitch size. As shown in FIGS. 6A and 6B, the chip matrix (chip presence / absence table) is a matrix having a predetermined number of vertical and horizontal dimensions including the wafer size, and each value of the matrix is a chip (pattern). ) Initially set to “1” indicating presence.
[0023]
In S3, a process of deleting a chip (pattern) that overlaps the outside and the boundary of the wafer size is performed. The deletion of the chip (pattern) means that the value at the corresponding position in the chip matrix is rewritten to “0” indicating no chip (pattern).
[0024]
The specific processing contents of S3 are shown in S31 to S35 of FIG.
In S31, it is determined whether or not all the processes for deleting other than the chips (patterns) within the wafer size are completed on the chip matrix (chip presence / absence table). If the processing has not been completed, the process proceeds to S32, in which the data on the presence / absence of the chip (pattern) is sequentially read, and in the next S33, the coordinates of the four corners of the chip portion corresponding to the data on the presence / absence of the chip (pattern) ( The coordinates from the wafer center are calculated.
[0025]
In S34, it is determined whether or not the coordinates of the four corners of the chip are larger than the neighboring wafer circumference (boundary) coordinates. If at least one of the four corner coordinates is larger than the wafer circumferential coordinate, the process proceeds to S35, and the corresponding chip (pattern) is deleted as corresponding to a chip exceeding the wafer size. In S35, as shown in S35 ′, the “chipless” code (“0” in the present embodiment) is set at the corresponding chip position on the chip matrix (chip presence / absence table), thereby exceeding the wafer size. After the chip is deleted, the process returns to S31 to determine whether or not the remaining chip (pattern) is within the wafer size. On the other hand, if all the coordinates of the four corners are smaller than the wafer circumferential coordinates, the chip matrix (chip presence / absence table) need not be updated, and the process directly returns to S31.
[0026]
In the above processing, on the chip matrix (chip presence / absence table) initially set to “1” indicating that all values are present, all chip portions exceeding the wafer size are rewritten to “0” indicating that there is no chip. (See FIGS. 7A and 7B).
[0027]
Next, the process proceeds to S4, and the point of interest for performing optical detection on the actual wafer is extracted. The point of interest is based on the chip portion that first becomes “1” (with a chip) when the horizontal chip presence / absence data is searched from the left side to the right side in FIG. Lattice points surrounded by the chip matrix of “1” when the data on the lower side of the size center is “1”, the left side is also “1”, and the next left is “0” (See FIG. 8). That is, the above-described attention point extraction results in the extraction of a portion where the boundary of chip presence / absence (outermost part) is slanted and becomes a combination of 0, 0, 0, 1 in the combination of vertical and horizontal 2 × 2 chips. A part or a part that is a combination of 1,1,1,0 is extracted.
[0028]
In addition, when all the points of interest are set in the part where the boundary of presence / absence of the chip is slanted as described above, the same chip part may be read redundantly by reading an optical pattern described later. In order to avoid overlapping readings as much as possible, combinations of attention points that do not overlap readings may be selected from the set attention points. That is, when the attention point is continuously set for each lattice point, two corners of one chip portion are individually detected by optical detection at different attention points, and 2 for one chip portion. Therefore, it is preferable to set the attention point so that only one corner is optically detected as much as possible for one chip portion.
[0029]
When the attention point is extracted, in S5, the XY table 12 is driven so that the center of the visual field range of the optical system including the half mirror 14, the microscope objective lens 15, the imaging element 16, and the like coincides with the attention point. The wafer 11 placed on the XY table 12 is moved (see FIG. 9). As shown in FIG. 9, the visual field range of the optical system only needs to include the corners of the four chip portions around the point of interest, and the entire area of the four chips need not be the visual field range.
[0030]
When the center of the visual field range coincides with the point of interest, the image data obtained at that time is taken into the image processing unit 17 in S6. In the image processing unit 17, the two-dimensional image data obtained by the image sensor 16 is divided into four vertically and horizontally along the pattern arrangement with the point of interest as the center (S 7: see FIG. 10), and the divided four regions are divided. The distribution (histogram) of the image data is calculated (S8: see FIG. 11).
[0031]
In the optical system, when a pattern is present, the level of reflected light is reduced and a low value is output as image data. The characteristics of the histogram differ depending on the presence or absence of the pattern as shown in FIG. . That is, in the above four areas, in the area where the pattern exists, the histogram tends to be darker due to the presence of the pattern (see FIG. 11A), and conversely, in the area where the pattern does not exist, the histogram is brighter. (See FIG. 11B), the presence or absence of a pattern can be determined in each of the four regions based on the characteristics of the histogram.
[0032]
Therefore, in S9, the presence or absence of four chips (patterns) around the point of interest is determined based on the characteristics of the histogram, and the determination result is “1” or “1” indicating the presence or absence of a chip (pattern) for each point of interest. “0” (see CASE 1 to CASE 3 in FIG. 4 S9), and “1” on the chip matrix (chip presence / absence table) set in S3, the optical for each point of interest. As for a chip portion in which no chip is “0” from the detection result, the corresponding portion of the chip matrix (chip presence / absence table) is rewritten to “0”. As a result, it is possible to exclude a chip portion that does not actually exist from among the chips (patterns) that are within the wafer size (see FIG. 12).
[0033]
Since the extraction of the point of interest and the optical detection of the pattern at the point of interest are performed only on the left side of the symmetrical chip (pattern) array as described above, in S10, the optical detection result in the left half Is inverted in the horizontal direction (X direction) (applied as it is in axial symmetry), the right half matrix data is corrected, and the corrected matrix data (pattern arrangement) is output as the final recognition result.
[0034]
【The invention's effect】
Since the present invention is configured as described above, after removing a pattern deviating from the semiconductor substrate size from the pattern arrangement set based on the pitch size, the pattern arrangement is corrected from the optical detection result at the outermost part of the pattern arrangement. By obtaining the final recognition result, optical pattern detection can be limited to a plurality of dispersed locations, and automatic pattern recognition can be performed in a short time and easily. Yes.
[0035]
Further, by performing optical pattern detection only on one side of the axially symmetric pattern array, the number of points for optical detection can be reduced, and the time required for pattern pattern recognition can be further shortened.
Furthermore, by setting the point for performing optical pattern detection based on the combination of the presence / absence of patterns in adjacent chip portions, it is possible to accurately set the point that requires optical detection.
[0036]
In addition, by setting the point for performing optical pattern detection to the lattice point at the chip boundary, optical pattern detection can be performed efficiently.
Moreover, the presence or absence of a pattern can be reliably detected by detecting the presence or absence of a pattern based on the difference in reflectance.
Furthermore, by obtaining histogram information for each region into which the visual field range is divided and detecting the presence / absence of a pattern, the difference in reflectance can be determined with high accuracy, and thus the presence / absence of a pattern can be detected with high accuracy.
[Brief description of the drawings]
FIG. 1 is a diagram showing an outline of an optical apparatus for carrying out a pattern arrangement recognition method according to the present invention.
FIG. 2 is a diagram schematically showing an embodiment of a pattern arrangement recognition method according to the present invention.
FIG. 3 is a flowchart showing in detail a pattern recognition procedure in the embodiment.
FIG. 4 is a flowchart showing in detail a pattern recognition procedure in the embodiment.
FIG. 5 is a flowchart showing how patterns are deleted based on the wafer size in the embodiment.
FIG. 6 is a diagram showing an initial state of a chip matrix (pattern array) in the embodiment.
7 is a diagram showing a chip matrix (pattern arrangement) after pattern deletion based on the wafer size in the embodiment. FIG.
FIG. 8 is a diagram showing a point of interest for performing optical detection of a pattern in the embodiment.
FIG. 9 is a diagram showing a correlation between the pattern arrangement and the field of view in which optical detection is performed in the embodiment.
FIG. 10 is a diagram showing how the visual field range is divided in the embodiment.
FIG. 11 is a diagram showing a correlation between the presence / absence of a pattern and histogram characteristics in the embodiment.
FIG. 12 is a diagram showing how a chip matrix is corrected based on an optical detection result at a point of interest in the embodiment.
[Explanation of symbols]
11 ... Wafer (semiconductor substrate)
DESCRIPTION OF SYMBOLS 12 ... XY table 13 ... Light source 14 ... Half mirror 15 ... Microscope objective lens 16 ... Image sensor 17 ... Image processing unit

Claims (6)

After virtually setting the pattern arrangement on the semiconductor substrate from the pitch size of the chip, after deleting the pattern outside the semiconductor substrate and the pattern overlapping the boundary from the pattern arrangement based on the size of the semiconductor substrate, A point of interest for optically detecting the presence or absence of a pattern is set at the outermost part of the pattern array, and based on the result of optically detecting a portion corresponding to the point of interest of the semiconductor substrate, A method for recognizing a pattern arrangement on a semiconductor substrate, comprising correcting a pattern presence / absence and outputting a final pattern arrangement recognition result. The point of interest is set only on one side of the axisymmetric pattern arrangement to detect the presence / absence of the pattern, and the presence / absence of the pattern is detected by applying the detection result of the pattern presence / absence on the one side to the other side The method for recognizing a pattern arrangement of a semiconductor substrate according to claim 1, wherein: 3. The method of recognizing a pattern on a semiconductor substrate according to claim 1, wherein the point of interest is set based on a combination of presence / absence of patterns in adjacent chip portions. 4. The method of recognizing a pattern arrangement on a semiconductor substrate according to claim 1, wherein the point of interest is set to a lattice point at a chip boundary. The reflected light of the light irradiated to the semiconductor substrate is detected within the field of view including the corner of the chip portion around the lattice point as the center of interest, and the detected reflected light is converted into the detected reflected light. 5. The method for recognizing a pattern arrangement on a semiconductor substrate according to claim 4, wherein the presence or absence of a pattern around the lattice point is detected based on the pattern. Dividing the visual field range into four regions along the pattern arrangement, obtaining the histogram information of the reflected light level for each of the four regions, and detecting the presence or absence of a pattern in the four regions around the lattice points based on the histogram information 6. The method for recognizing a pattern arrangement of a semiconductor substrate according to claim 5, wherein:

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