JP4266689B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP4266689B2
JP4266689B2 JP2003105225A JP2003105225A JP4266689B2 JP 4266689 B2 JP4266689 B2 JP 4266689B2 JP 2003105225 A JP2003105225 A JP 2003105225A JP 2003105225 A JP2003105225 A JP 2003105225A JP 4266689 B2 JP4266689 B2 JP 4266689B2
Authority
JP
Japan
Prior art keywords
semiconductor device
base
substrate
semiconductor element
connecting material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003105225A
Other languages
Japanese (ja)
Other versions
JP2004311820A (en
Inventor
吾朗 出田
政明 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2003105225A priority Critical patent/JP4266689B2/en
Publication of JP2004311820A publication Critical patent/JP2004311820A/en
Application granted granted Critical
Publication of JP4266689B2 publication Critical patent/JP4266689B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

【０００１】
【発明の属する技術分野】
この発明は、ベースと、このベースに接続材を介して接続された基板と、この基板に搭載された半導体素子とを備えた半導体装置に関するものである。
【０００２】
【従来の技術】
従来、半導体チップと基材とが接合金属であるはんだ合金により接合された半導体装置が知られている（例えば、特許文献１参照）。
【０００３】
【特許文献１】
特開平８−２６４６８１号公報（図１１）
【０００４】
【発明が解決しようとする課題】
従来の半導体装置では、半導体チップと接合金属のはんだ合金、あるいはこのはんだ合金と基材のアルミナとの熱膨張係数が大きく異なるため、半導体装置を動作中にこれ自身から発生する熱や半導体装置が設置される環境の温度変化等によって、半導体チップと基材との接合部に熱応力が生じ、これによって接合部のはんだ合金に亀裂が発生し、半導体チップから基材への熱の流路が狭められるため、十分な放熱が得られないとともに、亀裂が伝播し、最終的には半導体装置が破壊するに至るという問題点があった。
【０００５】
この発明は、上記のような問題点を解決することを課題とするものであって、ベースと半導体素子を搭載した基板との間での熱膨張係数の差に起因して接続材の亀裂の発生を起こさせるようなことのない半導体装置を得ることを目的とする。
【０００６】
【課題を解決するための手段】
この発明に係る半導体装置は、ベースと、このベースに接続材を介して接続された基板と、この基板に搭載された半導体素子とを備え、前記接続材は、前記半導体素子の作動時は液相である液体金属であり、前記液体金属は、周囲が樹脂で覆われ、この樹脂により液相の前記液体金属の流出が防止され、前記樹脂は、ゼリー状のゲルであり、前記基板、前記半導体素子は、密封された容器に内蔵され、前記容器内には、前記樹脂を加圧し続ける加圧気体が封入されて、前記基板と前記ベースとの間に挟まれた前記接続材は加圧されるようになっている。
【０００７】
【発明の実施の形態】
実施の形態１．
図１はこの発明の実施の形態１による半導体装置を示す側断面図である。
この半導体装置は、銅合金からなるベース３と、このベース３に接続材９を介して接続されたセラミック基板２と、このセラミック基板２に搭載されたＳｉからなる半導体素子１と、ベース３とともに容器を構成するエポキシ樹脂製のケース４と、絶縁材で例えば安価なシリコーン樹脂からなるゼリー状のゲル１０とを備えている。
セラミック基板２は、上面と下面に例えば銅からなる導電膜２ａが形成され、芯材が例えば窒化アルミニウムで構成されている。接続材９は、半導体素子１の作動による発熱で溶融するとともに、半導体素子１の非作動時には凝固する液体金属であり、具体的には融点が２８℃のガリウム金属で構成されている。この接続材９は、固相のときには、導電膜２ａおよびベース３の両面に接触しているとともに、ケース４の下側内側面で内側に突出した突起部４ａで平面方向の移動が規制されている。
【０００８】
この発明の半導体装置では、半導体素子１が作動して発熱すると、その熱がセラミック基板２を通じて接続材９やベース３に伝達されて半導体装置全体の温度が上昇し、接続材９は融点に達し、溶融する。従って、セラミック基板２とベース３との熱膨張係数が大きく異なっていても、接続材９に熱応力が生じることがない。これによって、接続材９に亀裂が生じることなく、放熱性に支障を生じるようなことはない。また、接続材９は、この溶融したときでも、セラミック基板２は、ゲル１０によって覆われ、位置決めされているので、半導体素子１が変動するようなこともないし、外部に流出することもなく、半導体素子１の短絡等は発生しない。
【０００９】
なお、この実施の形態では、液体金属としてガリウム金属を用いたが、勿論このものに限定されるものではなく、融点が１００℃以下の金属であればよく、例えばガリウム合金、Ｎａ、Ｋ、Ｃｓ、Ｒｂ等でもよい。但し、水分が存在した場合の爆発性や毒性を考慮するとガリウムが最も推奨される。
半導体素子１の耐熱上限温度は通常約１２０℃であるが、１００℃以上で溶融する金属を用いた場合、金属が溶融する前に、熱温度分布によっては半導体素子１が熱破損してしまうことがあり、そのため金属の融点は１００℃以下である必要性がある。
また、セラミック基板２は窒化アルミニウムに限るものではなく、アルミナ、窒化珪素などを芯材とする基板であってもよい。また、ベース３も銅に限るものではなく、アルミニウムなどの金属でもよく、あるいは炭化珪素等のセラミックスとの複合材料でも同様の効果が得られることは言うまでもない。
【００１０】
実施の形態２．
図２はこの発明の実施の形態２による半導体装置を示す側断面図であり、この実施の形態では、接続材９と接触する、ベース３の表面およびセラミック基板２の導電膜２ａの表面には、接続材９との間での溶解反応で銅が接続材９に溶けるのを防止する処理膜である酸化膜１１が形成されている。この酸化膜１１は、１５０℃以下の温度において金属と化学反応を生じない処理であり、十分な厚さを得るために予め高温に曝すことで簡単に形成される。その他の構成は実施の形態１と同様である。なお、１５０℃は、半導体素子１の作動時において部分的にも接続材９が達すると想定される上限値である。
【００１１】
この実施の形態の半導体装置では、半導体素子１が作動して発熱した時に接続材９が溶融するので、セラミック基板２とベース３との熱膨張係数差による熱応力が接続材９に発生しない点では実施の形態１と同様である。
また、セラミック基板２の下面の導電膜２ａとベース３の表面に酸化膜１１が存在するため、接続材９のガリウムと、セラミック基板２の導電膜２ａの銅、ベース３の銅とが直接接触することがなく、溶解反応が生じず、接続材９の融点が上昇するようなことはない。さらに、酸化膜１１があるため、セラミック基板２の導電膜２ａおよびベース３の浸食も防止される。
【００１２】
なお、上記実施の形態では、処理膜として酸化膜１１を形成した場合について説明したが、１５０℃以下の温度において金属と化学反応を生じない処理であれば、これに限るものではなく、例えば窒化膜、炭化膜、有機膜などでも同様の効果が得られる。また、酸化膜や窒化膜は、下層金属の酸化物や窒化物に限るものではなく、別の金属の酸化物や窒化物をコーティングしても同様の効果が得られることは言うまでもない。
【００１３】
実施の形態３．
図３はこの発明の実施の形態３による半導体装置を示す側断面図である。
この実施の形態では、ケース４の上に例えばエポキシ樹脂からなる蓋１２が被せられており、この蓋１２、ベース３およびケース４により、ゲル１０が充填された密閉容器を構成している。他の構成は、実施の形態２と同様である。
この実施の形態の半導体装置によれば、セラミック基板２、半導体素子１は、密封容器に内蔵されているので、半導体素子１が作動して発熱した時に接続材９が溶融したり、半導体素子１が作動を終了して温度が低下し、接続材９が凝固した時に、相変化による体積変化を生じるものの、その体積の増減は密閉容器の変形で吸収され、ゲル１０が外部に流出したりすることがない。また、接続材９の体積変化は、ゲル１０によって均一な内圧変化にするため、ケース４や蓋１２の一部が隆起したり陥没したりすることもない。
【００１４】
なお、蓋１２はエポキシ樹脂で構成されているが、接続材９の相変化による体積変化に対応できる強度のある蓋であれば他の樹脂でもよく、また樹脂以外の金属やセラミックであってもよい。
【００１５】
実施の形態４．
図４はこの発明の実施の形態４による半導体装置を示す側断面図である。
この実施の形態では、容器に内部の圧力変動に応じて内体積を変動させ、内部の圧力を一定に保持する体積変動機構である圧力調整弁１３が設けられている。この圧力調整弁１３は、シリンダ１３ａとピストン１３ｂとから構成されている。他の構成は、実施の形態３と同様である。
この実施の形態の半導体装置によれば、半導体素子１が作動して発熱した時に接続材９が溶融したり、半導体素子１が作動を終了して温度が低下して接続材９が凝固した時に、相変化による体積変化を生じ、半導体装置内の圧力が変化しようとしても圧力調整弁１３のピストン１３ｂがシリンダ１３ａ内を移動し、ゲル１０を流動させるため、内圧を一定に保持することができ、セラミック基板２、ベース３と、接続材９との密着性を確保でき、放熱性を安定化させることができる。
【００１６】
なお、体積変動機構として圧力調整弁について説明したが、内部圧力を調整できる機構であれば他の構造でもよく、例えば、蓋が伸縮性を有しており、蓋１２全体が変形する構造であっても同様の効果が得られる。
【００１７】
実施の形態５．
図５はこの発明の実施の形態５による半導体装置を示す側断面図である。
この実施の形態では、密閉容器の内部の上部に大気圧以上の圧力の気体で、例えば２気圧の空気１４が封入されている。その他の構成は、実施の形態３と同様である。
この実施の形態の半導体装置によれば、半導体素子１の作動により発熱して接続材９が溶融し、半導体素子１の作動終了により温度が低下して接続材９が凝固した時に、接続材９は相変化により体積変化が生じるものの、密封された空気１４がその体積変化を吸収し、かつゲル１０を加圧し続けるため、セラミック基板２とベース３との間に挟まれた接続材９は加圧され、セラミック基板２、ベース３と、接続材９との密着性が確保され、優れた放熱性が確保される。
【００１８】
なお、密閉容器内は、大気圧以上の気体が封入されていればよく、空気１４以外の窒素やアルゴン等の不活性ガスでも同様の効果が得られることは言うまでもない。
【００１９】
なお、上記の各実施の形態では、液体金属としてガリウム金属を用いた場合について説明したが、融点が１００℃以下の金属であればよいのであって、半導体素子の非作動時でも液相である金属で、例えば水銀であっても、この発明は適用できる。
【００２０】
【発明の効果】
以上説明したように、この発明の半導体装置によれば、ベースと、このベースに接続材を介して接続された基板と、この基板に搭載された半導体素子とを備え、前記接続材は、前記半導体素子の作動時は液相である液体金属であるので、前記ベースと前記基板との間での熱膨張係数に起因して前記接続材に亀裂が生じるようなことがなく、半導体素子の放熱性が確保される。
【図面の簡単な説明】
【図１】 この発明の実施の形態１による半導体装置の側断面図である。
【図２】 この発明の実施の形態２による半導体装置の側断面図である。
【図３】 この発明の実施の形態３による半導体装置の側断面図である。
【図４】 この発明の実施の形態４による半導体装置の側断面図である。
【図５】 この発明の実施の形態５による半導体装置の側断面図である。
【符号の説明】
１ 半導体素子、２ セラミック基板、３ ベース、４ ケース、９ 接続材、１０ ゲル、１１ 酸化膜（処理膜）、１２ 蓋、１３ 圧力調整弁、１４ 空気。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a base, a substrate connected to the base via a connecting material, and a semiconductor element mounted on the substrate.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a semiconductor device in which a semiconductor chip and a base material are bonded by a solder alloy that is a bonding metal is known (for example, see Patent Document 1).
[0003]
[Patent Document 1]
JP-A-8-264682 (FIG. 11)
[0004]
[Problems to be solved by the invention]
In the conventional semiconductor device, the thermal expansion coefficient of the semiconductor chip and the solder alloy of the joining metal, or the solder alloy and the alumina of the base material are greatly different. Thermal stress is generated at the joint between the semiconductor chip and the base material due to temperature changes in the environment in which it is installed, and this causes cracks in the solder alloy at the joint, thereby creating a heat flow path from the semiconductor chip to the base material. Since it is narrowed, there is a problem that sufficient heat dissipation cannot be obtained, cracks propagate, and eventually the semiconductor device is destroyed.
[0005]
An object of the present invention is to solve the above-mentioned problems, and the crack of the connecting material is caused by the difference in the thermal expansion coefficient between the base and the substrate on which the semiconductor element is mounted. An object is to obtain a semiconductor device which does not cause generation.
[0006]
[Means for Solving the Problems]
A semiconductor device according to the present invention includes a base, a substrate connected to the base via a connecting material, and a semiconductor element mounted on the substrate, and the connecting material is liquid when the semiconductor element is in operation. Ri liquid metal der is a phase, said liquid metal, surrounding is covered with a resin, the outflow of the liquid metal in the liquid phase is prevented by the resin, the resin is a jelly-like gel, the substrate, The semiconductor element is contained in a sealed container, and a pressurized gas that continues to pressurize the resin is sealed in the container, and the connecting material sandwiched between the substrate and the base is added. It comes to be pressed.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
1 is a side sectional view showing a semiconductor device according to Embodiment 1 of the present invention.
This semiconductor device includes a base 3 made of a copper alloy, a ceramic substrate 2 connected to the base 3 via a connecting material 9, a semiconductor element 1 made of Si mounted on the ceramic substrate 2, and the base 3 A case 4 made of an epoxy resin that constitutes the container and a jelly-like gel 10 made of an insulating material such as an inexpensive silicone resin are provided.
The ceramic substrate 2 has a conductive film 2a made of, for example, copper formed on an upper surface and a lower surface, and a core material made of, for example, aluminum nitride. The connecting material 9 is a liquid metal that melts due to heat generated by the operation of the semiconductor element 1 and solidifies when the semiconductor element 1 is not operated. Specifically, the connecting material 9 is made of gallium metal having a melting point of 28 ° C. When the connecting member 9 is in a solid phase, the connecting member 9 is in contact with both surfaces of the conductive film 2 a and the base 3, and movement in the planar direction is restricted by the protruding portion 4 a protruding inwardly on the lower inner surface of the case 4. Yes.
[0008]
In the semiconductor device of the present invention, when the semiconductor element 1 operates and generates heat, the heat is transmitted to the connecting material 9 and the base 3 through the ceramic substrate 2 to increase the temperature of the entire semiconductor device, and the connecting material 9 reaches the melting point. Melt. Therefore, even if the thermal expansion coefficients of the ceramic substrate 2 and the base 3 are greatly different, no thermal stress is generated in the connecting material 9. As a result, the connecting material 9 is not cracked, and heat dissipation is not hindered. Further, even when the connecting material 9 is melted, the ceramic substrate 2 is covered and positioned by the gel 10, so that the semiconductor element 1 does not fluctuate or flow out to the outside. A short circuit or the like of the semiconductor element 1 does not occur.
[0009]
In this embodiment, gallium metal is used as the liquid metal, but it is of course not limited to this, and any metal having a melting point of 100 ° C. or lower may be used. For example, gallium alloy, Na, K, Cs , Rb, etc. However, gallium is most recommended in view of explosiveness and toxicity in the presence of moisture.
The heat-resistant upper limit temperature of the semiconductor element 1 is normally about 120 ° C., but when a metal that melts at 100 ° C. or higher is used, the semiconductor element 1 may be thermally damaged depending on the thermal temperature distribution before the metal melts. Therefore, the melting point of the metal needs to be 100 ° C. or less.
The ceramic substrate 2 is not limited to aluminum nitride, and may be a substrate having alumina, silicon nitride or the like as a core material. Needless to say, the base 3 is not limited to copper, but may be a metal such as aluminum, or a composite material with ceramics such as silicon carbide can provide the same effect.
[0010]
Embodiment 2. FIG.
FIG. 2 is a side sectional view showing a semiconductor device according to the second embodiment of the present invention. In this embodiment, the surface of the base 3 and the surface of the conductive film 2a of the ceramic substrate 2 that are in contact with the connecting material 9 are shown. An oxide film 11 is formed as a treatment film for preventing copper from being dissolved in the connection material 9 by a dissolution reaction with the connection material 9. The oxide film 11 is a process that does not cause a chemical reaction with a metal at a temperature of 150 ° C. or lower, and is easily formed by exposing it to a high temperature in advance in order to obtain a sufficient thickness. Other configurations are the same as those of the first embodiment. Note that 150 ° C. is an upper limit value that is assumed to be partially reached by the connecting material 9 during the operation of the semiconductor element 1.
[0011]
In the semiconductor device of this embodiment, the connection material 9 is melted when the semiconductor element 1 is activated to generate heat, so that thermal stress due to the difference in thermal expansion coefficient between the ceramic substrate 2 and the base 3 does not occur in the connection material 9. Then, it is the same as that of Embodiment 1.
Further, since the conductive film 2a on the lower surface of the ceramic substrate 2 and the oxide film 11 are present on the surface of the base 3, the gallium of the connecting material 9, the copper of the conductive film 2a of the ceramic substrate 2, and the copper of the base 3 are in direct contact. And no melting reaction occurs, and the melting point of the connecting material 9 does not increase. Furthermore, since the oxide film 11 is present, erosion of the conductive film 2a and the base 3 of the ceramic substrate 2 is also prevented.
[0012]
In the above embodiment, the case where the oxide film 11 is formed as the treatment film has been described. However, the treatment is not limited to this as long as the treatment does not cause a chemical reaction with the metal at a temperature of 150 ° C. or lower. The same effect can be obtained with a film, a carbonized film, an organic film, or the like. In addition, the oxide film and the nitride film are not limited to the oxide or nitride of the lower layer metal, and it goes without saying that the same effect can be obtained by coating another metal oxide or nitride.
[0013]
Embodiment 3 FIG.
3 is a side sectional view showing a semiconductor device according to Embodiment 3 of the present invention.
In this embodiment, a lid 12 made of, for example, an epoxy resin is put on the case 4, and the lid 12, the base 3, and the case 4 constitute an airtight container filled with the gel 10. Other configurations are the same as those in the second embodiment.
According to the semiconductor device of this embodiment, since the ceramic substrate 2 and the semiconductor element 1 are contained in the sealed container, the connecting material 9 is melted when the semiconductor element 1 is activated and generates heat, or the semiconductor element 1 When the operation is finished and the temperature is lowered and the connecting material 9 is solidified, the volume change due to the phase change occurs, but the increase or decrease in the volume is absorbed by the deformation of the sealed container, and the gel 10 flows out to the outside. There is nothing. Further, since the volume change of the connecting material 9 is changed to a uniform internal pressure change by the gel 10, the case 4 and a part of the lid 12 do not rise or sink.
[0014]
The lid 12 is made of an epoxy resin, but other resins may be used as long as the lid is strong enough to cope with the volume change caused by the phase change of the connecting material 9, or a metal or ceramic other than the resin may be used. Good.
[0015]
Embodiment 4 FIG.
4 is a side sectional view showing a semiconductor device according to Embodiment 4 of the present invention.
In this embodiment, the container is provided with a pressure regulating valve 13 that is a volume variation mechanism that varies the internal volume according to the internal pressure variation and keeps the internal pressure constant. The pressure regulating valve 13 is composed of a cylinder 13a and a piston 13b. Other configurations are the same as those of the third embodiment.
According to the semiconductor device of this embodiment, when the semiconductor element 1 is activated and generates heat, the connecting material 9 is melted, or when the semiconductor element 1 is deactivated and the temperature is lowered and the connecting material 9 is solidified. Even if the volume change due to the phase change occurs and the pressure in the semiconductor device is about to change, the piston 13b of the pressure regulating valve 13 moves in the cylinder 13a and causes the gel 10 to flow, so that the internal pressure can be kept constant. Adhesion between the ceramic substrate 2 and the base 3 and the connecting material 9 can be ensured, and heat dissipation can be stabilized.
[0016]
Although the pressure adjustment valve has been described as the volume variation mechanism, other structures may be used as long as the internal pressure can be adjusted. For example, the lid has elasticity and the entire lid 12 is deformed. However, the same effect can be obtained.
[0017]
Embodiment 5 FIG.
5 is a side sectional view showing a semiconductor device according to Embodiment 5 of the present invention.
In this embodiment, air 14 having a pressure of atmospheric pressure or higher, for example, 2 atmospheres of air 14 is enclosed in the upper part of the inside of the sealed container. Other configurations are the same as those of the third embodiment.
According to the semiconductor device of this embodiment, when the connection element 9 is melted by the operation of the semiconductor element 1 and the connection material 9 is melted, and the temperature is lowered and the connection material 9 is solidified by the end of the operation of the semiconductor element 1, Although the volume change occurs due to the phase change, the sealed air 14 absorbs the volume change and continues to pressurize the gel 10, so that the connecting material 9 sandwiched between the ceramic substrate 2 and the base 3 is added. As a result, the adhesiveness between the ceramic substrate 2, the base 3, and the connecting material 9 is ensured, and excellent heat dissipation is ensured.
[0018]
It should be noted that the sealed container only needs to be filled with a gas at atmospheric pressure or higher, and it goes without saying that the same effect can be obtained with an inert gas such as nitrogen or argon other than the air 14.
[0019]
In each of the embodiments described above, the case where gallium metal is used as the liquid metal has been described. However, any metal having a melting point of 100 ° C. or lower may be used, and it is in a liquid phase even when the semiconductor element is not operating. Even if it is a metal, for example, mercury, this invention can be applied.
[0020]
【The invention's effect】
As described above, according to the semiconductor device of the present invention, it includes a base, a substrate connected to the base via a connecting material, and a semiconductor element mounted on the substrate, Since the liquid metal is in a liquid phase when the semiconductor element is operated, the connection material is not cracked due to the thermal expansion coefficient between the base and the substrate, and the heat dissipation of the semiconductor element is achieved. Sex is secured.
[Brief description of the drawings]
FIG. 1 is a side sectional view of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a side sectional view of a semiconductor device according to a second embodiment of the present invention.
FIG. 3 is a side sectional view of a semiconductor device according to a third embodiment of the present invention.
FIG. 4 is a side sectional view of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 5 is a side sectional view of a semiconductor device according to a fifth embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor element, 2 Ceramic substrate, 3 Base, 4 Case, 9 Connection material, 10 Gel, 11 Oxide film (treatment film), 12 Lid, 13 Pressure control valve, 14 Air.

Claims (5)

ベースと、このベースに接続材を介して接続された基板と、この基板に搭載された半導体素子とを備えた半導体装置において、
前記接続材は、前記半導体素子の作動時は液相である液体金属であり、
前記液体金属は、周囲が樹脂で覆われ、この樹脂により液相の前記液体金属の流出が防止され、
前記樹脂は、ゼリー状のゲルであり、
前記基板、前記半導体素子は、密封された容器に内蔵され、
前記容器内には、前記樹脂を加圧し続ける加圧気体が封入されて、前記基板と前記ベースとの間に挟まれた前記接続材は加圧されるようになっている
半導体装置。In a semiconductor device comprising a base, a substrate connected to the base via a connecting material, and a semiconductor element mounted on the substrate,
The connecting member is, during operation of the semiconductor device Ri liquid metal der is a liquid phase,
The liquid metal is covered with resin, and the resin prevents the liquid metal from flowing out of the liquid phase.
The resin is a jelly-like gel,
The substrate and the semiconductor element are embedded in a sealed container,
A pressurized gas that continues to pressurize the resin is sealed in the container, and the connecting material sandwiched between the substrate and the base is pressurized. Semiconductor apparatus. 前記接続材は、前記半導体素子の非作動時には凝固する液体金属である請求項１に記載の半導体装置。  The semiconductor device according to claim 1, wherein the connecting material is a liquid metal that solidifies when the semiconductor element is not operated. 前記液体金属は、ガリウムまたはその合金である請求項１または２に記載の半導体装置。The liquid metal, a semiconductor device according to claim 1 or 2 is gallium or an alloy thereof. 前記液体金属と接触する、前記ベースおよび前記基板の両面の金属被膜には、前記液体金属との間で溶解反応が生じるのを防止する処理膜が形成されている請求項１ないし請求項３の何れかに記載の半導体装置。Contacting the liquid metal, wherein the base and both sides of the metal coating of the substrate, of claims 1 to 3 treatment film to prevent the dissolution reaction occurs is formed between the liquid metal A semiconductor device according to any one of the above. 前記処理膜は、酸化膜、窒化膜、炭化膜および有機膜の何れかの一つである請求項４に記載の半導体装置。The semiconductor device according to claim 4 , wherein the treatment film is one of an oxide film, a nitride film, a carbonized film, and an organic film.
JP2003105225A 2003-04-09 2003-04-09 Semiconductor device Expired - Fee Related JP4266689B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003105225A JP4266689B2 (en) 2003-04-09 2003-04-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003105225A JP4266689B2 (en) 2003-04-09 2003-04-09 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2004311820A JP2004311820A (en) 2004-11-04
JP4266689B2 true JP4266689B2 (en) 2009-05-20

Family

ID=33467802

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003105225A Expired - Fee Related JP4266689B2 (en) 2003-04-09 2003-04-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JP4266689B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102019206896A1 (en) * 2019-05-13 2020-11-19 Siemens Aktiengesellschaft Improvements in power semiconductor components on heat pipes

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60111446A (en) * 1983-11-21 1985-06-17 Toshiba Corp Semiconductor device
JPH07135279A (en) * 1993-06-30 1995-05-23 Sony Corp Method for packaging multichip module and multichip module package
JPH08213521A (en) * 1995-02-06 1996-08-20 Shin Etsu Polymer Co Ltd Cooling structure of semiconductor device
JP2002203942A (en) * 2000-12-28 2002-07-19 Fuji Electric Co Ltd Power semiconductor module
JP2003068979A (en) * 2001-08-28 2003-03-07 Hitachi Ltd Semiconductor device

Also Published As

Publication number Publication date
JP2004311820A (en) 2004-11-04

Similar Documents

Publication Publication Date Title
TW201535631A (en) Semi-conductor module with an encapsulating mass that covers a semi-conductor component
JP2005354095A (en) Device for packing electronic components using injection moulding technology
US20210193546A1 (en) Packaging of a semiconductor device with dual sealing materials
JPH07211832A (en) Power radiating device and manufacture thereof
WO2018092251A1 (en) Semiconductor package
JP2009514240A (en) Method for joining electronic components
CN106847781A (en) Power module package and its manufacture method
US7196417B2 (en) Method of manufacturing a low expansion material and semiconductor device using the low expansion material
JP4757880B2 (en) Method for manufacturing electronic component, method for manufacturing heat conductive member, and method for mounting heat conductive member for electronic component
JP4266689B2 (en) Semiconductor device
JP2006202936A (en) Semiconductor device
US5465481A (en) Method for fabricating a semiconductor package
JP4354377B2 (en) Semiconductor device
JP2004363183A (en) Heat dissipating structure of electronic part
JPH0432251A (en) Semiconductor package and manufacture thereof
US20220077011A1 (en) Package, and method for manufacturing power semiconductor module
JP2004146392A (en) Package for housing semiconductor element and semiconductor device
JP2006013420A (en) Package for electronic component housing, and electronic device
JPS63226031A (en) Manufacture of compound structure
JPH09219473A (en) Package having electronic component cooling structure and manufacture thereof
JP7124637B2 (en) semiconductor equipment
WO2024053699A1 (en) Electronic device and manufacturing method for electronic device
JP2002184907A (en) Semiconductor device for power
JP2006128589A (en) Electronic component housing package and electronic device
JP2008004760A (en) Wiring board and electronic device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20051102

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080123

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080708

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080904

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090217

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090217

R150 Certificate of patent or registration of utility model

Ref document number: 4266689

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120227

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130227

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130227

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140227

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees