JP2006202936A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2006202936A
JP2006202936A JP2005012280A JP2005012280A JP2006202936A JP 2006202936 A JP2006202936 A JP 2006202936A JP 2005012280 A JP2005012280 A JP 2005012280A JP 2005012280 A JP2005012280 A JP 2005012280A JP 2006202936 A JP2006202936 A JP 2006202936A
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semiconductor chip
corner
semiconductor device
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Seiki Hiramatsu
星紀 平松
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
    • H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique capable of improving a semiconductor device in reliability. <P>SOLUTION: Adhesion reinforcing projections 1 are provided on a base board 5 where a semiconductor chip 3 is mounted. A coating material 2 is provided on the base board 5 covering the adhesion reinforcing projections 1 and the semiconductor chip 3. The coating material 2 has a lower elastic modulus than the adhesion reinforcing projections 1, the semiconductor chip 3, and the base board 5. A sealing resin 4 is formed to cover and seal up the coating material 2 and the base board 5. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、ベース板に搭載された半導体チップを覆ってコーティング材が設けられた半導体装置に関する。   The present invention relates to a semiconductor device in which a coating material is provided so as to cover a semiconductor chip mounted on a base plate.

ハイブリッド自動車、電気鉄道をはじめ洗濯機、冷蔵庫、エアコンディショナーなどに使用されるインバータモジュールでは、高付加価値化や低コスト化の観点から小型化、高効率化、高機能化へ向けた開発が精力的に行われている。インバータモジュールは、半導体チップ、当該半導体チップを搭載するベース板、ワイヤ、電極、封止材などの部品から成り、近年では小型化のために複数の半導体チップをモジュール内に搭載するマルチチップモジュール化や、ＳｉＣ（炭化シリコン）チップのようにＳｉチップに比べて絶縁性が高く装置を小型化できる半導体チップを使用する検討が進んでいる。このような開発が進めばモジュール内は半導体チップの発熱によって高温化が加速するため、高温時の信頼性を確保できるモジュール構造が必要となる。   Inverter modules used in washing machines, refrigerators, air conditioners, as well as hybrid vehicles, electric railways, etc., are energetically developing for miniaturization, high efficiency, and high functionality from the viewpoint of high added value and low cost Has been done. Inverter modules consist of components such as semiconductor chips, base plates on which the semiconductor chips are mounted, wires, electrodes, and sealing materials. In recent years, inverter modules have become multi-chip modules in which multiple semiconductor chips are mounted in modules. In addition, studies are underway to use a semiconductor chip, such as a SiC (silicon carbide) chip, which has higher insulation than a Si chip and can reduce the size of the device. If such development progresses, the temperature inside the module will accelerate due to the heat generated by the semiconductor chip, so a module structure that can ensure reliability at high temperatures is required.

このような要求に対して、例えば特許文献１では、半導体チップの周囲をコーティングする技術が提案されている。この技術では、高温時の振動や衝撃から半導体装置での結線を保護し、当該半導体装置の信頼性を向上させている。   In response to such a demand, for example, Patent Document 1 proposes a technique for coating the periphery of a semiconductor chip. In this technique, the connection in the semiconductor device is protected from vibration and shock at high temperatures, and the reliability of the semiconductor device is improved.

なお、特許文献２にも半導体装置の信頼性の向上を図る技術が提案されている。   Patent Document 2 also proposes a technique for improving the reliability of a semiconductor device.

特開２００２−１９８４７１号公報JP 2002-198471 A 特開平１０−６５０６２号公報Japanese Patent Laid-Open No. 10-65062

さて、特許文献１に記載の技術では、装置が高温化すると、半導体チップをコーティングするコーティング材に発生する熱応力によって、当該コーティング材がベース板から剥離することがある。また、半導体装置内の各部品を封止する封止樹脂においては、装置の高温化によって熱劣化が生じることがある。その結果、半導体装置の信頼性が低下するという問題が生じる。   In the technique described in Patent Document 1, when the temperature of the apparatus increases, the coating material may be peeled off from the base plate due to thermal stress generated in the coating material that coats the semiconductor chip. In addition, in the sealing resin that seals each component in the semiconductor device, thermal degradation may occur due to the high temperature of the device. As a result, there arises a problem that the reliability of the semiconductor device is lowered.

そこで、本発明は上記点に鑑みて成されたものであり、半導体装置の信頼性を向上させることが可能な技術を提供することを目的とする。   Therefore, the present invention has been made in view of the above points, and an object thereof is to provide a technique capable of improving the reliability of a semiconductor device.

この発明の第１の半導体装置は、半導体チップと、前記半導体チップを搭載するベース板と、前記ベース板上に設けられた凸部と、前記凸及び前記半導体チップを覆って前記ベース板上に設けられた、前記ベース板、前記凸部及び前記半導体チップよりも弾性率の低いコーティング材とを備える。   A first semiconductor device according to the present invention includes a semiconductor chip, a base plate on which the semiconductor chip is mounted, a convex portion provided on the base plate, and the convex and the semiconductor chip so as to cover the base plate. The base plate, the convex portion, and the coating material having a lower elastic modulus than the semiconductor chip are provided.

また、この発明の第２の半導体装置は、半導体チップと、前記半導体チップを搭載するベース板と、前記半導体チップを覆って前記ベース板上に設けられたコーティング材と、前記コーティング材と前記ベース板とを覆う封止樹脂とを備え、前記コーティング材の熱伝導率は前記封止樹脂よりも低い。   A second semiconductor device of the present invention includes a semiconductor chip, a base plate on which the semiconductor chip is mounted, a coating material that covers the semiconductor chip and is provided on the base plate, the coating material, and the base A sealing resin covering the plate, and the thermal conductivity of the coating material is lower than that of the sealing resin.

この発明の第１の半導体装置によれば、コーティング材が、それよりも弾性率の高い凸部を覆うため、当該凸部の表面積の分、当該コーティング材とその他の弾性率が高い材料との接触面積が増加する。従って、コーティング材がベース板から剥がれ難くなり、その結果、本半導体装置の信頼性が向上する。   According to the first semiconductor device of the present invention, since the coating material covers the convex portion having a higher elastic modulus, the coating material and other materials having a high elastic modulus are equivalent to the surface area of the convex portion. The contact area increases. Therefore, the coating material is difficult to peel off from the base plate, and as a result, the reliability of the semiconductor device is improved.

また、この発明の第２の半導体装置によれば、コーティング材の熱伝導率が封止樹脂よりも低いため、半導体チップで発生した熱が封止樹脂に伝導しにくくなる。その結果、封止樹脂で発生する熱応力を低減でき、当該封止樹脂の熱劣化を抑制できる。従って、本半導体装置の信頼性が向上する。   In addition, according to the second semiconductor device of the present invention, since the thermal conductivity of the coating material is lower than that of the sealing resin, the heat generated in the semiconductor chip is hardly conducted to the sealing resin. As a result, thermal stress generated in the sealing resin can be reduced, and thermal degradation of the sealing resin can be suppressed. Therefore, the reliability of the semiconductor device is improved.

実施の形態１．
図１は本発明の実施の形態１に係る半導体装置の構造を示す断面図である。本実施の形態１に係る半導体装置は、例えば、ハイブリッド自動車や冷蔵庫などに使用されるインバータモジュールである。図１に示されるように、本実施の形態１に係る半導体装置は、ベース板５と、ベース板５上に搭載された複数の半導体チップ３と、複数の電極７と、半導体チップ３間、あるいは半導体チップ３と電極７との間を接続する複数のワイヤ６とを備えている。 Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 1 of the present invention. The semiconductor device according to the first embodiment is an inverter module used in, for example, a hybrid vehicle or a refrigerator. As shown in FIG. 1, the semiconductor device according to the first embodiment includes a base plate 5, a plurality of semiconductor chips 3 mounted on the base plate 5, a plurality of electrodes 7, and between the semiconductor chips 3. Alternatively, a plurality of wires 6 for connecting the semiconductor chip 3 and the electrodes 7 are provided.

ベース板５上には、各半導体チップ３の周辺に接着補強凸部１が複数設けられている。そして、ベース板５上には半導体チップ３ごとにコーティング材２が設けられており、当該コーティング材２は、対応する半導体チップ３とその周辺の複数の接着補強凸部１とを覆って形成されている。   On the base plate 5, a plurality of adhesion reinforcing convex portions 1 are provided around each semiconductor chip 3. A coating material 2 is provided for each semiconductor chip 3 on the base plate 5, and the coating material 2 is formed so as to cover the corresponding semiconductor chip 3 and the plurality of adhesion reinforcing convex portions 1 around it. ing.

また、ベース板５の底面には例えばセラミック板から成る絶縁性高熱伝導材８が設けられており、当該絶縁性高熱伝導材８には図示しないヒートシンクが取り付けられる。そして、ベース板５と、ワイヤ６と、電極７と、コーティング材２とを覆って封止する封止樹脂４が設けられている。   An insulating high heat conductive material 8 made of, for example, a ceramic plate is provided on the bottom surface of the base plate 5, and a heat sink (not shown) is attached to the insulating high heat conductive material 8. And the sealing resin 4 which covers and seals the base plate 5, the wire 6, the electrode 7, and the coating material 2 is provided.

半導体チップ３は、例えばやや平たい直方体形状のシリコンチップであって、コーティング材２よりも弾性率が高い。半導体チップ３には、ＭＯＳトランジスタやダイオードなどが形成されている。半導体チップ３としては、ＧａＡｓ（ガリウム砒素）、ＩｎＰ（インジウムリン）、ＳｉＣ（炭化シリコン）などから成る半導体チップを用いても良い。   The semiconductor chip 3 is, for example, a slightly flat rectangular parallelepiped silicon chip and has a higher elastic modulus than the coating material 2. On the semiconductor chip 3, MOS transistors, diodes, and the like are formed. As the semiconductor chip 3, a semiconductor chip made of GaAs (gallium arsenide), InP (indium phosphide), SiC (silicon carbide), or the like may be used.

半導体チップ３は、例えば、ＡｕＳｎ（金−錫）半田やＡｇＳｎ（銀−錫）半田などの金属融解物を用いてベース板５上に固定される。半導体チップ３とベース板５とは、銀ペーストなどの熱伝導率と電気的導電性が良好な接合材を用いて接合しても良い。   The semiconductor chip 3 is fixed on the base plate 5 using, for example, a metal melt such as AuSn (gold-tin) solder or AgSn (silver-tin) solder. The semiconductor chip 3 and the base plate 5 may be bonded using a bonding material having good thermal conductivity and electrical conductivity such as silver paste.

電極７は、例えばニッケルメッキが施された銅から成る。電極７は、十分な電気導電性を有する材料であればその他の材料で形成しても良い。電極７には、半導体チップ３で発生した信号がワイヤ６を介して伝達され、当該信号は本半導体装置の外部に出力される。また、本半導体装置の外部から信号が電極７に入力されると、当該信号は、ワイヤ６を介して半導体チップ３に入力される。   The electrode 7 is made of, for example, copper plated with nickel. The electrode 7 may be formed of other materials as long as the material has sufficient electrical conductivity. A signal generated in the semiconductor chip 3 is transmitted to the electrode 7 through the wire 6, and the signal is output to the outside of the semiconductor device. Further, when a signal is input to the electrode 7 from the outside of the semiconductor device, the signal is input to the semiconductor chip 3 through the wire 6.

ワイヤ６は例えばアルミニウムから成る。ワイヤ６は、金などの他の金属から形成しても良い。また、本半導体装置で消費される電力量によって、所定の径のワイヤ６を複数本使用して半導体チップ３間、あるいは電極７と半導体チップ３との間を接続しても良い。   The wire 6 is made of aluminum, for example. The wire 6 may be formed from other metals such as gold. Further, depending on the amount of power consumed by the semiconductor device, a plurality of wires 6 having a predetermined diameter may be used to connect the semiconductor chips 3 or between the electrodes 7 and the semiconductor chip 3.

コーティング材２は、半導体チップ３とワイヤ６との接続箇所等を保護するために設けられたものである。コーティング材２は、例えば、JIS K 6253試験規格においてゴム硬度３５（弾性率を示すヤング率は約０．２Ｍｐａ）であって、熱伝導率が０．３Ｗ／ｍ・ｋのシリコーン樹脂から形成されており、接着補強凸部１及びベース板５よりも弾性率が低く、封止樹脂４よりも熱伝導率が低い。コーティング材２は、シリコーン樹脂以外にも、エポキシ樹脂、ポリイミド樹脂、ウレタン樹脂などで形成しても良く、コーティング材２の材料は、接着補強凸部１、ベース板５及び半導体チップ３よりも弾性率が低く、かつ封止樹脂４よりも熱伝導率が低い、接着補強凸部１やベース板５と接着できる材料であれば良い。   The coating material 2 is provided to protect the connection portion between the semiconductor chip 3 and the wire 6 and the like. The coating material 2 is formed of, for example, a silicone resin having a rubber hardness of 35 (Young's modulus indicating an elastic modulus is approximately 0.2 Mpa) in the JIS K 6253 test standard and having a thermal conductivity of 0.3 W / m · k. The elastic modulus is lower than that of the adhesion reinforcing convex portion 1 and the base plate 5, and the thermal conductivity is lower than that of the sealing resin 4. The coating material 2 may be formed of an epoxy resin, a polyimide resin, a urethane resin, or the like other than the silicone resin, and the material of the coating material 2 is more elastic than the adhesion reinforcing convex portion 1, the base plate 5, and the semiconductor chip 3. Any material can be used as long as it has a low rate and a thermal conductivity lower than that of the sealing resin 4 and can be bonded to the adhesion reinforcing convex portion 1 and the base plate 5.

封止樹脂４は、例えば、熱伝導率が２．０Ｗ／ｍ・ｋのエポキシ樹脂から形成されている。封止樹脂４は、エポキシ樹脂以外にも、シリコーン樹脂、ポリイミド樹脂、ウレタン樹脂などで形成しても良く、封止樹脂４の材料は、コーティング材２よりも熱伝導率が高く、ベース板５やコーティング材２などと接着できる材料であれば良い。   The sealing resin 4 is made of, for example, an epoxy resin having a thermal conductivity of 2.0 W / m · k. The sealing resin 4 may be formed of a silicone resin, a polyimide resin, a urethane resin, or the like other than the epoxy resin. The material of the sealing resin 4 has a higher thermal conductivity than the coating material 2, and the base plate 5 Any material that can be bonded to the coating material 2 or the like may be used.

接着補強凸部１は、コーティング材２よりもヤング率の高い樹脂で形成されている。接着補強凸部１は、例えば、充填材を添加したシリコーン樹脂（ヤング率は０．６Ｍｐａ）で形成されるが、エポキシ樹脂、ポリイミド樹脂、ウレタン樹脂などで形成しても良く、接着補強凸部１の材料は、コーティング材２よりもヤング率が高く、ベース板５と接着できるものであれば良い。   The adhesion reinforcing convex portion 1 is formed of a resin having a higher Young's modulus than the coating material 2. The adhesion reinforcing convex part 1 is formed of, for example, a silicone resin to which a filler is added (Young's modulus is 0.6 Mpa), but may be formed of an epoxy resin, a polyimide resin, a urethane resin, or the like. The material 1 may have any Young's modulus higher than that of the coating material 2 and can be bonded to the base plate 5.

コーティング材２、封止樹脂４、あるいは接着補強凸部１では、材料コストの観点から有機樹脂を使用するのが好ましいが、それ以外に、シラザンやアルミノキサンなどの無機系の樹脂や、ガラス、セラミック前駆体などを用いても良い。   In the coating material 2, the sealing resin 4, or the adhesion reinforcing convex portion 1, it is preferable to use an organic resin from the viewpoint of material cost, but other than that, inorganic resins such as silazane and aluminoxane, glass, ceramics, etc. A precursor or the like may be used.

また、コーティング材２、封止樹脂４、あるいは接着補強凸部１では、ヤング率と熱伝導率とを調節するために樹脂に充填材が添加される。この充填材としては、充填性の観点からシリカ粉末が好ましいが、それ以外にも、アルミナ、窒化アルミ、窒化珪素、窒化ホウ素などの粉末を樹脂等に添加しても良い。   In the coating material 2, the sealing resin 4, or the adhesion reinforcing convex portion 1, a filler is added to the resin in order to adjust the Young's modulus and the thermal conductivity. As the filler, silica powder is preferable from the viewpoint of fillability, but in addition, powders such as alumina, aluminum nitride, silicon nitride, and boron nitride may be added to the resin or the like.

また充填材の形状は、添加量の観点からは球状が好ましいが、樹脂に充填できる形状ならば、破砕状、燐片状、中空状などでも良い。また当該充填材の大きさは、充填性の観点から１０μｍ程度が好ましいが、コーティング材２のヤング率と熱伝導率が調節できる大きさであればそれ以外の大きさでも構わない。   The shape of the filler is preferably spherical from the viewpoint of the amount added, but may be crushed, flake-shaped, hollow or the like as long as it can be filled into the resin. Further, the size of the filler is preferably about 10 μm from the viewpoint of filling properties, but may be other sizes as long as the Young's modulus and thermal conductivity of the coating material 2 can be adjusted.

ベース板５は、コーティング材２及び接着補強凸部１よりも弾性率が高く、熱伝導率などの観点から銅で形成されるのが好ましいが、モリブデン（Ｍｏ）やアルミニウム（Ａｌ）などから成る金属板で形成しても良く、炭化ケイ素アルミニウム（ＳｉＣＡｌ）などの合金で形成しても良い。また、ベース板５の上面にニッケルや金などのメッキを行っても良い。ベース板５の材料としては、熱伝導率などの観点からは、半導体チップ３を搭載でき、かつ当該半導体チップ３の発熱を効率よく伝達する材料であれば構わない。   The base plate 5 has a higher elastic modulus than the coating material 2 and the adhesion reinforcing convex portion 1, and is preferably made of copper from the viewpoint of thermal conductivity, but is made of molybdenum (Mo), aluminum (Al), or the like. You may form with a metal plate and you may form with alloys, such as silicon carbide aluminum (SiCAl). Further, the upper surface of the base plate 5 may be plated with nickel or gold. The material of the base plate 5 may be any material that can mount the semiconductor chip 3 and efficiently transmit the heat generated by the semiconductor chip 3 from the viewpoint of thermal conductivity and the like.

またベース板５は、加工性の観点からは、金属以外の材料、例えば、窒化アルミニウム、シリカ、アルミナなどから成るセラミック板や、有機樹脂を使用したプリント基板で形成しても良く、当該セラミック板や当該プリント基板上には、銅、アルミ、金などのから成る金属配線を施しても良い。   From the viewpoint of workability, the base plate 5 may be formed of a material other than metal, for example, a ceramic plate made of aluminum nitride, silica, alumina, or the like, or a printed board using an organic resin. Alternatively, metal wiring made of copper, aluminum, gold, or the like may be provided on the printed board.

以上のように、本実施の形態１に係る半導体装置では、コーティング材２が、それよりも弾性率の高い接着補強凸部１を覆うため、当該接着補強凸部１の表面積の分、当該コーティング材２とその他の弾性率が高い材料との接触面積が増加する。従って、コーティング材２がベース板５から剥がれ難くなり、本半導体装置の信頼性が向上する。   As described above, in the semiconductor device according to the first embodiment, since the coating material 2 covers the adhesive reinforcing convex portion 1 having a higher elastic modulus than that, the surface area of the adhesive reinforcing convex portion 1 corresponds to the coating. The contact area between the material 2 and other materials having a high elastic modulus increases. Accordingly, the coating material 2 is hardly peeled off from the base plate 5 and the reliability of the semiconductor device is improved.

また、本実施の形態１では、コーティング材２の熱伝導率が封止樹脂４よりも低いため、半導体チップ３で発生した熱が封止樹脂４に伝導しにくくなる。その結果、封止樹脂４で発生する熱応力を低減でき、当該封止樹脂４の熱劣化を抑制できる。従って、本半導体装置の信頼性が向上する。   In the first embodiment, since the thermal conductivity of the coating material 2 is lower than that of the sealing resin 4, it is difficult for heat generated in the semiconductor chip 3 to be conducted to the sealing resin 4. As a result, thermal stress generated in the sealing resin 4 can be reduced, and thermal degradation of the sealing resin 4 can be suppressed. Therefore, the reliability of the semiconductor device is improved.

また、本実施の形態１では、接着補強凸部１が樹脂から形成されているため、ベース板５の任意の位置に当該接着補強凸部１を形成しやすくなる。その結果、半導体チップ３の大きさに応じて接着補強凸部１の形成位置を容易に変更することができ、複数種類の半導体装置を容易に製造することができる。その結果、製造効率が向上する。更に、接着補強凸部１に関して、コーティング材２の材質に応じた材料選定が行いやすくなり、接着補強凸部１の設計自由度が向上する。   Further, in the first embodiment, since the adhesion reinforcing convex portion 1 is made of resin, it becomes easy to form the adhesive reinforcing convex portion 1 at an arbitrary position of the base plate 5. As a result, the formation position of the adhesion reinforcing convex portion 1 can be easily changed according to the size of the semiconductor chip 3, and a plurality of types of semiconductor devices can be easily manufactured. As a result, manufacturing efficiency is improved. Furthermore, regarding the adhesion reinforcing convex portion 1, it becomes easy to select a material according to the material of the coating material 2, and the design freedom of the adhesive reinforcing convex portion 1 is improved.

なお、本実施の形態１では、ベース板５上には半導体チップ３が１層しか形成されていないが、図２に示されるように、例えばスイッチング機能を有する複数の半導体チップ３を上下方向に重ねて積層しても良い。   In the first embodiment, only one layer of the semiconductor chip 3 is formed on the base plate 5. However, as shown in FIG. 2, for example, a plurality of semiconductor chips 3 having a switching function are vertically arranged. You may pile up.

また、図３に示されるように、図１に示される、半導体チップ３、ベース板５、ワイヤ６、電極７及び絶縁性高熱伝導材８から成る組みを２組設けて、一方の組みにおける半導体チップ３と、他方の組みに置ける半導体チップ３とが互いに対向するように配置し、それらの互いに対向する半導体チップ３をコーティング材２で覆いつつ、それらの組みの間を封止樹脂４で充填することによって、複数の半導体チップ３を上下方向に離して積層しても良い。   Further, as shown in FIG. 3, two sets of the semiconductor chip 3, the base plate 5, the wire 6, the electrode 7, and the insulating high heat conductive material 8 shown in FIG. The chip 3 and the semiconductor chip 3 placed in the other set are arranged so as to face each other, the semiconductor chip 3 facing each other is covered with the coating material 2, and the space between these sets is filled with the sealing resin 4 By doing so, a plurality of semiconductor chips 3 may be stacked apart in the vertical direction.

また、上述の図１では、半導体チップ３が横方向に２個並べられた半導体装置の断面図を示しているが、半導体チップ３は横方向に３個以上並べてベース板５上に搭載しても良い。   1 shows a cross-sectional view of a semiconductor device in which two semiconductor chips 3 are arranged in the horizontal direction. Three or more semiconductor chips 3 are arranged on the base plate 5 in the horizontal direction. Also good.

また、本実施の形態１では、電極７と半導体チップ３との電気的接続はワイヤ６で行っていたが、図４に示されるように、ワイヤ６及び電極７の替わりに、片面にバンプ１０が形成された圧接電極９とバネ材１１を設けて、当該バネ材１１によって圧接電極９上のバンプ１０を半導体チップ３に圧接することにより、半導体チップ３で発生する電気信号を外部に取り出したり、外部からの電気信号を半導体チップ３に入力しても良い。   In the first embodiment, the electrode 7 and the semiconductor chip 3 are electrically connected by the wire 6. However, as shown in FIG. 4, the bump 10 is provided on one side instead of the wire 6 and the electrode 7. The pressure contact electrode 9 and the spring material 11 are provided, and the bump 10 on the pressure contact electrode 9 is pressed against the semiconductor chip 3 by the spring material 11 so that an electrical signal generated in the semiconductor chip 3 is taken out to the outside. An external electrical signal may be input to the semiconductor chip 3.

また、図５に示されるように、図３の装置において、ワイヤ６及び電極７の替わりに、両面にバンプ１０が形成された圧接電極９とバネ材１１を設けて、当該バネ材１１によって、圧接電極９の上面上のバンプ１０を上側の半導体チップ３に圧接するとともに、圧接電極９の下面上のバンプ１０を下側の半導体チップ３に圧接することにより、半導体チップ３で発生する電気信号を外部に取り出したり、外部からの電気信号を半導体チップ３に入力しても良い。   Further, as shown in FIG. 5, in the apparatus of FIG. 3, instead of the wire 6 and the electrode 7, a pressure contact electrode 9 having a bump 10 formed on both surfaces and a spring material 11 are provided. The bump 10 on the upper surface of the pressure contact electrode 9 is pressed against the upper semiconductor chip 3, and the bump 10 on the lower surface of the pressure contact electrode 9 is pressed against the lower semiconductor chip 3, thereby generating an electrical signal generated in the semiconductor chip 3. May be taken out or an electric signal from the outside may be input to the semiconductor chip 3.

なお図４の装置では、バネ材１１の一端は圧接電極９のバンプ１０とは反対側の面と接触していることから、当該バネ材１１の伸長力により圧接電極９が半導体チップ３に圧接されている。また図５の装置では、バネ材１１は上下のベース板５の間で狭持されていることから、当該バネ材１１の収縮力により圧接電極９が半導体チップ３に圧接されている。   In the apparatus of FIG. 4, one end of the spring material 11 is in contact with the surface of the pressure contact electrode 9 opposite to the bump 10, so that the pressure contact electrode 9 is in pressure contact with the semiconductor chip 3 by the extension force of the spring material 11. Has been. In the apparatus of FIG. 5, since the spring material 11 is held between the upper and lower base plates 5, the press contact electrode 9 is pressed against the semiconductor chip 3 by the contraction force of the spring material 11.

実施の形態２．
図６は本発明の実施の形態２に係る半導体装置の構造を示す平面図である。本実施の形態２では、実施の形態１では特定されていなかった、接着補強凸部１の形状、個数及び配置位置を特定する。なお図６では、説明の便宜上、封止樹脂４、ワイヤ６及び電極７の記載を省略し、コーティング材２の輪郭を破線で示している。 Embodiment 2. FIG.
FIG. 6 is a plan view showing the structure of the semiconductor device according to the second embodiment of the present invention. In the second embodiment, the shape, number, and arrangement position of the adhesion reinforcing convex portions 1 that are not specified in the first embodiment are specified. In FIG. 6, for convenience of explanation, description of the sealing resin 4, the wire 6, and the electrode 7 is omitted, and the outline of the coating material 2 is indicated by a broken line.

図６に示されるように、本実施の形態２に係る接着補強凸部１は、一つの半導体チップ３に対して４つ設けられている。そして、平面視上において、４つの接着補強凸部１は、半導体チップ３が有する４つの角３ａと一対一で対向するように配置されている。ここで、角３ａは半導体チップ３における上面と互いに繋がる２つの側面とが成す角であって、平面視上においては、互いに繋がる２つのチップ辺３ｂが成す角である。   As shown in FIG. 6, four adhesive reinforcing convex portions 1 according to the second embodiment are provided for one semiconductor chip 3. In plan view, the four adhesion reinforcing convex portions 1 are arranged so as to face the four corners 3 a of the semiconductor chip 3 on a one-to-one basis. Here, the corner 3a is an angle formed by the upper surface of the semiconductor chip 3 and two side surfaces connected to each other, and is an angle formed by two chip sides 3b connected to each other in plan view.

また、断面視上の接着補強凸部１の形状は、図１に示されるように半球状であって、平面視上の接着補強凸部１の形状は、図６に示されるように、半導体チップ３の角３ａとは離れる方向に突出する円弧状となっている。本実施の形態２に係る半導体装置のその他の構造については、実施の形態１に係る半導体装置と同様である。   Further, the shape of the adhesion reinforcing convex portion 1 in the sectional view is hemispherical as shown in FIG. 1, and the shape of the adhesive reinforcing convex portion 1 in the plan view is the semiconductor as shown in FIG. The tip 3 has an arc shape protruding in a direction away from the corner 3a. Other structures of the semiconductor device according to the second embodiment are the same as those of the semiconductor device according to the first embodiment.

このように、本実施の形態２に係る半導体装置では、コーティング材２よりも弾性率が高く円弧状を成す接着補強凸部１が半導体チップ３の角３ａと対向するように配置されている。通常、コーティング材２に発生する熱応力は、半導体チップ３の角３ａ付近に集中するため、本実施の形態２のように、コーティング材２よりも弾性率が高く円弧状の接着補強凸部１を半導体チップ３の角３ａと対向するように配置することによって、当該熱応力を接着補強凸部１によって効率的に分散できる。従って、コーティング材２がベース板５から剥がれにくくなり、本半導体装置の信頼性が向上する。   As described above, in the semiconductor device according to the second embodiment, the adhesive reinforcing convex portion 1 having a higher elastic modulus than the coating material 2 and having an arc shape is arranged so as to face the corner 3 a of the semiconductor chip 3. Usually, the thermal stress generated in the coating material 2 is concentrated in the vicinity of the corner 3a of the semiconductor chip 3, and therefore, the arc-shaped adhesion reinforcing convex portion 1 having a higher elastic modulus than the coating material 2 as in the second embodiment. Is disposed so as to face the corner 3 a of the semiconductor chip 3, so that the thermal stress can be efficiently dispersed by the adhesion reinforcing convex portion 1. Therefore, the coating material 2 is difficult to peel off from the base plate 5, and the reliability of the semiconductor device is improved.

なお、本実施の形態２では、接着補強凸部１は半導体チップ３の各々の角３ａに合計４つ設けていたが、必要な角３ａにのみ当該接着補強凸部１を設けてもよい。   In the second embodiment, a total of four adhesion reinforcing convex portions 1 are provided at each corner 3a of the semiconductor chip 3. However, the adhesive reinforcing convex portions 1 may be provided only at the necessary corner 3a.

また、本実施の形態２では、接着補強凸部１を１重の円弧状に作製したが、図７に示されるように、多重に接着補強凸部１を設けても良い。この場合には、コーティング材２の熱応力を更に効率良く分散できる。   In the second embodiment, the adhesive reinforcing convex portion 1 is formed in a single arc shape. However, as shown in FIG. 7, the adhesive reinforcing convex portion 1 may be provided in multiple layers. In this case, the thermal stress of the coating material 2 can be more efficiently dispersed.

また、接着補強凸部１は、ディスペンサから樹脂をベース板５上に円弧状に塗出し、塗出後の樹脂を熱硬化させることによって形成することができるが、金型成型、転写、リソグラフィなどの方法を使用して形成しても良い。   In addition, the adhesive reinforcing convex portion 1 can be formed by applying a resin from the dispenser in a circular arc shape on the base plate 5 and thermally curing the resin after the application, such as mold molding, transfer, lithography, etc. It may be formed using the method.

実施の形態３．
図８は本発明の実施の形態３に係る半導体装置の構造を拡大して示す部分平面図であって、図９は当該半導体装置の構造を拡大して示す部分断面図である。本実施の形態３に係る半導体装置は、上述の実施の形態２に係る半導体装置において、接着補強凸部１の形状及び配置位置を更に特定したものである。なお、図８では半導体チップ３と接着補強凸部１だけを拡大して示しており、図９では封止樹脂４、ワイヤ６及び電極７の記載を省略している。 Embodiment 3 FIG.
FIG. 8 is an enlarged partial plan view showing the structure of the semiconductor device according to the third embodiment of the present invention. FIG. 9 is an enlarged partial sectional view showing the structure of the semiconductor device. The semiconductor device according to the third embodiment is obtained by further specifying the shape and arrangement position of the adhesion reinforcing convex portion 1 in the semiconductor device according to the second embodiment described above. In FIG. 8, only the semiconductor chip 3 and the adhesion reinforcing convex portion 1 are shown in an enlarged manner, and in FIG. 9, the sealing resin 4, the wire 6 and the electrode 7 are not shown.

図８に示されるように、本実施の形態３に係る半導体装置では、平面視上において、接着補強凸部１が成す円弧の中心Ｏと、当該接着補強凸部１に対応する半導体チップ３の角３ａとを結ぶ仮想直線５０は、当該角３ａを成す半導体チップ３の２つのチップ辺３ｂとそれぞれ４５°の角度を成す。つまり、平面視上において当該仮想直線５０は角３ａが成す角度を均等に二分する。   As shown in FIG. 8, in the semiconductor device according to the third embodiment, in plan view, the center O of the arc formed by the adhesion reinforcing protrusion 1 and the semiconductor chip 3 corresponding to the adhesion reinforcing protrusion 1. The virtual straight line 50 connecting the corner 3a forms an angle of 45 ° with the two chip sides 3b of the semiconductor chip 3 forming the corner 3a. That is, the virtual straight line 50 equally bisects the angle formed by the corner 3a in plan view.

また、接着補強凸部１が成す円弧の中心Ｏと、当該接着補強凸部１に対応する半導体チップ３の角３ａとの距離ｄ１は、半導体チップ３の厚みｈ１の１倍以上５倍以下に設定されている。つまり、距離ｄ１はｈ１≦ｄ１≦５×ｈ１を満足する。   Further, the distance d1 between the center O of the arc formed by the adhesion reinforcing convex portion 1 and the corner 3a of the semiconductor chip 3 corresponding to the adhesive reinforcing convex portion 1 is 1 to 5 times the thickness h1 of the semiconductor chip 3. Is set. That is, the distance d1 satisfies h1 ≦ d1 ≦ 5 × h1.

接着補強凸部１が成す円弧の半径ｒ、つまり平面視上において接着補強凸部１の円弧方向に延びる中心線１ａと中心Ｏとの半径方向の距離は、距離ｄ１と同様に、半導体チップ３の厚みｈ１の１倍以上５倍以下に設定され、当該半径ｒはｈ１≦ｒ≦５×ｈ１を満足する。そして、接着補強凸部１は、仮想直線５０の両側に均等に広がる１／４円の円弧を成している。つまり、接着補強凸部１が成す円弧は、対応する角３ａに繋がる一方のチップ辺３ｂに対する平行線と、角３ａに繋がる他方のチップ辺３ｂに対する平行線とで、点Ｏを中心とする正円を切断して得られる、仮想直線上５０に位置する１／４円である。   The radius r of the arc formed by the adhesion reinforcing projection 1, that is, the distance in the radial direction between the center line 1 a extending in the arc direction of the adhesion reinforcement projection 1 and the center O in plan view is the same as the distance d 1, the semiconductor chip 3. The thickness r is set to be 1 to 5 times the thickness h1, and the radius r satisfies h1 ≦ r ≦ 5 × h1. And the adhesion reinforcement convex part 1 has comprised the circular arc of the ¼ circle spread equally on the both sides of the virtual straight line 50. That is, the arc formed by the adhesion reinforcing convex portion 1 is a positive line centered on the point O between a parallel line to one tip side 3b connected to the corresponding corner 3a and a parallel line to the other tip side 3b connected to the corner 3a. This is a ¼ circle located on the virtual straight line 50 obtained by cutting the circle.

このように、距離ｄ１がｈ１≦ｄ１≦５×ｈ１を満足し、かつ半径ｒもｈ１≦ｒ≦５×ｈ１を満足し、かつ接着補強凸部１が成す、仮想直線５０の両側に均等に広がる円弧のサイズが１／４円の場合には、コーティング材２で発生した、半導体チップ３の角３ａ付近に集中する熱応力を最も効果的に分散することができる。   In this way, the distance d1 satisfies h1 ≦ d1 ≦ 5 × h1, the radius r also satisfies h1 ≦ r ≦ 5 × h1, and the adhesive reinforcing convex portion 1 is formed evenly on both sides of the virtual straight line 50. When the size of the expanding arc is ¼ circle, the thermal stress concentrated in the vicinity of the corner 3a of the semiconductor chip 3 generated in the coating material 2 can be most effectively dispersed.

図１０は、距離ｅ１と接着補強凸部１が成す円弧のサイズを一定にして半径ｒを変化させた際の本半導体装置の不良率を示す図であり、図１１は、半径ｒと接着補強凸部１が成す円弧のサイズを一定にして距離ｄ１を変化させた際の本半導体装置の不良率を示す図であり、図１２は、距離ｄ１及び半径ｒを一定にして接着補強凸部１が成す円弧のサイズを変化させた際の本半導体装置の不良率を示す図である。なお距離ｅ１は、接着補強凸部１が成す円弧と、それに対応する半導体チップ３の角３ａとの距離であって、具体的には、図８に示されるように、仮想直線５０と中心線１ａとの交点と、半導体チップ３の角３ａとの距離である。   FIG. 10 is a diagram showing the defect rate of the present semiconductor device when the radius r is changed while keeping the distance e1 and the size of the arc formed by the adhesion reinforcing convex portion 1 constant, and FIG. FIG. 12 is a diagram showing a defect rate of the semiconductor device when the distance d1 is changed while keeping the size of the arc formed by the protrusion 1 constant, and FIG. 12 shows the adhesion reinforcing protrusion 1 with the distance d1 and the radius r constant. It is a figure which shows the defect rate of this semiconductor device at the time of changing the size of the circular arc which consists of. Note that the distance e1 is the distance between the arc formed by the adhesion reinforcing convex portion 1 and the corresponding corner 3a of the semiconductor chip 3, and specifically, as shown in FIG. 8, the virtual straight line 50 and the center line This is the distance between the intersection with 1a and the corner 3a of the semiconductor chip 3.

図１０〜１２に示される結果は、半導体チップ３のチップサイズを縦５ｍｍ×横５ｍｍｍ×厚み０．５ｍｍとし、コーティング材２としてゴム硬度３５、熱伝導率０．３Ｗ／ｍ・ｋの樹脂を使用し、接着補強凸部１としてゴム硬度６０の樹脂を使用した場合の結果である。また、図１０〜１２に示される不良率は、本半導体装置の周囲温度を−５０℃〜２００℃まで変化させる熱サイクル試験を１００回繰り返した後にコーティング材２の剥離状況を確認し、当該剥離状況が一定の基準を満足するか否かに基づいて算出している。   The results shown in FIGS. 10 to 12 show that the chip size of the semiconductor chip 3 is 5 mm long × 5 mm wide × 0.5 mm thick, and the coating material 2 is a resin having a rubber hardness of 35 and a thermal conductivity of 0.3 W / m · k. It is a result at the time of using and using resin of rubber hardness 60 as the adhesion reinforcement convex part 1. FIG. Also, the defect rate shown in FIGS. 10 to 12 is obtained by confirming the peeling state of the coating material 2 after repeating the thermal cycle test for changing the ambient temperature of the semiconductor device from −50 ° C. to 200 ° C. 100 times. Calculations are based on whether the situation meets certain criteria.

なお、図１０においては、半径ｒ、距離ｅ１及び接着補強凸部１が成す円弧のサイズがすべて零の場合の不良率が示されており、図１１，１２においては、半径ｒ、距離ｄ１及び接着補強凸部１が成す円弧のサイズがすべて零の場合の不良率が示されているが、これらの不良率は、本発明の接着補強凸部１を形成しなかった場合の不良率である。   FIG. 10 shows the defect rate when the radius r, the distance e1, and the size of the arc formed by the adhesion reinforcing protrusion 1 are all zero. In FIGS. 11 and 12, the radius r, the distance d1, The defect rate when the sizes of the arcs formed by the adhesive reinforcing convex portion 1 are all zero is shown. These defective rates are defective rates when the adhesive reinforcing convex portion 1 of the present invention is not formed. .

図１０に示されるように、半導体チップ３の厚みｈ１が０．５ｍｍの場合において、接着補強凸部１が成す円弧の半径ｒが０．５ｍｍから２．５ｍｍの範囲内に設定されると、不良率が０．２％以下となり、この場合には本半導体装置の信頼性が非常に高いと言える。そして、半径ｒについての不良率が低い範囲は、半導体チップ３の厚みｈ１に比例することから、本実施の形態３のように、半径ｒを半導体チップ３の厚さｈ１の１倍以上５倍以下に設定することによって、コーティング材２で発生した熱応力が効果的に分散され、コーティング材２がベース板５から剥がれにくくなり、本半導体装置の信頼性を向上することができる。   As shown in FIG. 10, when the thickness h1 of the semiconductor chip 3 is 0.5 mm, when the radius r of the arc formed by the adhesion reinforcing convex portion 1 is set within the range of 0.5 mm to 2.5 mm, The defect rate is 0.2% or less. In this case, it can be said that the reliability of the semiconductor device is very high. The range in which the defect rate for the radius r is low is proportional to the thickness h1 of the semiconductor chip 3, so that the radius r is 1 to 5 times the thickness h1 of the semiconductor chip 3 as in the third embodiment. By setting as follows, the thermal stress generated in the coating material 2 is effectively dispersed, and the coating material 2 becomes difficult to peel off from the base plate 5, and the reliability of the semiconductor device can be improved.

また、図１１に示されるように、半導体チップ３の厚みｈ１が０．５ｍｍの場合において、接着補強凸部１が成す円弧の中心Ｏと半導体チップ３の角３ａとの距離ｄ１が０．５ｍｍから２．５ｍｍの範囲内に設定されると、不良率が０．５％以下であり、この場合には本半導体装置の信頼性が非常に高いと言える。   As shown in FIG. 11, when the thickness h1 of the semiconductor chip 3 is 0.5 mm, the distance d1 between the center O of the arc formed by the adhesion reinforcing convex portion 1 and the corner 3a of the semiconductor chip 3 is 0.5 mm. To 2.5 mm, the defect rate is 0.5% or less. In this case, it can be said that the reliability of the semiconductor device is very high.

ここで、ベース板５とコーティング材２との界面において熱応力が最も大きくなる位置は、半導体チップ３の厚みｈ１に依存し、当該厚みｈ１に比例して、当該位置は半導体チップ３の側面から離れる傾向にある。これは、コーティング材２の熱膨張動作が、当該コーティング材２よりも弾性率の高いベース板５及び半導体チップ３によって拘束されるからである。従って、距離ｄ１についての不良率が低い範囲は、半導体チップ３の厚みｈ１に比例する。   Here, the position where the thermal stress is greatest at the interface between the base plate 5 and the coating material 2 depends on the thickness h1 of the semiconductor chip 3, and the position is proportional to the thickness h1 from the side surface of the semiconductor chip 3. There is a tendency to leave. This is because the thermal expansion operation of the coating material 2 is restrained by the base plate 5 and the semiconductor chip 3 having a higher elastic modulus than the coating material 2. Therefore, the range where the defect rate for the distance d1 is low is proportional to the thickness h1 of the semiconductor chip 3.

以上のことから、本実施の形態３のように、距離ｄ１を半導体チップ３の厚さｈ１の１倍以上５倍以下に設定することによって、コーティング材２で発生した熱応力が効果的に分散され、コーティング材２がベース板５から剥がれにくくなり、本半導体装置の信頼性を向上することができる。   From the above, the thermal stress generated in the coating material 2 is effectively dispersed by setting the distance d1 to be not less than 1 and not more than 5 times the thickness h1 of the semiconductor chip 3 as in the third embodiment. Thus, the coating material 2 is less likely to be peeled off from the base plate 5, and the reliability of the semiconductor device can be improved.

また、図１２に示されるように、接着補強凸部１が成す円弧のサイズが１／４円のときには不良率が０．１％以下であり、この場合には本半導体装置の信頼性が非常に高いと言える。従って、本実施の形態３のように、接着補強凸部１が成す円弧のサイズを１／４円に設定することによって、コーティング材２で発生した熱応力が効果的に分散され、コーティング材２がベース板５から剥がれにくくなり、本半導体装置の信頼性を向上することができる。   Also, as shown in FIG. 12, when the size of the arc formed by the adhesion reinforcing convex portion 1 is 1/4 circle, the defect rate is 0.1% or less. In this case, the reliability of the semiconductor device is very high. It can be said that it is very expensive. Therefore, the thermal stress generated in the coating material 2 is effectively dispersed by setting the size of the arc formed by the adhesion reinforcing convex portion 1 to ¼ circle as in the third embodiment, and the coating material 2 Can hardly be peeled off from the base plate 5, and the reliability of the semiconductor device can be improved.

なお、接着補強凸部１の高さは１００μｍ程度が好ましいが、半導体チップ３の高さ以下でありコーティング材２が当該接着補強凸部１を完全に覆う高さであれば構わない。   The height of the adhesion reinforcing convex portion 1 is preferably about 100 μm, but may be any height as long as it is equal to or less than the height of the semiconductor chip 3 and the coating material 2 completely covers the adhesive reinforcing convex portion 1.

また、本実施の形態３に係る半導体装置に、ベース板５と半導体チップ３との間に介在する特定の介在層が設けられる場合には、接着補強凸部１が成す円弧の半径ｒ等は、当該介在層の厚さと半導体チップ３の厚さｈ１とを足し合わせた値を基準にして特定することになる。以下に、この場合の接着補強凸部１の形状及び配置位置について説明する。   Further, when the semiconductor device according to the third embodiment is provided with a specific intervening layer interposed between the base plate 5 and the semiconductor chip 3, the radius r of the arc formed by the adhesion reinforcing convex portion 1 is The thickness is specified based on the sum of the thickness of the intervening layer and the thickness h1 of the semiconductor chip 3. Below, the shape and arrangement | positioning position of the adhesion reinforcement convex part 1 in this case are demonstrated.

図１３は本実施の形態３に係る半導体装置の変形例の構造を示す部分断面図であって、図１４は当該変形例の構造を示す部分平面図である。本変形例は、図８，９に示される半導体装置において、絶縁性高熱伝導材１８を更に備え、接着補強凸部１の形状及び配置位置を変更したものである。なお、図１３では封止樹脂４、ワイヤ６及び電極７の記載を省略し、図１４では半導体チップ３、絶縁性高熱伝導材１８及び接着補強凸部１だけを示している。   FIG. 13 is a partial cross-sectional view showing the structure of a modification of the semiconductor device according to the third embodiment, and FIG. 14 is a partial plan view showing the structure of the modification. This modification is a semiconductor device shown in FIGS. 8 and 9, further including an insulating high thermal conductive material 18 and a modified shape and arrangement position of the adhesion reinforcing convex portion 1. In FIG. 13, the description of the sealing resin 4, the wire 6, and the electrode 7 is omitted, and in FIG. 14, only the semiconductor chip 3, the insulating high thermal conductive material 18, and the adhesion reinforcing convex portion 1 are shown.

絶縁性高熱伝導材１８は、例えばセラミック板であって、やや平たい直方体である。そして図１３に示されるように、絶縁性高熱伝導材１８はベース板５と半導体チップ３との間に介在している。   The insulating high thermal conductive material 18 is, for example, a ceramic plate and is a somewhat flat rectangular parallelepiped. As shown in FIG. 13, the insulating high thermal conductive material 18 is interposed between the base plate 5 and the semiconductor chip 3.

本変形例では、図１４に示されるように、絶縁性高熱伝導材１８と半導体チップ３とは平面視上においては相似形であって、絶縁性高熱伝導材１８の方が半導体チップ３よりも上面積が大きい。そして、半導体チップ３は、平面視上においてそのチップ辺３ｂが絶縁性高熱伝導材１８の辺１８ｂよりも内側に位置するように、当該絶縁性高熱伝導材１８上に配置されている。従って、絶縁性高熱伝導材１８の角１８ａは、半導体チップ３の角３ａよりも外側に位置している。なお角１８ａは、絶縁性高熱伝導材１８における上面と互いに繋がる２つの側面とが成す角であって、平面視上においては、互いに繋がる２つの辺１８ｂが成す角である。   In this modification, as shown in FIG. 14, the insulating high thermal conductive material 18 and the semiconductor chip 3 are similar in plan view, and the insulating high thermal conductive material 18 is more than the semiconductor chip 3. The top area is large. The semiconductor chip 3 is arranged on the insulating high heat conductive material 18 so that the chip side 3b is located on the inner side of the side 18b of the insulating high heat conductive material 18 in plan view. Accordingly, the corner 18 a of the insulating high thermal conductive material 18 is located outside the corner 3 a of the semiconductor chip 3. The corner 18a is an angle formed by the upper surface of the insulating high thermal conductive material 18 and two side surfaces connected to each other, and is an angle formed by two sides 18b connected to each other in plan view.

本変形例における接着補強凸部１は、一つの絶縁性高熱伝導材１８に対して４つ設けられている。そして、平面視上において、４つの接着補強凸部１は、半導体チップ３が有する４つの角３ａだけではなく、絶縁性高熱伝導材１８が有する４つの角１８ａと一対一で対向するように配置されている。   Four adhesive reinforcing convex portions 1 in this modification are provided for one insulating high thermal conductive material 18. Then, in plan view, the four adhesion reinforcing convex portions 1 are arranged so as to face not only the four corners 3 a of the semiconductor chip 3 but also the four corners 18 a of the insulating high thermal conductive material 18. Has been.

また、図１４に示されるように、平面視上においては、接着補強凸部１が成す円弧の中心Ｏと、当該接着補強凸部１に対応する絶縁性高熱伝導材１８の角１８ａと、当該接着補強凸部１に対応する半導体チップ３の角３ａとは仮想直線６０上に配置されている。そして、平面視上においては、仮想直線６０と、半導体チップ３における角３ａに繋がるチップ辺３ｂとの成す角度、及び当該仮想直線６０と、絶縁性高熱伝導材１８における角１８ａに繋がる辺１８ｂとの成す角度はともに４５度である。従って、平面視上において仮想直線６０は角３ａが成す角度及び角１８ａが成す角度を均等に二分する。   Further, as shown in FIG. 14, in a plan view, the center O of the arc formed by the adhesive reinforcing convex portion 1, the corner 18 a of the insulating high heat conductive material 18 corresponding to the adhesive reinforcing convex portion 1, The corner 3 a of the semiconductor chip 3 corresponding to the adhesion reinforcing protrusion 1 is arranged on the virtual straight line 60. In plan view, the angle formed by the virtual straight line 60 and the chip side 3b connected to the corner 3a in the semiconductor chip 3 and the virtual straight line 60 and the side 18b connected to the corner 18a in the insulating high heat conductive material 18 Both angles are 45 degrees. Accordingly, the virtual straight line 60 equally bisects the angle formed by the corner 3a and the angle formed by the corner 18a in plan view.

本変形例では、接着補強凸部１が成す円弧の中心Ｏと、当該接着補強凸部１に対応する絶縁性高熱伝導材１８の角１８ａとの距離ｄ２は、半導体チップ３の厚みｈ１と絶縁性高熱伝導材１８の厚みｈ２とを足し合わせた値の１倍以上５倍以下に設定されている。つまり、距離ｄ２は（ｈ１＋ｈ２）≦ｄ２≦５×（ｈ１＋ｈ２）を満足する。   In the present modification, the distance d2 between the center O of the arc formed by the adhesion reinforcing convex portion 1 and the corner 18a of the insulating high thermal conductive material 18 corresponding to the adhesive reinforcing convex portion 1 is insulated from the thickness h1 of the semiconductor chip 3. The thickness h2 of the conductive high heat conductive material 18 is set to 1 to 5 times the sum of the values. That is, the distance d2 satisfies (h1 + h2) ≦ d2 ≦ 5 × (h1 + h2).

接着補強凸部１が成す円弧の半径ｒも、距離ｄ２と同様に、半導体チップ３の厚みｈ１と絶縁性高熱伝導材１８の厚みｈ２とを足し合わせた値の１倍以上５倍以下に設定され、当該半径ｒは（ｈ１＋ｈ２）≦ｒ≦５×（ｈ１＋ｈ２）を満足する。そして、接着補強凸部１は、仮想直線６０の両側に均等に広がる１／４円の円弧を成している。   Similarly to the distance d2, the radius r of the arc formed by the adhesion reinforcing convex portion 1 is also set to 1 to 5 times the value obtained by adding the thickness h1 of the semiconductor chip 3 and the thickness h2 of the insulating high thermal conductive material 18. The radius r satisfies (h1 + h2) ≦ r ≦ 5 × (h1 + h2). And the adhesion reinforcement convex part 1 has comprised the circular arc of the 1/4 circle spread equally on the both sides of the virtual straight line 60.

本変形例において、距離ｅ２と円弧サイズを一定にして半径ｒを変化させると、図１０に示される結果と似たような結果が得られる。つまり、半径ｒが、半導体チップ３の厚さｈ１と絶縁性高熱伝導材１８の厚さｈ２とを足し合わせた値の１倍以上５倍以下の場合には不良率が１％未満となる。従って、本変形例のように、半径ｒを（ｈ１＋ｈ２）≦ｒ≦５×（ｈ１＋ｈ２）に設定することによって、コーティング材２で発生した熱応力が効果的に分散され、コーティング材２がベース板５から剥がれにくくなり、本半導体装置の信頼性を向上することができる。なお距離ｅ２は、接着補強凸部１が成す円弧と、それに対応する絶縁性高熱伝導材１８の角１８ａとの距離であって、具体的には、仮想直線６０と中心線１ａとの交点と、絶縁性高熱伝導材１８の角１８ａとの距離である。   In the present modification, when the radius r is changed with the distance e2 and the arc size fixed, a result similar to the result shown in FIG. 10 is obtained. That is, when the radius r is 1 to 5 times the value obtained by adding the thickness h1 of the semiconductor chip 3 and the thickness h2 of the insulating high thermal conductive material 18, the defect rate is less than 1%. Therefore, as in this modification, by setting the radius r to (h1 + h2) ≦ r ≦ 5 × (h1 + h2), the thermal stress generated in the coating material 2 is effectively dispersed, and the coating material 2 becomes the base plate. Therefore, the reliability of the semiconductor device can be improved. The distance e2 is the distance between the arc formed by the adhesion reinforcing convex portion 1 and the corresponding corner 18a of the insulating high heat conductive material 18, and specifically, the intersection of the imaginary straight line 60 and the center line 1a. The distance from the corner 18a of the insulating high thermal conductive material 18.

また、本変形例において、半径ｒと円弧サイズを一定にして距離ｄ２を変化させると、図１１に示される結果と似たような結果が得られる。つまり、距離ｄ２が、半導体チップ３の厚さｈ１と絶縁性高熱伝導材１８の厚さｈ２とを足し合わせた値の１倍以上５倍以下の場合には不良率が１％未満となる。従って、本変形例のように、距離ｄ２を（ｈ１＋ｈ２）≦ｄ２≦５×（ｈ１＋ｈ２）に設定することによって、コーティング材２で発生した熱応力が効果的に分散され、コーティング材２がベース板５から剥がれにくくなり、本半導体装置の信頼性を向上することができる。   Further, in the present modification, when the distance d2 is changed while the radius r and the arc size are fixed, a result similar to the result shown in FIG. 11 is obtained. That is, when the distance d2 is not less than 1 and not more than 5 times the sum of the thickness h1 of the semiconductor chip 3 and the thickness h2 of the insulating high thermal conductive material 18, the defect rate is less than 1%. Therefore, as in the present modification, by setting the distance d2 to (h1 + h2) ≦ d2 ≦ 5 × (h1 + h2), the thermal stress generated in the coating material 2 is effectively dispersed, and the coating material 2 becomes the base plate. Therefore, the reliability of the semiconductor device can be improved.

また、本変形例において、半径ｒと距離ｄ２と一定にして接着補強凸部１の円弧サイズを変化させると、図１２に示される結果と似たような結果が得られる。つまり、当該円弧サイズが１／４円のときには不良率が１％未満となる。従って、本変形例のように、接着補強凸部１が成す円弧を１／４円に設定することによって、コーティング材２で発生した熱応力が効果的に分散され、コーティング材２がベース板５から剥がれにくくなり、本半導体装置の信頼性を向上することができる。   In this modification, when the arc size of the adhesion reinforcing convex portion 1 is changed while keeping the radius r and the distance d2 constant, a result similar to the result shown in FIG. 12 is obtained. That is, when the arc size is ¼ circle, the defect rate is less than 1%. Therefore, as in this modification, by setting the arc formed by the adhesion reinforcing convex portion 1 to ¼ circle, the thermal stress generated in the coating material 2 is effectively dispersed, so that the coating material 2 becomes the base plate 5. Therefore, the reliability of the present semiconductor device can be improved.

以上の実施の形態１〜３に係る半導体装置においては、接着補強凸部１の断面形状は半球状であったが、図１５に示されるように、接着補強凸部１の表面に凹凸を設けても良い。この凹凸は、図１５に示されるように、接着補強凸部１の表面にＶ字型の窪みを形成することによって実現しても良いし、当該表面に半球状の窪みを形成することによって実現しても良い。なお、図１５と後述する図１６では、封止樹脂４、ワイヤ６及び電極７の記載を省略している。   In the semiconductor devices according to the above first to third embodiments, the cross-sectional shape of the adhesion reinforcing convex portion 1 is hemispherical. However, as shown in FIG. May be. As shown in FIG. 15, the unevenness may be realized by forming a V-shaped depression on the surface of the adhesion reinforcing convex portion 1 or by forming a hemispherical depression on the surface. You may do it. In FIG. 15 and FIG. 16 to be described later, the description of the sealing resin 4, the wire 6, and the electrode 7 is omitted.

接着補強凸部１の表面の凹凸は、ディスペンサの塗出ノズルの形状を工夫することによって形成することができるが、金型成型、転写、リソグラフィなどの方法を用いて形成しても良い。   The irregularities on the surface of the adhesion reinforcing convex portion 1 can be formed by devising the shape of the dispensing nozzle of the dispenser, but may be formed using a method such as mold molding, transfer, or lithography.

このように、接着補強凸部１の表面に凹凸を設けることによって、コーティング材２と接着補強凸部１との接触面積を更に大きくすることができるため、コーティング材２がベース板５から剥がれ難くなり、半導体装置の信頼性が更に向上する。   As described above, since the contact area between the coating material 2 and the adhesion reinforcing convex portion 1 can be further increased by providing irregularities on the surface of the adhesive reinforcing convex portion 1, the coating material 2 is hardly peeled off from the base plate 5. Thus, the reliability of the semiconductor device is further improved.

また、図１６に示されるように、接着補強凸部１の表面に、コーティング材２に対する接着性が当該接着補強凸部１よりも良好な表面処理材１４を設けても良い。表面処理材１４には、シランカップリング剤を使用するのが好ましいが、接着補強凸部１の表面には表面処理材１４として、当該接着補強凸部１よりも接着性が良好なエポキシ樹脂、シリコーン樹脂、ポリイミド樹脂などを塗布しても良い。   Further, as shown in FIG. 16, a surface treatment material 14 having better adhesion to the coating material 2 than the adhesion reinforcing convex portion 1 may be provided on the surface of the adhesive reinforcing convex portion 1. Although it is preferable to use a silane coupling agent for the surface treatment material 14, an epoxy resin having better adhesion than the adhesion reinforcement projection 1 as the surface treatment material 14 on the surface of the adhesion reinforcement projection 1, Silicone resin, polyimide resin, or the like may be applied.

また、表面処理材１４は、接着補強凸部１を作製した後にその表面にディスペンサ等を用いて塗布するのが好ましいが、蒸着、転写などの方法によっても表面処理材１４を形成しても良い。   Moreover, it is preferable to apply the surface treatment material 14 to the surface of the surface after forming the adhesion reinforcing convex portion 1 using a dispenser or the like. However, the surface treatment material 14 may be formed by a method such as vapor deposition or transfer. .

このように、コーティング材２に対する接着性が接着補強凸部１よりも良好な表面処理材１４を当該接着補強凸部１の表面に設けることによって、コーティング材２と接着補強凸部１との接着性が向上し、コーティング材２がベース板５から剥がれ難くなり、半導体装置の信頼性が更に向上する。   As described above, the surface treatment material 14 having better adhesion to the coating material 2 than the adhesion reinforcing convex portion 1 is provided on the surface of the adhesive reinforcing convex portion 1, thereby bonding the coating material 2 and the adhesive reinforcing convex portion 1. As a result, the coating material 2 is hardly peeled off from the base plate 5 and the reliability of the semiconductor device is further improved.

本発明の実施の形態１に係る半導体装置の構造を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体装置の変形例の構造を示す断面図である。It is sectional drawing which shows the structure of the modification of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体装置の変形例の構造を示す断面図である。It is sectional drawing which shows the structure of the modification of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体装置の変形例の構造を示す断面図である。It is sectional drawing which shows the structure of the modification of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体装置の変形例の構造を示す断面図である。It is sectional drawing which shows the structure of the modification of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態２に係る半導体装置の構造を示す平面図である。It is a top view which shows the structure of the semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態２に係る半導体装置の変形例の構造を示す平面図である。It is a top view which shows the structure of the modification of the semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態３に係る半導体装置の構造を拡大して示す部分平面図である。It is a fragmentary top view which expands and shows the structure of the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態３に係る半導体装置の構造を拡大して示す部分断面図である。It is a fragmentary sectional view which expands and shows the structure of the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態３に係る半導体装置の不良率を示す図である。It is a figure which shows the defect rate of the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態３に係る半導体装置の不良率を示す図である。It is a figure which shows the defect rate of the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態３に係る半導体装置の不良率を示す図である。It is a figure which shows the defect rate of the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態３に係る半導体装置の変形例の構造を示す部分断面図である。It is a fragmentary sectional view which shows the structure of the modification of the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態３に係る半導体装置の変形例の構造を示す平面図である。It is a top view which shows the structure of the modification of the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態１〜３に係る半導体装置の変形例の構造を示す部分断面図である。It is a fragmentary sectional view which shows the structure of the modification of the semiconductor device which concerns on Embodiment 1-3 of this invention. 本発明の実施の形態１〜３に係る半導体装置の変形例の構造を示す部分断面図である。It is a fragmentary sectional view which shows the structure of the modification of the semiconductor device which concerns on Embodiment 1-3 of this invention.

符号の説明Explanation of symbols

１ 接着補強凸部、２ コーティング材、３ 半導体チップ、３ａ，１８ａ 角、３ｂ チップ辺、４ 封止樹脂、５ ベース板、１８ 絶縁性高熱伝導材、１８ｂ 辺、５０，６０ 仮想直線。
DESCRIPTION OF SYMBOLS 1 Adhesive reinforcement convex part, 2 coating material, 3 semiconductor chip, 3a, 18a corner | angular, 3b chip edge, 4 sealing resin, 5 base board, 18 insulating high heat conductive material, 18b edge | side, 50,60 virtual straight line.

Claims (13)

半導体チップと、
前記半導体チップを搭載するベース板と、
前記ベース板上に設けられた凸部と、
前記凸及び前記半導体チップを覆って前記ベース板上に設けられた、前記ベース板、前記凸部及び前記半導体チップよりも弾性率の低いコーティング材と
を備える、半導体装置。 A semiconductor chip;
A base plate on which the semiconductor chip is mounted;
A convex portion provided on the base plate;
A semiconductor device comprising: the base plate, the convex portion, and a coating material having a lower elastic modulus than the semiconductor chip, which is provided on the base plate so as to cover the convex and the semiconductor chip. 請求項１に記載の半導体装置であって、
前記コーティング材と前記ベース板とを覆う封止樹脂を更に備え、
前記コーティング材の熱伝導率は前記封止樹脂よりも低い、半導体装置。 The semiconductor device according to claim 1,
A sealing resin covering the coating material and the base plate;
The semiconductor device, wherein the coating material has a lower thermal conductivity than the sealing resin. 請求項１及び請求項２のいずれか一つに記載の半導体装置であって、
前記凸部は樹脂で形成されている、半導体装置。 A semiconductor device according to any one of claims 1 and 2,
The semiconductor device, wherein the protrusion is made of resin. 請求項１乃至請求項３のいずれか一つに記載の半導体装置であって、
平面視上において、前記凸部は、前記半導体チップにおける互いに繋がる２つのチップ辺が成す角に対向するように配置され、かつ前記角とは離れる方向に突出する円弧状に形成されている、半導体装置。 A semiconductor device according to any one of claims 1 to 3,
In plan view, the convex portion is arranged to face an angle formed by two chip sides connected to each other in the semiconductor chip, and is formed in an arc shape protruding in a direction away from the corner. apparatus. 請求項４に記載の半導体装置であって、
平面視上において前記半導体チップの前記角の角度は９０°であって、
平面視上においては、前記凸部が成す円弧の中心と前記半導体チップの前記角とを結ぶ仮想直線と、前記半導体チップの前記チップ辺との成す角度は４５度であって、更に、前記円弧は前記仮想直線の両側に均等に広がり、
前記円弧の半径は、前記半導体チップの厚みの１倍以上５倍以下に設定されている、半導体装置。 The semiconductor device according to claim 4,
In plan view, the angle of the corner of the semiconductor chip is 90 °,
In plan view, an angle formed between a virtual straight line connecting the center of the arc formed by the convex portion and the corner of the semiconductor chip and the chip side of the semiconductor chip is 45 degrees, and the arc Spreads evenly on both sides of the virtual straight line,
The radius of the said circular arc is a semiconductor device set to 1 to 5 times the thickness of the said semiconductor chip. 請求項４に記載の半導体装置であって、
平面視上において前記半導体チップの前記角の角度は９０°であって、
平面視上においては、前記凸部が成す円弧の中心と前記半導体チップの前記角とを結ぶ仮想直線と、前記半導体チップの前記チップ辺との成す角度は４５度であって、更に、前記円弧は前記仮想直線の両側に均等に広がり、
前記円弧の中心と前記半導体チップの前記角との平面視上における距離は、前記半導体チップの厚みの１倍以上５倍以下に設定されている、半導体装置。 The semiconductor device according to claim 4,
In plan view, the angle of the corner of the semiconductor chip is 90 °,
In plan view, an angle formed between a virtual straight line connecting the center of the arc formed by the convex portion and the corner of the semiconductor chip and the chip side of the semiconductor chip is 45 degrees, and the arc Spreads evenly on both sides of the virtual straight line,
A distance between the center of the arc and the corner of the semiconductor chip in a plan view is set to 1 to 5 times the thickness of the semiconductor chip. 請求項４に記載の半導体装置であって、
平面視上において前記半導体チップの前記角の角度は９０°であって、
平面視上においては、前記凸部が成す円弧の中心と前記半導体チップの前記角とを結ぶ仮想直線と、前記半導体チップの前記チップ辺との成す角度は４５度であって、更に、前記円弧は前記仮想直線の両側に均等に広がり、
前記円弧は１／４円を成す、半導体装置。 The semiconductor device according to claim 4,
In plan view, the angle of the corner of the semiconductor chip is 90 °,
In plan view, an angle formed between a virtual straight line connecting the center of the arc formed by the convex portion and the corner of the semiconductor chip and the chip side of the semiconductor chip is 45 degrees, and the arc Spreads evenly on both sides of the virtual straight line,
The semiconductor device in which the arc forms a quarter circle. 請求項４に記載の半導体装置であって、
平面視上において前記半導体チップの前記角の角度は９０°であって、
前記ベース板と前記半導体チップとの間に介在する介在層を更に備え、
平面視上において、前記介在層における互いに繋がる２つの辺が成す角の角度は９０°であって、
前記介在層の前記角は、前記半導体チップの前記角よりも外側に位置し、
平面視上においては、前記凸部が成す円弧の中心と、前記介在層の前記角と、前記半導体チップの前記角とは仮想直線上に配置され、当該仮想直線と前記半導体チップの前記チップ辺との成す角度、及び当該仮想直線と前記介在層の前記辺との成す角度はともに４５度であって、更に前記円弧は前記仮想直線の両側に均等に広がり、
前記円弧の半径は、前記介在層の厚みと前記半導体チップの厚みとを足し合わせた値の１倍以上５倍以下に設定されている、半導体装置。 The semiconductor device according to claim 4,
In plan view, the angle of the corner of the semiconductor chip is 90 °,
An intervening layer interposed between the base plate and the semiconductor chip;
In plan view, an angle formed by two sides connected to each other in the intervening layer is 90 °,
The corner of the intervening layer is located outside the corner of the semiconductor chip,
In plan view, the center of the arc formed by the convex portion, the corner of the intervening layer, and the corner of the semiconductor chip are arranged on a virtual straight line, and the virtual straight line and the chip side of the semiconductor chip And the angle formed by the virtual straight line and the side of the intervening layer are both 45 degrees, and the arc further extends equally on both sides of the virtual straight line,
The radius of the circular arc is set to 1 to 5 times the value obtained by adding the thickness of the intervening layer and the thickness of the semiconductor chip. 請求項４に記載の半導体装置であって、
平面視上において前記半導体チップの前記角の角度は９０°であって、
前記ベース板と前記半導体チップとの間に介在する介在層を更に備え、
平面視上において、前記介在層における互いに繋がる２つの辺が成す角の角度は９０°であって、
前記介在層の前記角は、前記半導体チップの前記角よりも外側に位置し、
平面視上においては、前記凸部が成す円弧の中心と、前記介在層の前記角と、前記半導体チップの前記角とは仮想直線上に配置され、当該仮想直線と前記半導体チップの前記チップ辺との成す角度、及び当該仮想直線と前記介在層の前記辺との成す角度はともに４５度であって、更に前記円弧は前記仮想直線の両側に均等に広がり、
前記円弧の中心と前記介在層の前記角との平面視上における距離は、前記介在層の厚みと前記半導体チップの厚みを足し合わせた値の１倍以上５倍以下に設定されている、半導体装置。 The semiconductor device according to claim 4,
In plan view, the angle of the corner of the semiconductor chip is 90 °,
An intervening layer interposed between the base plate and the semiconductor chip;
In plan view, an angle formed by two sides connected to each other in the intervening layer is 90 °,
The corner of the intervening layer is located outside the corner of the semiconductor chip,
In plan view, the center of the arc formed by the convex portion, the corner of the intervening layer, and the corner of the semiconductor chip are arranged on a virtual straight line, and the virtual straight line and the chip side of the semiconductor chip And the angle formed by the virtual straight line and the side of the intervening layer are both 45 degrees, and the arc further extends equally on both sides of the virtual straight line,
The distance in plan view between the center of the arc and the corner of the intervening layer is set to 1 to 5 times the sum of the thickness of the intervening layer and the thickness of the semiconductor chip. apparatus. 請求項４に記載の半導体装置であって、
平面視上において前記半導体チップの前記角の角度は９０°であって、
前記ベース板と前記半導体チップとの間に介在する介在層を更に備え、
平面視上において、前記介在層における互いに繋がる２つの辺が成す角の角度は９０°であって、
前記介在層の前記角は、前記半導体チップの前記角よりも外側に位置し、
平面視上においては、前記凸部が成す円弧の中心と、前記介在層の前記角と、前記半導体チップの前記角とは仮想直線上に配置され、当該仮想直線と前記半導体チップの前記チップ辺との成す角度、及び当該仮想直線と前記介在層の前記辺との成す角度はともに４５度であって、更に前記円弧は前記仮想直線の両側に均等に広がり、
前記円弧は１／４円を成す、半導体装置。 The semiconductor device according to claim 4,
In plan view, the angle of the corner of the semiconductor chip is 90 °,
An intervening layer interposed between the base plate and the semiconductor chip;
In plan view, an angle formed by two sides connected to each other in the intervening layer is 90 °,
The corner of the intervening layer is located outside the corner of the semiconductor chip,
In plan view, the center of the arc formed by the convex portion, the corner of the intervening layer, and the corner of the semiconductor chip are arranged on a virtual straight line, and the virtual straight line and the chip side of the semiconductor chip And the angle formed by the virtual straight line and the side of the intervening layer are both 45 degrees, and the arc further extends equally on both sides of the virtual straight line,
The semiconductor device in which the arc forms a quarter circle. 請求項１乃至請求項１０のいずれか一つに記載の半導体装置であって、
前記凸部の表面には凹凸が設けられている、半導体装置。 A semiconductor device according to any one of claims 1 to 10,
A semiconductor device, wherein irregularities are provided on a surface of the convex portion. 請求項１乃至請求項１１のいずれか一つに記載の半導体装置であって、
前記凸部の表面には、前記コーティング材に対する接着性が前記凸部よりも良好な表面処理材が設けられている、半導体装置。 A semiconductor device according to any one of claims 1 to 11,
A semiconductor device, wherein a surface treatment material having better adhesion to the coating material than the convex portion is provided on a surface of the convex portion. 半導体チップと、
前記半導体チップを搭載するベース板と、
前記半導体チップを覆って前記ベース板上に設けられたコーティング材と、
前記コーティング材と前記ベース板とを覆う封止樹脂と
を備え、
前記コーティング材の熱伝導率は前記封止樹脂よりも低い、半導体装置。
A semiconductor chip;
A base plate on which the semiconductor chip is mounted;
A coating material that covers the semiconductor chip and is provided on the base plate;
A sealing resin covering the coating material and the base plate;
The semiconductor device, wherein the coating material has a lower thermal conductivity than the sealing resin.
JP2005012280A 2005-01-20 2005-01-20 Semiconductor device Pending JP2006202936A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009010313A (en) * 2007-05-30 2009-01-15 Denso Corp Resin sealed semiconductor apparatus
JP2012109437A (en) * 2010-11-18 2012-06-07 Elpida Memory Inc Semiconductor device and method of manufacturing the same
WO2015033633A1 (en) * 2013-09-03 2015-03-12 株式会社村田製作所 Vertical cavity surface emitting laser element, semiconductor wafer and light emitting module provided with vertical cavity surface emitting laser element, and method for manufacturing vertical cavity surface emitting laser element
JP2018186292A (en) * 2018-07-17 2018-11-22 株式会社東芝 Semiconductor device and optical coupling device
US10833055B2 (en) 2015-09-04 2020-11-10 Kabushiki Kaisha Toshiba Semiconductor device and optical coupling device
CN112992821A (en) * 2019-12-13 2021-06-18 珠海格力电器股份有限公司 Chip packaging structure and packaging method thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009010313A (en) * 2007-05-30 2009-01-15 Denso Corp Resin sealed semiconductor apparatus
JP2012109437A (en) * 2010-11-18 2012-06-07 Elpida Memory Inc Semiconductor device and method of manufacturing the same
US9466546B2 (en) 2010-11-18 2016-10-11 Ps4 Luxco S.A.R.L. Semiconductor device and method of forming the same
WO2015033633A1 (en) * 2013-09-03 2015-03-12 株式会社村田製作所 Vertical cavity surface emitting laser element, semiconductor wafer and light emitting module provided with vertical cavity surface emitting laser element, and method for manufacturing vertical cavity surface emitting laser element
US10833055B2 (en) 2015-09-04 2020-11-10 Kabushiki Kaisha Toshiba Semiconductor device and optical coupling device
JP2018186292A (en) * 2018-07-17 2018-11-22 株式会社東芝 Semiconductor device and optical coupling device
CN112992821A (en) * 2019-12-13 2021-06-18 珠海格力电器股份有限公司 Chip packaging structure and packaging method thereof

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