JPS63226031A - Manufacture of compound structure - Google Patents

Abstract

PURPOSE:To assure the voidless low thermal resistance bonding process excellent in mechanical strength by a method wherein a melting material as an intermedi ate material is previously provided in the region along the periphery of bonded region such as a semiconductor pellet or a wiring substrate to be heat-melted in the atmosphere at specified pressure. CONSTITUTION:Specimens (an Si chip 11, a solder preform 13 and a heat sink 14) are mounted on a heating base provided in an exhaust system 16 while the atmospheric pressure is reduced down to 1torr. Due to the naturally made minor gaps, the pressure in the inner region 17 of solder preform 13 is immedi ately reduced down to 1torr to heat-melt the solder preform 13 at around 220 deg.C augmenting the liquidity for creating the close contact state or intermetal reac tion state between the metalized layers 12 and 15. The atmospheric pressure is restored to the normal pressure of 760torr with the solder preform 13 heat- melted as it is. Through these procedures, any external pressure is applied on the melted solder preform 13 to reduce the volume of inner region 17 marked ly. Finally, heating process is stopped to bond the solder 13 so that the specified substantial voidless solder bonded structure may be manufactured.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a manufacturing technology for composite members, and particularly to a method for manufacturing a composite structure suitable for realizing highly reliable bonding between a semiconductor pellet and a substrate. .

[Conventional technology]

In order to obtain highly reliable bonding of semiconductor pellets, the bonding with heat sinks and wiring boards must have low thermal resistance and excellent mechanical strength. The conventional method for forming low thermal resistance junctions is based on Japanese Patent Application Laid-Open No. 60-214536 (hereinafter referred to as "prior art").
As described in A), a groove is provided in the center of the back surface of the semiconductor chip, and this surface is fixed to the package base via a melting material to prevent voids from forming in the bonding layer. Furthermore, in order to solve the problem that thermal strain caused by temperature cycling etc. causes pellet cracks and deteriorates mechanical strength, as described in JP-A-61-125025 (hereinafter referred to as prior art (B)), The pellet crack resistance was improved by using a eutectic metal plate with multiple through holes as the bonding material and applying pressure to make the bonding layer void-free.

[Problem that the invention seeks to solve]

The prior art (A) is expected to have the effect of increasing the leakage of the fusion material (gold silicon) due to the presence of the groove provided on the back surface of the silicon chip. This is thought to be because gas can easily escape through the grooves, thereby preventing the generation of voids.

However, according to the experience of the present inventors, the configuration that can exhibit the above effects is limited for the following reasons. For example, it is difficult to achieve the above effect when a compound semiconductor chip other than a silicon chip is used, or when a Pb-8n solder other than gold silicon is used as a flux.

First of all, it goes without saying that the prior art (A) cannot be applied to devices where it is undesirable to form a groove in the central portion of the back surface of the chip for process reasons or from the viewpoint of reliability.

Second, in order to improve solder leakage, it is necessary to metallize the entire sidewall of the groove provided on the back of the chip, and to do this, a new technical national policy of metallizing uneven surfaces is required. There is a problem in that not only does the metallization increase, but also voids are caused due to leakage defects in areas where the metallization is insufficient.

The range of application of the prior art (B) is limited for the following reasons in order to achieve the effect of improving pellet cracking resistance and reducing thermal resistance due to void-free formation.

First of all, when using a eutectic metal plate with multiple through holes as a bonding material and pressurizing pellets to eliminate voids in the bonding layer, the pressure causes the through holes to flow and fill. A natural oxide film usually exists on the surface of eutectic metals other than eutectic metals. As a result, when looking at the entire bonding surface, non-uniform leakage conditions were created, which resulted in problems such as a decrease in mechanical strength due to the generation of local stress and non-uniform temperature distribution, which impaired reliability. .

The Au mentioned in the example of the conventional technology (B)
When Pb-3n solder, which is relatively prone to natural oxidation on the surface, is used as a flux other than the eutectic metal, it is extremely difficult to achieve the straightening effect expected in conventional technology CB). Ta.

The purpose of the present invention is to
Another object of the present invention is to provide a highly reliable and simple manufacturing method for a composite structure having void-free, low thermal resistance bonding with excellent mechanical strength, regardless of the shape and dimensions of the bonding surfaces.

[Means for solving problems]

The above purpose is to provide a melting material as an intermediate material in advance in the area along the outer periphery so as to confine the spatial area formed by the bonded areas such as semiconductor pellets and wiring boards that make up the members of the composite structure, and to apply a predetermined pressure. We take measures to increase fluidity by heating and melting the flux in an atmosphere with
This is achieved by introducing the main step of causing the melt to flow by increasing the pressure.

[Effect]

When the melting material is melted in an atmosphere of pressure P1, it leaks only at the outer periphery of the joint surfaces of the members and the parts come into close contact, and as a result, a spatial region of volume v1 having pressure P1 is also sealed in the inner part. Furthermore, by increasing the pressure of the atmosphere to P2O>pt), a pressure difference is created between the inside and outside of the sealed space area, causing the melt to flow, resulting in a bonded structure that has good heat conduction performance that is substantially equivalent to voidless. get.

In this case, no matter what non-flat portions exist on the joint surfaces of the members, the requirement that the melting material be placed so as to seal the spatial region is satisfied.

The space region can be densely filled with flux.

Furthermore, when solder is used as a flux, its surface is usually covered with a natural oxide film. However, since the spatial region is filled with the intrinsic solder that breaks through the oxide film and flows in, it is possible to produce extremely good leakage properties without using flux to remove the oxide film, and to improve mechanical strength and heat resistance. An ideal taraxless solder joint with excellent conductivity can be obtained.

〔Example〕

Two embodiments of the present invention will be described below with reference to FIGS. 1 to 8.

Embodiment (1) FIGS. 1(a) to 1(d) are diagrams illustrating steps for realizing a substantially void-free solder fixing structure according to the present invention.

11 is a lea-angle silicon large-scale integrated circuit (Si-L
SI) chip, and the back side has T i / N i /
A metallized layer 12 having a three-layer structure is formed. 13 is a Pb-
It was a 40wt, %Sn solder preform, and the width of the band-shaped portion was 1 mm and the thickness was 100 μm. ■4 is a heat sink made of SiC ceramic, with Ti on the surface.
A metallized layer 15 having a three-layer structure of /Ni/Au is formed. It should be noted that this figure shows only the minimum components necessary for explaining the solder fixing method of the present invention, and illustrations of chip wiring and other structures necessary for practical use are completely omitted.

Hereinafter, a method for creating a voidless solder bonding structure according to Example (1) of the present invention will be described in detail in the order of steps shown in FIGS. 1(a) to (d).

First, in Figure 1(a), a sample (Si
Chip 11. Solder preform 13° heat sink 14
) and the atmosphere was reduced to I Torr. At this time, the solder preform 13 is in a solid state. Therefore, since there is inevitably a slight gap between the bonding surfaces of the Si chip 11 and the heat sink 14 that are mechanically placed one on top of the other, the inner region 17 of the solder preform 13 is also immediately exposed to the heat sink.
The pressure is reduced to Torr.

In such a state, in Figure (b), the solder preform 1
No. 3 was heated and melted at about 220° C. to increase fluidity and to create sufficient adhesion or intermetallic reaction with the metallized layers 12 and 15. At this point, the inner region 17 (with volume v1) is almost completely sealed from the outside, and its pressure P1 is maintained at I Torr.

Next, in the same figure (c), while the solder preform 13 is heated and melted, the atmospheric pressure and force are set to 760 Torr.
(pressure P2). As a result, the melted solder preform 13 is exposed to external pressure (normal pressure 760 Torr).
) is added. Through this operation, the volume of the inner region 17 is significantly reduced (at this time, the volume is set to v2).

Finally, in FIG. 4(d), heating is stopped to solidify the solder 13, thereby obtaining the required substantially void-free solder bonding structure.

The results for a large number of samples were obtained from the data obtained by measuring the void area using soft X-ray transmission images and the finally obtained data about the thickness of the solder bonding layer.

FIG. 2 shows experimental results clearly showing the effect of implementing the present invention, and compares the average void ratio between the conventional method and the method according to the present invention. Method (2) is a method in which pb-40wt%Sn solder is previously formed on the entire surface of one of the parts to be soldered. In response to this, method (1), called the soldering method, prepared a sample using the method (2), and applied the method of the present invention (reduced pressure→solder melting→normal pressure→solder solidification) only to the solder fixation process. Method (2) is based on the method of the present invention, and differs from method (2) in that solder is provided only in the area along the outer peripheral area of the fixing surface.

As is clear from the results shown in FIG. 2, the average void percentage of Methods (1) and (2) is 30 to 60%, while that of Method (2) is at most 1%, indicating that the void reduction effect of the present invention is extremely remarkable. Third
The photographs shown in the figure are soft X-ray transmission images (microscopic photographs) of solder-fixed samples prepared by methods ① to ②, and the white parts are void parts.

The black parts correspond to solder joints. For method (2), photographs taken in steps (b) and (d) of FIG. 1 are shown.

A supplementary explanation of the characteristics of each method is given below.

In method ■, gas (air) is taken in during solder fixation due to the slight waviness that occurs on the surface of the solder layer, resulting in a reduction of 50%.
It was difficult to obtain the following void ratio with good reproducibility.

Method ① has the effect of reducing the volume of voids sealed inside the solder layer.

Since voids also occur in peripheral areas that are not sealed from the external atmosphere, the void ratio varies widely, and the United Nations recommended that the void ratio be kept at 20% or less. Furthermore, as a common condition seen in methods and (2) above.

Due to the presence of an oxide film on the surface of the solder, it was difficult to obtain good solder leakage.

In contrast, in method (2) of the present invention, the region 17 inside the solder preform (which can also be called an intentionally created void) is substantially in a vacuum state and sealed from the external atmosphere in the initial state; In this method, the natural oxide film of the solder preform was broken and the intrinsic solder flowed in, so there were no problems seen in the above methods and ideal solder leakage was obtained. This state will be explained in detail with reference to FIG.

The solder preform 13 is usually manufactured by molding, punching, etc., but a natural oxide film 13-b is formed on the surface of the intrinsic solder 13-a due to the manufacturing process and the elapse of storage time in the atmosphere. There is. Therefore, the first
The solder preform 13 in step (b) of the figure is the fourth
As shown in Figure (a), it is in contact with the metallized layers 12 and 15 via the natural oxide film 13-b. (In this case, a state in which a portion of the oxide film 13-b is lost and the intrinsic solder 13-a flows out may occur depending on the process conditions such as how the load is applied to the Si chip 11.

Rather, the conventional method uses a method of applying mechanical vibration to the Si chip 11 in order to create such a state and increase leakage. ) FIG. 4(b) corresponds to the step (c) in FIG. 1, in which the intrinsic solder 13-a is
-b is broken and flows to region 17. Oxide film 1
It was easily confirmed by Auger elemental analysis that the 3-stain remained only around the solder bonding surface.

As described above, in Example (1), no non-uniformity of solder leakage occurred within the main bonding surface.

That is, the above-mentioned prior art (B) (Japanese Unexamined Patent Publication No. 61-125
No problem of reduced bonding strength due to non-uniformity of solder leakage observed in 025) did not occur at all.

As is clear from the above, according to Example (1), it is possible to easily realize a solder fixing structure in which the void ratio is dramatically reduced and the leakage is excellent. Therefore, by applying the present invention to solder bonding between a semiconductor chip and a heat sink, it is possible to enhance the heat dissipation effect and significantly improve the thermal performance and reliability of the semiconductor device.

Next, the fact that the controllability of the solder joint thickness t in Example (1) is extremely high will be explained below based on the principle of the present invention.

FIG. 5 is an explanatory diagram of the principle of the present invention, which has already been shown in steps (b) and (d) in FIG.

The dimensions of each part are as shown in Fig. 5 (a) and (b).
Assuming that o is the thickness of the solder preform, t is the thickness of the solder fixation layer, d is the width of the band-shaped part of the solder preform, and 2r is the length of the side surface of the solder preform, the following linear relational expression is obtained. .

FIG. 5(e) is a graph of the relationship expressed by equation (1). In the embodiments described above, - by way of example, t o=1
00 μm, r = 5 mm, and d = 1 + * + *. Therefore, according to equation (1), t>36μm,
This was in good agreement with the actually measured values of 30 to 40 μm obtained from a plurality of samples. That is, since the void ratio finally obtained is as small as about 1% at most, the solder joint thickness can be controlled with extremely high accuracy based on equation 1 (1,).

This effect can be fully exploited in accurately controlling the solder joint thickness and designing optimal thermal and mechanical properties.

The above effect is based on the principle of void rate reduction according to the present invention, and its physical basis will be explained below. The principle of the present invention utilizes the Boyle-Charles law. As shown in FIG. 5(a), the change in the volume V of the region 17 sealed in the solder preform 13 (v1→V 2 )
maintains the following relationship (Boyle-Charles law) with the change in pressure P (pt→P2).

The table below shows changes in the state of the sealed area 17 in the order of the steps shown in FIGS. 1(b) to 1(d).

Here in the example - as an example, P 1 = I T
arryP2=760 Torrt T1=220°C (heating temperature).

T2 = 183℃ (solder melting point), T3 = 250℃ (room temperature)
And so. Step (d) includes a temperature change (T2→T3) to room temperature after solder solidification (referred to as step (d')).

As is clear from the above description, this is the void volume of the solder joint finally obtained in Example (1). That is, by determining the volume V of the region 17 shown in FIG. 1, the final void ratio can be controlled.

Embodiment (2) In the embodiment (1), a solder fixation structure between a single solder pellet and a heat sink is realized. The effectiveness of the present invention was demonstrated above. This was an example of a case where the weight of the pellets was relatively small and the surface to which the pellets were fixed was flat.

On the other hand, in the embodiment (2) shown in FIG. 6, cooling blocks (25
) is related to a voidless solder fixing structure of a so-called multi-chip cooling module. This embodiment will be explained below with reference to FIGS. 6 to 8.

FIG. 6(a) shows a multi-chip cooling module similar to that disclosed in JP-A-60-94749, ``Integrated Circuit Chip Cooling Apparatus''.

The cooling module 21 has a function of enclosing the S 1-LS I chip 22 and cooling it.

The Si chip 22 is connected to the circuit board 24 via solder bumps 23.
It is connected to the. Fins (not shown) are provided inside the cooling block 25 and are connected to the cooling channel 27 by a bellows 26 . In other words, the exit 28
The Si chip 22 and the cooling block 25, which has the function of removing heat from the cooling block 25 by flowing cooling water between the Si chip 22 and the cooling block 25, are fixed by solder 29. FIG. 6(b) is a perspective view of the cooling block 25 attached to the Si chip 22.

In the cooling module 21, a method of performing voidless solder bonding on a plurality of chips at once using the principle of the present invention will be described below.

As can be easily inferred from the structure of the cooling module shown in FIG. Variations occur in the gap between the Si chip 22 and the Si chip 22.

Therefore, when fixing the solder, it was necessary to apply an appropriate vertical load to the cooling block 25 and bring it into contact with the chip 22 through the solder layer. However, according to the inventors' experiments, 1
For example, if a vertical load of 20 to 30 g/c 2 is applied during melting of P b -S n 5 wt% solder, Si chip 2
An inconvenience occurred in that most of the molten solder flowed out around No. 2.

FIG. 7 is a diagram illustrating a process for solving this problem and enabling voidless solder fixation according to the present invention.

That is, by providing the projections 30 on the fixed surface of the cooling block 25, the molten solder 29 is prevented from flowing out. Further, the same effect could be achieved by installing a spacer having a predetermined thickness, for example, 50 μm, on the fixing surface.

7(a), (b), and (c) correspond to steps (a), (b), and (C) of FIG. 1. Figure 7 (b
), when a vertical load W (indicated by an arrow) is applied and the tip of the protrusion 30 is in contact with the Si chip 22, a suitable gap (30 to 50 μm) is created to prevent the solder from flowing to the surrounding area. could be prevented. In FIG. 7(C), voidless solder fixation was easily realized according to the principle of the present invention explained in step (c) of FIG. 1.

FIG. 8 shows a modified example in which a spherical surface is used as the non-flat surface, and steps (a), (b), and (e) are similar to (a) in FIG.
), (b), and (c). In this example, even when the solder fixation surface is inclined, a relatively high quality fixation structure can be obtained, and therefore, it has the effect of widening the allowable range of assembly accuracy of the component parts.

Furthermore, as explained in FIGS. 7 and 8.

The effect that the thickness of the solder used as intermediate fi can be uniquely determined with good controllability by installing a spacer on the fixing surface or by using a structure having the same function as a spacer, such as a fixing surface with a protrusion or a spherical surface. was there.

From the results of Example (2) above, it is clear that the voidless solder fixing method according to the present invention can be applied to members having non-flat fixing surfaces. That is, Example (2)
In the above, a non-flat surface with protrusions 30 etc. was intentionally adopted due to the necessity of vertical load, but in view of the demand for increasing the diameter of the Si chip and increasing the mechanical tolerance of the constituent members, the non-flat surface according to the present invention was adopted. It is obvious that voidless solder fixation technology for flat surfaces can be applied to a wide range of applications and can have universal effects. The effect of the present invention observed in Example (2) is similar to that of the prior art (A) and (B) described above.
It will be easily understood that it is extremely difficult to realize this.

In the embodiments (1) and (2) described above, a solder preform was used as an example of an intermediate machine, but any material that satisfies the requirements of the present invention that the solder material is provided in the area along the outer periphery of the solder joint surface may be used. For example, it is obvious that the effects of this embodiment can be enjoyed regardless of the type, shape, and installation method of the solder material and the members to be joined. Furthermore, in an application example in which the purpose is to densely fill a bonding agent as an intermediate agent into a bonding surface between members, the effect of the present invention is obtained only if the bonding agent has fluidity when the pressure of the atmosphere changes. This is a necessary condition for its realization. That is, it goes without saying that the effects of the present invention can be fully exerted even when using a bonding agent other than a solder material that satisfies the above requirements, such as an organic resin.

In the above embodiment, the method of obtaining the pressure ratio is to first reduce the pressure (
A method was used in which the pressure was set to Pl) and then returned to normal pressure (P2). The void ratio reduction effect, which is the key point of the present invention, is the pressure ratio P x
/ P z As is clear from the fact that the initial pressure P1 is set relative to P2, it does not necessarily have to be specified as in the above embodiment. therefore.

Pl may be set in consideration of operational convenience. For example, if Pl is set to normal pressure (760 Torr), P2 may be set to pressurization (>760 Torr) to obtain the same result as in the above embodiment. effect can be obtained.

〔Effect of the invention〕

According to the present invention, the void ratio is dramatically reduced, and
A solder-fixed structure with excellent leakage properties can be realized with good controllability. Furthermore, fluxless solder fixation is possible due to the effect that the surface oxide film is broken and the intrinsic solder flows into the bonding surface. Therefore, especially when applied to fixing a semiconductor chip and a heat sink substrate, it is possible to reduce thermal resistance and increase bonding strength, which has the effect of significantly improving device performance and reliability. Furthermore, there is an effect that it is possible to easily realize a solder-fixed structure in which solder does not flow out or scatter from the joint surface even under a practically required load.

[Brief explanation of drawings]

Fig. 1 is a process explanatory diagram of the first embodiment of the present invention, Fig. 2 is a diagram illustrating the effects of the embodiment, Fig. 3 is a micrograph showing a soft X-ray transmission image of a solder-fixed sample, and Fig. 4 5 is a diagram explaining the state in which the intrinsic solder flows by breaking the oxide film, FIG. 5 is a diagram explaining the present invention in detail, FIG. 6 is a diagram explaining the second embodiment, and FIGS. 7 and 8 The figure is a process explanatory diagram of the second embodiment. It, 22... Silicon chip, 12.15... Metallized layer, 14... Heat sink. 17... Internal area, 25... Cooling block.

Claims (1)

[Scope of Claims] 1. In a method for manufacturing a composite structure in which a plurality of members are formed via an intermediate material, the spatial region formed by the opposing surfaces of each of the members is confined so as to confine the spatial region. The intermediate material is placed along the outer circumferential region, the intermediate material is placed under a predetermined pressure, and if necessary, a means is taken to increase fluidity, and then the pressure is increased to move the intermediate material into the spatial region. A method for producing a composite structure, characterized by causing the structure to flow inwards. 2. In the manufacturing method according to claim 1,
A method for manufacturing a composite structure, wherein the thickness of the intermediate material is determined by the shape of a spacer provided in advance between the plurality of members or a structure having an equivalent function.