JP4246437B2 - Manufacturing method of probe with built-in element - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method and system for inspecting a semiconductor element such as a wireless chip, in particular, a high-frequency compatible semiconductor element that has a great adverse effect due to a long probe needle.
[0002]
[Prior art]
A wafer is provided with a large number of LSI semiconductor elements (chips) on its surface and is used separately. Further, a large number of electrodes or solder balls for connection to an external substrate are arranged on the surface of the semiconductor element.
[0003]
An inspection device is used to industrially produce a large number of such semiconductor elements and to inspect their electrical performance. This inspection apparatus is composed of a probe card and a probe made of a tungsten needle obliquely projected from the probe card. In the inspection by this apparatus, a method of inspecting the electrical characteristics by rubbing the electrode or solder ball for connecting the wafer by contact pressure using the deflection of the probe made of a tungsten needle is used.
[0004]
As an inspection method and an inspection apparatus capable of inspecting characteristics of a semiconductor element when an operation test using a high-speed signal is required as the density and pitch of the semiconductor element are further increased as described above, Japanese Patent Application Laid-Open No. Sho 64 A technique described in Japanese Patent No. 711141 is known. This technique uses a spring probe having a shape in which two movable pins urged by springs so as to protrude in opposite directions are fitted into a tube so as to be freely retractable. That is, the inspection is performed by bringing the movable pin on one end of the spring probe into contact with the electrode of the inspection object and bringing the movable pin on the other end into contact with a terminal provided on the substrate on the measurement circuit side. .
[0005]
[Problems to be solved by the invention]
In the above prior art, it is common to inspect by attaching a probe needle made of tungsten or the like to a probe card. However, when the probe needle becomes long, a problem of crosstalk occurs in a high-frequency compatible semiconductor element. Moreover, it is desirable that the terminal to be measured and the ground are close to each other, but it is difficult to obtain such a structure when the probe is drawn with a long probe needle.
[0006]
  An object of the present invention is to make it possible to check in an operating state, for example, an inspection of a high-frequency wireless chip that is a core component of a communication module, in order to solve the above-described problemsDoBuilt-in probeManufacturing methodIs to provide.
[0007]
[Means for Solving the Problems]
  In order to achieve the above object, the present invention provides a probe with a built-in element in which a probe needle for use in testing a semiconductor element and an inspection circuit for checking operation are integrated.Manufacturing methodIt is characterized by.
[0010]
  That is, the present invention includes a first insulating layer, a first wiring layer formed on the first insulating layer, a second insulating layer formed on the first insulating layer and covering the first wiring layer, A second wiring layer formed on the second insulating layer and electrically connected to the first wiring layer through the second insulating layer; and an upper surface of the second wiring layer formed on the second insulating layer. A wiring board having a third insulating layer having an exposed opening; a probe needle implanted in the first wiring layer of the wiring board and projecting downward from the first insulating layer; and the second wiring A method for manufacturing a probe with a built-in element comprising electronic components and terminals electrically connected to each layer,
  The manufacturing method includes:
  A first step of connecting the electronic component and the terminal by solder to the upper surface of the second wiring layer exposed from the third insulating layer through the opening;
  A second step of covering the electronic component and the terminal with a mold resin and curing the mold resin;
  By polishing the upper surface of the mold resin, a third step of exposing the upper surface of the terminal from the mold resin in the state where the electronic component is embedded in the mold resin is performed in this order.Yes,
  The probe needle is inserted into a hole formed from the first insulating layer through the first wiring layer to the second insulating layer after the third step and filled with a solder paste.It is characterized by that.
  In the method of manufacturing a probe with a built-in element according to the present invention, the electronic component is one of the second wiring layers connected to the electronic component, the first wiring layer connected to the one second wiring layer. Through one wiring layer and the other one of the second wiring layers connected to the first wiring layer, electrically connected to the terminal joined by soldering to the upper surface of the other second wiring layer It is characterized by being.
  Further, the present invention is the method for manufacturing an element-embedded probe, wherein the probe needle includes the first wiring layer in which the probe needle is implanted, and one of the second wiring layers connected to the first wiring layer. And is electrically connected to the terminal joined by solder to the upper surface of the one second wiring layer.
  According to the present invention, in the method of manufacturing an element-embedded probe, an underfill is injected between the third insulating layer and the electronic component between the first step and the second step. An electronic component is fixed to the wiring board.
  The present invention is also characterized in that, in the method for manufacturing a probe with a built-in element, a cable is soldered to the upper surface of the terminal exposed from the mold resin.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a method for performing a characteristic inspection including an operation test of a chip to be inspected composed of, for example, a high-frequency compatible analog semiconductor element (wireless chip) according to the present invention and an element-embedded probe used therefor will be described with reference to the drawings. .
[0015]
An inspection system for performing an operation and characteristic inspection of an analog semiconductor device (wireless chip), for example, corresponding to a high frequency according to the present invention is configured as shown in FIG. That is, this inspection system is basically performed on a wafer on which a wafer level CSP (chip scale package) is formed as the chip 1 to be inspected. This is because the prober with a built-in element formed by this method requires machining in the probe needle mounting process, as will be described later, and it is difficult to reduce the pitch of the probe needle beyond its processing limit. It is. Of course, when the chip to be inspected 1 has a small number of pins, it is possible to directly probe the receiving wafer. In this inspection, the receiving wafer is inspected using the element built-in probe 10 after the wafer level CSP is formed. For wafers, thinning the wafer in a back grinding process (back polishing process) is widely performed, but this inspection may be performed either before or after the back grinding process.
[0016]
As shown in FIG. 1, for example, a chip 1 to be inspected according to this inspection system is called Bluetooth (a revolutionary new wireless chip (using 2.4 GHz band) developed by cooperation of the computer and communication industries). It is intended for a core electronic component of a wireless device composed of a high-frequency compatible analog semiconductor element. This chip 1 to be inspected is, for example, Bluetooth, 2.45 GHz radio 2, RAM 3, DSP (digital signal processor) 4, μP (microprocessor) 5, computer 32 and flash memory 11 which is a nonvolatile memory. And I / O 6 for inputting and outputting signals via probe needles 19a and 19h.
[0017]
Therefore, for example, the element built-in type probe 10 includes a 4 Mbit flash memory 11, a crystal oscillator 12, an LNA (low noise amplifier) 14, a balun (amplifier) 13, an RF switch 15, and a BPF (bandpass filter). ) 16, and further, power supply wirings 17 a and 17 b are formed, and signal wiring to the computer 32 (immediately after being output from the chip 1 to be inspected is an RF signal) 18 is formed, and the flash memory (software Wear stack) 11, crystal oscillator 12, balun 13, LNA 14, power supply wiring 17 and signal wiring 18 and probe needles 19 a to 19 h that connect to the chip 1 to be inspected are formed, and electrodes connected to the power supply 20 Alternatively, via the terminals 24b and 24c, the evaluation computer 31, and the communication cable (coaxial cable, optical cable, etc.) 23a. Configured to form an electrode or a terminal 24d is connected via the communication cable 23b to the electrodes or terminals 24a and computer 32 is continued. The power supply wiring 17b is a ground wiring (ground wiring). The electrode or terminal 24 includes a connector.
[0018]
The power supply 30 supplies power to the chip 1 to be inspected through power supply wires 17a and 17b formed in the element built-in probe 10 through the power cable 23c. The power supply wires 17a and 17b are also supplied with power to the electronic components required by the power supply in the element-embedded probe 10. The power supply wiring 17b is a ground wiring (ground wiring). The evaluation computer 31 performs the test based on the RF signal obtained through the LNA 14 or the balun 13, the RF switch 15 and the BPF 16 built in the element built-in type probe 10 as a result of the signal processing performed on the chip 1 to be tested. It evaluates the operation and characteristics of the chip. The computer 32 provides a test signal as a digital signal to the chip 1 to be inspected.
[0019]
With the above configuration, first, as shown in FIG. 3 and FIG. 4, each of the chips to be inspected arranged on the wafer level CSP 50 on which the probe needle 19 of the element built-in type probe 10 is placed on the holder 71 on the XYZθ stage 70. It is inspected by evaluating the operation and characteristics of the chip to be inspected by bringing it into contact with one solder bump 60 (not necessarily the solder bump 60). That is, the wafer level CSP 50 is inspected using the element built-in type probe 10 formed in the present invention.
[0020]
Incidentally, the XYZθ stage 70 is configured to be movable in the X direction, the Y direction, the Z direction, and the θ (rotation) direction. The relative positioning between the element built-in type probe 10 and each chip 1 to be inspected arranged on the wafer level CSP 50 is performed by controlling the XYθ stage. The probe needle 19 of the element-embedded probe 10 is brought into contact with, for example, the solder bump 60 of each chip 1 to be inspected arranged on the wafer level CSP 50 by, for example, raising the Z stage. The contact pressure at this time can be obtained by an upward pressure increase of the Z stage or a pressure applied to the element built-in type probe 10 or a probe card (holding substrate) 35 to which the probe 10 is attached.
[0021]
In the case shown in FIG. 4, a plurality of element built-in probes 10 are attached to a probe card (holding substrate) 35 in accordance with the interval between the plurality of chips 1 to be inspected arranged on the wafer level CSP 50.
[0022]
In this way, the test signal is output from the computer 32 with the element built-in probe 10 electrically connected to the chip 1 to be inspected, and the signal wiring formed on the element built-in probe 10 through the communication cable 23b. 18 and the probe needle 19h are input to the chip 1 to be inspected. The chip to be inspected 1 receives an oscillation signal of, for example, 16 MHz from the crystal oscillator 12 through the probe needle 19b, and is connected to the flash memory 11 provided in the element built-in probe 10 based on the test signal. Thus, signal processing is performed by transferring data through the probe needle 19a. The result of signal processing by the chip 1 to be inspected is input as an analog signal to the LNA 14 and the balun 13 of the probe 10 with built-in element via the probe needles 19c to 19e, and further selected by the RF switch 15 and RFed through the BPF 16. A signal is transmitted to the evaluation computer 31 via the electrode or terminal 24a and the communication cable 23a, and the operation and characteristics of the chip 1 to be inspected are evaluated in the evaluation computer 31. That is, the flash memory 11, the balun 13, the LNA 14, the RF switch 15, and the BPF 16 that are integrally incorporated in the element built-in type probe 10 constitute an inspection circuit that confirms the operation of the chip 1 to be inspected.
[0023]
Next, the structure of the chip 1 to be inspected will be specifically described. FIG. 2 shows a partial cross-sectional view of the chip 1 to be inspected. In this figure, the dimensional ratio of each part is different from the actual one for explanation. The wafer 50 on which the semiconductor circuit as the chip 1 to be inspected is formed is a wafer that has been subjected to the previous process in the semiconductor manufacturing process, and is a semiconductor chip that has not been divided and cut. Each semiconductor chip, which is the chip 1 to be inspected, has a pad 54 made of aluminum or the like. When the semiconductor chip is a semiconductor package such as a QFP (Quad Flat Package), a gold wire is connected to the pad 54 to Conduction with external terminals is realized.
[0024]
The surface of the chip 1 to be inspected is covered with a protective film 55 except for a cut portion on the pad 54 and when the wafer 50 on which a large number of semiconductors are formed is cut into semiconductor chips. For the protective film 55, a photosensitive resin material having a thickness of about 2 to 10 microns is used. The rewiring wiring 56 is formed of a metal such as copper, and is formed on the protective film 55 so as to connect the pad 54 and the bump pad 57. On the bump pad 57, Au is plated as a barrier metal (not shown). The surface of the wafer is covered with a surface protective film 59 except for the bump pad 57 and a cut portion when cutting into a semiconductor chip. As the surface protective film 59, a photosensitive resin is used. On the bump pad 57, solder bumps 60 are formed.
[0025]
Next, a method for manufacturing the semiconductor device that is the chip 1 to be inspected will be described with reference to FIGS. It should be noted that the explanatory diagram is partially extracted so that the cross-sectional structure can be easily understood. Moreover, the figure of the cutting | disconnection to the individual chip | tip performed between the processes shown to Fig.7 (a)-(b) is abbreviate | omitted.
[0026]
Step A shown in FIG.
For example, a semiconductor circuit as shown in FIG. 1 as a chip 1 to be inspected (in the case of a wireless chip, for example, is configured to include a radio 2, a RAM 3, a DSP 4, a μP 5 and an I / O 6). A wafer 58 having a pad 54 made of aluminum or the like for external connection formed on the uppermost layer is manufactured.
[0027]
Step B shown in FIG.
A protective film 55 is formed on the wafer 58 as necessary. This process may be formed as a semiconductor process (pre-process) using an inorganic material, or may be formed using an organic material after the semiconductor process (pre-process) is completed using an inorganic material. There is. In the present invention, photosensitive polyimide, which is an organic material, is applied on the insulating film made of an inorganic material formed in the semiconductor process (previous process) to about 6 microns.
[0028]
Step C shown in FIG.
A power supply film 61 for use in electroplating was formed by a method such as sputtering. First, a power supply film 61 for performing electroplating is formed on the entire surface of the protective film 55 on the semiconductor wafer 58. Here, vapor deposition, electroless copper plating, CVD, or the like can be used. However, since the adhesive strength with polyimide as the protective film 55 is strong, sputtering is used. As a pretreatment for sputtering, sputter etching was performed in order to ensure conduction of the conductor. As the sputtered film, a multilayer film of chromium (about 75 nm) / copper (about 0.5 μm) was formed. The film thickness of chromium here is a film thickness that can be adhered to the copper formed thereon, and the film thickness of copper is the film thickness when electrolytic copper plating and electro nickel plating performed in a later process are performed. A minimum film thickness that does not cause distribution is preferred. Here, when the film thickness of copper is increased more than necessary, when removing the power feeding film 61 performed in a later process, the etching time becomes long, and as a result, the side etching becomes large, so there is a possibility that the specification may not be satisfied. is there.
[0029]
Step D shown in FIG.
A reverse pattern 62 of wiring was formed using a photoresist. That is, the reverse pattern 62 of the wiring opened only by the wiring forming part for rewiring was formed by using a resist by the photolithography technique. As the resist used here, a negative liquid resist was used. Here, a positive resist can be used. However, when the resist is formed, the resist film thickness of the connection portion 67 between the pad and the wiring shown in the step D becomes thick, so the negative type is preferable. Here, a PMER-NCA2000 type resist manufactured by Tokyo Ohka Kogyo Co., Ltd. was used as the resist, and a resist coating device was used to form a resist with a thickness of 15 μm. Next, it exposed with the exposure amount of about 250 mJ using the type of exposure machine with which a mask and a resist closely_contact | adhere. Then, it developed using the resist image development apparatus.
[0030]
Step E shown in FIG. 5 (e) and Step F shown in FIG. 6 (a):
Electroplating is performed using this pattern to form the rewiring wiring 56. Further, the rewiring wiring 56 has a multilayer structure by repeating electroplating as necessary. In this embodiment, the rewiring wiring 56 is made of two layers of electrolytic copper plating 65 and electrical nickel 66, and the terminal on one side is also used as a bump pad. Here, a method of forming a conductor using electroplating for both copper and nickel has been shown, but electroless plating can also be used.
[0031]
Step G shown in FIG. 6B and Step H shown in FIG.
The photoresist used for the reverse pattern 62 of the wiring was removed. Thereafter, the power supply film 61 for use in electroplating was removed. That is, after performing the electrolytic copper plating and the electrolytic nickel plating, the resist pattern is removed, and the power feeding film 61 formed in advance is removed by etching. There are various types of etching of copper, such as iron chloride and an alkaline etching solution. Here, an etching solution mainly containing sulfuric acid / hydrogen peroxide solution was used. The etching time here is difficult to control the film thickness unless the etching time is 10 seconds or more, and there is a concern that side etching becomes large in the case of iron chloride or an alkaline etching solution. Next, as for etching of Cr, here, an etching solution mainly composed of potassium permanganate and metasilicic acid was used.
[0032]
Step I shown in FIG.
A surface protective layer 59 was formed using a photosensitive resin. Then, using this pattern, electroless Au plating (not specifically shown) was performed on the outermost surface of the pad as an antioxidant film. That is, a photosensitive resin in which only the bump pad portion 57 was opened was formed, and then electroless gold plating was performed to form Au on the bump pad portion 57. The surface protective film 59 used here is made of photosensitive polyimide, but is not limited thereto.
[0033]
Step J shown in FIG.
Solder balls 63 were mounted on the pads together with the flux, and the solder balls were connected to the pads by heating to form solder bumps. At this stage, as shown in FIG. 8, it becomes possible to form the chip 1 to be inspected as a wafer level CSP 50 composed of a rewiring layer / insulating layer and solder bumps on a silicon wafer.
[0034]
The solder bump formation can be realized by using a commercially available solder ball mounter and a reflow furnace. That is, the solder ball mounter mounts a predetermined amount of flux and solder balls on the bump pad 57 of the semiconductor wafer. At this time, the solder balls are temporarily fixed on the bump pads by the adhesive force of the flux. By putting the semiconductor wafer on which the solder balls are mounted into a reflow furnace, the solder balls are once melted and then solidified again, thereby forming the solder bumps 60 connected to the bump pads 57 shown in FIG. In addition, there is a method of forming the solder bump 60 by printing and applying a solder paste onto the bump pad 57 using a printing machine and reflowing the paste. In any method, it is possible to select various solder materials, and there is no particularly unusable solder material currently on the market. Moreover, you may use the bump formed using the resin which mix | blended the bump which used the ball | bowl which Au or Cu became the nucleus, and the electrically-conductive material.
[0035]
The rewiring wiring 56 and the bump pad 60 from the aluminum pad 54 to the bump pad 60 and the bump pad 60 are formed on the wafer level CSP 50 as shown in FIG.
[0036]
Next, as described above, as shown in FIG. 3, the probe needles 19 of the element built-in type probe 10 are arranged on the wafer level CSP 50 mounted on the holder 71 on the XYZθ stage 70. For example, it is inspected by evaluating the operation and characteristics of the chip to be inspected by contacting with the solder bump 60 (not necessarily the solder bump 60). That is, the wafer level CSP 50 is inspected using the element built-in type probe 10 formed in the present invention. Here, it is possible to perform probing without dividing the wafer level CSP 50 into chip pieces.
[0037]
Incidentally, the XYZθ stage 70 is configured to be movable in the X direction, the Y direction, the Z direction, and the θ (rotation) direction. The relative positioning between the element built-in type probe 10 and each chip 1 to be inspected arranged on the wafer level CSP 50 is performed by controlling the XYθ stage. The probe needle 19 of the element-embedded probe 10 is brought into contact with, for example, the solder bump 60 of each chip 1 to be inspected arranged on the wafer level CSP 50 by, for example, raising the Z stage. The contact pressure at this time can be obtained by an upward pressure increase of the Z stage or a pressure applied to the element built-in type probe 10 or a probe card (holding substrate) 35 to which the probe 10 is attached.
[0038]
After the inspection, the wafer level CSP 50 was removed from the holder 71 and cut into individual chips in the cutting process.
[0039]
Further, as shown in FIG. 7B, in the above inspection, a non-defective inspected chip 1 is mounted on a printed circuit board 64 together with electronic components similar to the electronic components 11 to 16 mounted on the element built-in probe 10. An analog module for communication will be completed.
[0040]
Next, a method for manufacturing the element-embedded probe 10 according to the present invention will be described with reference to FIGS. For ease of explanation, the dimensional ratio of each part is changed from the actual one.
[0041]
FIG. 9 is a perspective view showing the external appearance of the element-embedded probe 10. Specifically, as shown in FIG. 15, the element-embedded probe 10 is an electronic component (element) (flash memory 11, crystal oscillator 12, balun 13) that constitutes an inspection circuit for inspecting the operation and characteristics of the chip to be inspected. The LNA 14, the RF switch 15, the BPF 16, and the like have an analog circuit.) 11 to 16 are mounted on the wiring board 25, and these electronic components 11 to 16 are covered and molded with the mold resin 20. Probe needles 19a to 19h connected to the wiring in the wiring board 25 connected to the components (elements) 11 to 16, the power supply wirings 17a and 17b, and the signal wiring 18, or more specifically, FIG. As shown in FIG. 4, electrodes or terminals (including connectors) 24a to 24d connected to the wiring in the wiring board 25 connected to the electronic component 16, and specifically It is configured with a mounting bracket 21 as shown in FIG. 18 (d). The probe needles 19a to 19h are implanted in the chip 1 to be inspected of the element built-in type probe 10. As described above, the electronic components (elements) 11 to 16 mounted on the element-embedded probe 10 are electronic components configured together with the chip 1 to be inspected as a core component, for example, as a communication module. Note that the electronic components 13 to 16 can be configured by one or a plurality of chip components. The electrodes or terminals 24a to 24d are connected to a communication cable, a power cable 23, and the like.
[0042]
First, a method for forming the element built-in probe 10 body will be described.
[0043]
10 to 15, in the element built-in type probe 10, one of the built-in electronic components (elements) is connected to the implanted probe needle, and the other is connected to the ground wiring (grounding) in the first layer. The case where it connects to (wiring) is shown typically.
[0044]
Step (1) shown in FIG.
A stainless steel substrate 101 is used as a substrate for manufacturing the wiring substrate 25. An electric nickel plating film 102 is formed thereon. This electro nickel plating film 102 is finally used as a connection terminal and solder diffusion preventing layer for implanting probe needles 19a to 19h with the chip 1 to be inspected. As the film thickness increases, the warp of the stainless steel substrate 101 tends to increase. For this reason, it is better to use a thin film. However, if the film is too thin, it will not function as a solder diffusion preventing layer. A minimum film thickness is required that plays the role of a solder diffusion preventing layer and that allows the stainless steel substrate 101 and the electro nickel plating film 102 to be easily peeled off in the step (14) shown in FIG.
[0045]
Step (2) shown in FIG.
An insulating layer 103 is formed on the electronickel plating film 102 using photosensitive polyimide, and a portion to be a terminal is opened. As the opening method, photosensitive polyimide was used, but there is no problem even if polyimide is applied to the entire surface and a technique such as laser processing or dry etching is used. In addition, although polyimide is used as the material of the insulating layer, there is no problem even if a resin such as epoxy is used. In some cases, an inorganic insulating layer may be used.
[0046]
Step (3) shown in FIG.
A conductor film 104 was formed on the insulating layer 103 by filling the opening (through hole) 103a by sputtering. Here, vapor deposition, electroless copper plating, CVD, or the like can be used, but sputtering is used because of its strong adhesive strength with polyimide. As a pretreatment for sputtering, sputter etching was performed in order to ensure conduction of the conductor. As the sputtered film 104 in this example, as shown in FIG. 21, a multilayer film of chromium (about 75 nm) 104a / copper (about 2 μm) 104b / chromium (about 50 nm) 104a was formed. The function of the chromium here is to ensure adhesion between the copper located above and below the insulating layer 103, and the film thickness may be a minimum to maintain the adhesion. The required film thickness varies depending on sputter etching and sputtering conditions, chromium film quality, and the like. Note that a titanium film, a titanium / platinum film, tungsten, or the like can be substituted for the chromium film used in this embodiment.
[0047]
Step (4) shown in FIG.
A resist wiring pattern 105 is formed on the conductive film 104. The resist needs to be resistant to the etching solution in the etching step shown in step (5) shown in FIG. The chromium etching solution used here is an etching solution mainly composed of potassium permanganate and metasilicic acid, but this etching solution is alkali (pH 13) and oxidizable, so that it has a high chemical resistance. Is required. Here, a rubber-based or novolak-based resist containing a rubber component is preferable.
[0048]
Step (5) shown in FIG.
The conductor film 104 formed in the step (3) shown in FIG. 10C has a three-layer structure including a chromium film 104a and a copper film 104b, as shown in FIG. Therefore, the etching needs to be performed in the order of the chromium film 104a, the copper film 104b, and the chromium film 104a.
[0049]
There are various etching solutions for the chromium film 104a, such as ferricyan acid and hydrochloric acid. In this embodiment, an etching solution mainly containing potassium permanganate and metasilicic acid was used.
[0050]
There are various types of etching of the copper film 104b, such as iron chloride and an alkaline etching solution. In this embodiment, an etching solution mainly containing sulfuric acid / hydrogen peroxide solution was used. If the etching time is short, it is difficult to control and disadvantageous from a practical point of view, but if etching is performed for an excessively long time, there is a problem that side etching becomes large or tact becomes long. It is better to obtain it by experiments as appropriate. Subsequent etching of the lower chromium film was performed in the same manner as the etching of the upper chromium film.
[0051]
In this way, a wiring pattern (chromium (about 75 nm) / copper (about 2 μm) / connected to the portion 28a where the probe needles 19a to 19h are implanted on the insulating layer 103 including the opening (through hole) 103a. Chromium (about 50 nm) is formed. The wiring pattern 28 may be used as a ground wiring 17b for a power source. Thus, when the first wiring layer 28 is used as the ground wiring, the ground wiring is stretched except for the portion where the probe needle 19 is implanted. In this manner, by removing the portion where the probe needle 19 is implanted and extending the ground wiring, it is possible to take noise countermeasures for the high-frequency signal propagated to the second and higher wiring layers 29.
[0052]
Then, the resist pattern 105 used for wiring formation was peeled off. The resist pattern 105 can be peeled by organic alkali type or organic solvent type. The insulating layer 103 formed in the step (2) shown in FIG. 10B and the step (5) shown in FIG. Any stripping solution may be used as long as it does not damage the wiring pattern 28 formed in (1).
[0053]
Step (6) shown in FIG.
On top of that, as in the step (1) shown in FIG. 10A, an insulating layer 106 is formed using photosensitive polyimide, and an opening (through hole) 106a is formed to connect to the wiring pattern 28. . For this opening method, photosensitive polyimide is used, but there is no problem even if polyimide is applied to the entire surface and a technique such as laser processing or dry etching is used. Further, although polyimide is used as the material of the insulating layer 106, there is no problem even if a resin such as epoxy is used. In some cases, an inorganic insulating layer may be used.
[0054]
Step (7) shown in FIG.
A power supply film 108 for performing electroplating is formed on the entire surface of the insulating layer 106 including the opening 106a. Here, vapor deposition, electroless copper plating, CVD, or the like can be used, but sputtering is used because of its strong adhesive strength with polyimide. As a pretreatment for sputtering, sputter etching was performed to ensure electrical connection with the wiring pattern (conductor) 28.
[0055]
As the sputtered film in this example, a multilayer film of chromium (about 75 nm) / copper (about 0.5 μm) was formed. The function of the chromium here is to ensure the adhesion between the copper located above and below the insulating layer 106, and the film thickness may be the minimum to maintain the adhesion. The required film thickness varies depending on sputter etching and sputtering conditions, chromium film quality, and the like. Note that a titanium film, a titanium / platinum film, tungsten, or the like can be substituted for the chromium film used in this embodiment.
[0056]
On the other hand, the copper film thickness is preferably a minimum film thickness distribution that does not cause a film thickness distribution when the electrolytic copper plating film 111 and the nickel electroplating film 112 are formed in the subsequent step (9). The film thickness that does not induce the film thickness distribution is determined after taking into account the amount of film loss caused by pickling. When the copper film thickness is increased more than necessary, for example, when the copper thickness exceeds 1 μm, in addition to the problem that the sputtering time becomes long and the production efficiency decreases, the power feeding performed in the subsequent step (10) When the film 108 is removed by etching, etching is inevitable for a long time, and as a result, side etching of the electrolytic copper plating film 111 and the electrolytic nickel plating film 112 becomes large.
[0057]
Step (8) shown in FIG.
Using the photolithography technique, a reverse pattern of the wiring 29 opened only in the portions where the electrolytic copper plating film 111 and the nickel electroplating film 112 are formed in the step (9) is formed using the resist pattern 109.
[0058]
Step (9) shown in FIG.
A second wiring layer (conductor layer) 29 is formed by electroplating. The conductor layer 29 formed here is composed of an electrolytic copper plating film 111 having a good electric conductivity and an electric nickel plating film 112 which is a solder diffusion preventing film. Note that one end of the electrolytic copper plating film 111 and the electrolytic nickel plating film 112 may also be used as a bump pad 113 described later in step (11).
[0059]
Thus, as shown in the circuit diagram of FIG. 1, the wiring layer 29 of the second layer includes the electrodes of the electronic components 11 to 14 and the probe needles 19a to 19h including the power supply wires 17a and 17b. Between each wiring pattern 28 connected to the portion 28a to be connected, and between the signal wiring 18 and the wiring pattern 28 connected to the portion 28a in which the probe needle 19h is implanted, to connect the electronic components 13-16. This is for connecting the electrodes. Further, as shown in FIGS. 16 and 17B, the second wiring layer 29 includes an electrode or terminal 24a connected to the electrode of the electronic component 16 and an electrode or terminal 24b connected to the power supply wiring 17. 24c, as shown in FIGS. 19 and 20, the electrode or terminal 24d connected to the signal wiring 18 and the mounting bracket 21 as shown in FIG. 18 are also provided.
[0060]
Further, the second wiring layer 29 has a multilayer structure as shown by 29a and 29b in FIG. 22 by repeating the formation of the insulating films 114a and 114b and the electrolytic copper plating film 111 as necessary. It is also possible to do. FIG. 22 schematically shows a case where the wiring layers 28, 29a, and 29b are three layers. Although a conductor composed of a single layer of the copper electroplating film 111 is shown as the second layer, the electronickel plating film 112 may be formed on the second layer and individual wirings of three or more layers in order to unify the process. In addition, the wiring structure can be applied to a multilayer film formed by sputtering as shown in FIG. 21 or a single layer film made of an electrolytic copper plating film 111 as shown in FIG. It becomes possible. In this figure, three layers of wiring are shown, but it is possible to form four or more layers of wiring. In the case of multilayer wiring, the nickel electroplating film 112 may be formed only on the outermost layer, that is, the wiring in contact with the solder ball 121 connected to the electronic component 120 (11 to 16).
[0061]
The electrolytic copper plating film 111 in the step (9) shown in FIG. 11C uses a sulfuric acid / copper sulfate plating solution, washed with a surfactant, washed with water, washed with dilute sulfuric acid, and washed with water, and then the feeding film 108. Was connected to the cathode, and a copper plate containing phosphorus was connected to the anode to form an electrolytic copper plating film 111. The nickel electroplating film 112, which is a solder diffusion preventing film, was formed by connecting the power supply film 108 to the cathode and connecting the nickel plate to the anode. If the surface is washed with a surfactant, washed with water, washed with dilute sulfuric acid, or washed with water before forming the electronickel plated film, an electronickel plated film with good film quality may be obtained. In addition, although the method of forming a conductor using electroplating was shown for both copper and nickel, electroless plating can also be used. Further, the electroplated copper film 111 may include gold or silver in addition to copper, and the electronickel plated film 112 which is a solder diffusion preventing film may be a nickel alloy.
[0062]
Step (10) shown in FIG.
The reverse pattern 109 of the wiring formed using the resist and the feeding film 108 for electroplating are removed by etching. After the electrolytic copper plating film 111 and the nickel electroplating film 112 are formed, the wiring reverse pattern 109 using a resist is removed, and an etching process is performed to form a power supply formed in step (7) shown in FIG. The film 108 is removed. There are various types of copper etching, such as ferric chloride and alkaline etching solution. In this example, an etching solution mainly composed of sulfuric acid / hydrogen peroxide solution was used. If the etching time is not longer than 10 seconds, it is difficult to control and disadvantageous from a practical point of view. However, if etching is performed for an excessively long time, there is a problem that the side etching becomes large or the tact time becomes long. The etching conditions are preferably obtained by experiments as appropriate. Subsequent etching of the chromium portion of the power feeding film 108 was performed in the same manner as in step (5) shown in FIG.
[0063]
Step (11) shown in FIG.
The cover coat 114 is formed using photosensitive polyimide, and the electrodes or terminals connected to the electrodes of the electronic components 120 (11 to 16) via the solder balls 121, as shown in FIG. 16 and FIG. The electrode or terminal 24a connected to the electrode of the component 16 and the electrodes or terminals 24b and 24c connected to the power supply wiring 17, and the electrode or terminal 24d connected to the signal wiring 18 as shown in FIG. 19 and FIG. As shown in FIG. 18, a portion for providing the mounting bracket 21 is opened. As the opening method, photosensitive polyimide was used, but there is no problem even if polyimide is applied to the entire surface and a technique such as laser processing or dry etching is used. Here, photosensitive polyimide is used as the cover coat 114, but it is also possible to form the cover coat 114 using a material such as a solder resist or printing polyimide in addition to the photosensitive polyimide. Although not particularly illustrated, electroless Au plating was performed on the outermost surface of the pad using this pattern.
[0064]
Step (12) shown in FIG.
In this step (12), step (12) shown in FIGS. 16A and 18A is also executed.
[0065]
Electronic components 120 (11 to 16) are mounted on wiring board 115 formed in the steps shown in FIGS. A method for mounting the electronic component 120 is generally to form the solder ball 121 on the electronic component side. The solder ball 121 is formed on the electronic component 120, mounted on the bump pad 113 together with the flux, and heated. As a result, the solder balls 121 are connected to the bump pads 113. However, it is also possible to form the solder balls 121 on the side of the wiring board 115 formed in the steps shown in FIGS. A predetermined amount of flux and solder balls are mounted on the bump pads 113. At this time, the solder balls are temporarily fixed on the bump pads by the adhesive force of the flux. The wiring board 115 or the electronic component 120 formed in the process shown in FIG. 10 and FIG. 11 on which the solder ball is mounted is put into a reflow furnace so that the solder ball is once melted and then solidified again, so that the solder ball 121 is obtained. Is mounted, and the electronic component 120 is mounted thereon.
[0066]
In addition to supplying solder with solder balls, there is a method of forming solder bumps by printing and applying solder paste onto the bump pads 113 using a printing machine and reflowing the solder paste. In any method, various solder materials can be selected, and many of the solder materials currently available on the market can be used. In addition, although a solder material is limited, there is a method of forming a solder bump by using a plating technique. Further, a bump using a ball having gold or copper as a core or a bump formed using a resin containing a conductive material may be used. In the present embodiment, the required film thickness of the electro nickel plating film 112 is determined depending on the thickness of the diffusion layer formed by solder diffusion, and the condition varies depending on the type of solder and the reflow conditions. As for the reflow conditions when the solder balls were mounted, a belt-type reflow furnace was used, and the reflow was performed for 30 seconds at a maximum temperature of 245 ° C. and 230 ° C. or higher. The solder balls used were composed mainly of Sn and Cu and added with Bi and Ag as the third component.
[0067]
As described above, after the step (12) shown in FIG. 12 (a) and the step (12) shown in FIGS. 16 (a) and 18 (a) are completed, the process proceeds to the next step (13). Become.
[0068]
Step (13) shown in FIG.
An underfill 122 is injected between the surface of the wiring board 115 and the mounted electronic component 120. After the injection, heat curing is performed. Here, an underfill 122 made of an epoxy resin was used, and after the injection, it was cured by heating at about 200 ° C. for about 60 minutes. Note that when the electronic component is small, the underfill 122 is not necessarily required.
[0069]
After filling the underfill 122, as shown in FIG. 12B, the wiring board 115 and the electronic component 120 into which the underfill 122 is injected, the electrode or terminal 24 shown in FIG. 16B, and FIG. 18B are shown. The mounting bracket 21 is covered with a mold resin 20 by molding and curing. The mold resin 20 used a transfer mold method. As the mold resin, a mold resin made of an epoxy resin was used. After the injection, the mold resin was molded at about 200 ° C. in about 3 minutes, and then secondarily cured at about 170 ° C. for about 8 hours. As a result, the electronic components (elements) 120 (11 to 16), the electrodes or terminals 24, and the mounting bracket 21 are mounted on the wiring board 115, and are protected by the mold resin 20 and incorporated.
Next, the polishing step (14) shown in FIGS. 16 (c) and 18 (c) is entered. In addition, you may put a grinding | polishing process (14) after the following process (15).
[0070]
Step (15) shown in FIG.
Thereafter, the stainless steel substrate 101 was peeled off. For this purpose, it is necessary to prevent the stainless steel substrate 101 and the electronickel plating film 102 from being peeled off during the steps shown in FIGS. 10 and 11, and for that purpose, like the circled portion in FIG. It is preferable that the stainless steel substrate 101, the electric nickel plating film 102, and the insulating layer 103 are disposed, and the insulating layer 103 is bonded to the stainless steel substrate 101 so as to cover the electric nickel plating film 102.
[0071]
Step (16) shown in FIG.
Using the resist 125, a pattern 125a for forming the probe needle base 126 was formed on the nickel electroplating film 102 by using copper electroplating. Note that the pedestal 126 does not require these steps when a large force is not applied to the probe needle 19 (steps (16) to (18) shown in FIGS. 13A to 13C).
[0072]
Step (17) shown in FIG.
The resist 125 formed for forming the probe needle pedestal 126 on the electric nickel plating film 102 is peeled off using electrolytic copper plating. There are various types of resist stripping, such as organic alkali type and organic solvent type, but any stripping solution may be used as long as it does not damage the mold resin 20.
[0073]
Step (18) shown in FIG.
The electronickel plating film 102 formed in the step (1) was etched as shown in the figure. In this etching, a ferric chloride solution was used. The ferric chloride etches not only the nickel electroplating but also the probe needle base 126 formed in the step (18). However, by increasing the thickness of the pedestal 126 of the probe needle, it can be prevented from being burned out by etching. Although not shown here, it is possible to form a resist on the probe needle base 126 using a dispenser and perform etching, or to form a resist by a photo process, although the number of processes increases. It is preferable for forming an accurate pattern.
[0074]
Step (19) shown in FIG.
A hole 130 for attaching the probe needle 19 (19a to 19h) is formed by machining. Here, the solder paste 131 filled in the step (20) forms a slightly larger hole so that the solder fixes the probe needle 19 as shown when the probe needle 19 is inserted in the step (21). did. The size is such that the gap between the hole 130 and the probe needle 19 passes through the particles in the solder paste.
[0075]
Step (20) shown in FIG.
The solder paste 131 is filled into the hole 130 processed in the step (19). Since the probe needle is fixed by solder at the base portion of the needle 19 as shown in FIG. 14C, the solder paste 131 does not necessarily need to be filled up to the bottom portion of the hole 130.
[0076]
Step (21) shown in FIG.
The probe needle 19 (19a to 19h) was inserted into the attachment hole 130. Here, the manufacturing method of the inserted probe needle 19 will be described later.
[0077]
Step (22) shown in FIG. 15:
The solder paste 131 was melted by using a belt-type reflow furnace and reflowing at a maximum temperature of about 245 ° C. and about 230 ° C. for 30 seconds. Moreover, the used solder paste 131 was composed of Sn and Cu as main components and Bi and Ag as third components. However, in this case, reflow is not necessarily required, and heating using a hot plate may be used. Also. Unlike the reflow at the time of component mounting described in the step (12) shown in FIG. 12 (a), the heating here increases the positional accuracy in the vertical direction by boiling up the organic component in the solder paste and pushing up the probe needle 19. In order to ensure, it is preferable to heat gradually.
[0078]
Next, a method for forming the electrodes or terminals 24 (24a to 24d) will be described with reference to FIGS.
[0079]
In the step (12) shown in FIG. 16A, the electrodes or terminals 24 (24a to 24d) are connected to the power supply wirings 17a and 17b, the wirings connected to the electronic components 13 to 16 and the wirings 29 including the signal wirings 18. In order to take out to the upper part, this electrode or terminal 24 is connected to each wiring 29 using solder. 16 and 17 show the case where the electrode or terminal 24 (24b, 24c) is connected to the power supply wirings 29, 28 (17a, 17b) using solder. The step of connecting the electrode or terminal 24 to each wiring 29 is performed in the step of mounting the electronic component 120 (11 to 16) in the step (12) shown in FIG.
[0080]
The process shown in FIG. 16B is the same as the molding process (13) shown in FIG. It is preferable that the mold resin 20 on the upper surface of the electrode or terminal 24 be as thin as possible. However, the mold resin 20 on the upper surface of the electrode or terminal 24 can be eliminated by bringing the upper surface of the electrode or terminal 24 into close contact with the contact surface between the fixed mold and the movable mold constituting the mold. The next polishing step can be eliminated.
[0081]
Step (14) shown in FIG. 16C is a polishing step for removing the mold resin covering the upper surface of the electrode or terminal 24. This polishing step can be performed after the molding in the step (13), but can also be performed after the stainless steel plate 101 in the step (15) is peeled off as shown in the figure.
[0082]
The steps shown in FIG. 17A are steps (16) to (22) for implanting the probe needle 19 in the element-embedded probe 10 as shown in FIGS.
[0083]
Step (23) shown in FIG. 17B is a step of attaching the communication cable or power cable 23 (23c) to the electrode or terminal 24 (24b, 24c) exposed in step (14) using solder 135 or the like. is there. The communication cable 23 a is connected to an evaluation computer 31 that evaluates the operation and characteristics of the chip 1 to be inspected, the communication cable 23 b is connected to a computer 32 that transmits a test signal, and the power cable 23 c is connected to the DC power supply 30. Is done.
[0084]
Next, a method for forming the attachment fitting 21 (attachment method) will be described with reference to FIG. That is, the steps shown in FIGS. 18 (a) to 18 (c) are the same as those shown in FIGS. 16 (a) to 16 (c), in which the mounting bracket (in this case, the screw hole may be closed) 21 or the mounting bracket 21. The component that is the base of the mounting bracket is connected to the wiring 29 for mounting using solder, then molded with the mold resin 20, and then the surface is polished to expose the mounting bracket 21 or the upper surface of the component that is the base of the mounting bracket 21. It is a process. That is, the steps shown in FIGS. 18A to 18C are steps in which the mounting bracket 21 or a component that is the base of the mounting bracket 21 is provided on the wiring 29 for mounting.
[0085]
In addition, when the component used as the origin of the attachment metal fitting 21 is attached, as shown in FIG.18 (d), it is necessary to form the screw hole for attachment in the said component by machining, for example. In the figure, the screw hole does not penetrate, but there is no problem even if it penetrates.
[0086]
Mounting the element-embedded probe 10 directly or via a probe card (holding substrate) 35 using the mounting bracket 21 described above to a probe machine having an XYZθ stage 70 as shown in FIG. Become.
[0087]
Next, another embodiment of a method for connecting a communication cable and / or a power cable to the electrode or terminal 24 will be described with reference to FIGS. 19 and 20. As shown in FIG. 17B, it is possible to connect the communication cable and the power cable 23 to the electrode or terminal 24 using solder 135, but the electrode or terminal formed as shown in FIGS. It is also possible to attach and connect terminals using the mounting bracket 21 formed as shown in FIG.
[0088]
FIG. 19A shows a stage where the electrode or terminal 24 and the mounting bracket 21 are completed.
[0089]
The process shown in FIG. 19B is the same as the process shown in FIGS. 13A to 13C, and the same shape as the probe needle base 126 is completed.
[0090]
The step shown in FIG. 19C is a step of forming the hole 130 for inserting the probe needle and the hole 140 for inserting the terminal using machining.
[0091]
The process shown in FIG. 20A is a process in which the probe needle 19 is inserted into the hole 130 and fixed using the solder paste 131 and then connected to the electrode 24 of the communication cable and / or the power cable 23. For connection to the electrode 24, the terminal 23 ′ of the communication cable and / or the power cable 23 is inserted into the insertion hole 140 and connected by the solder 143, and the holder 141 attached to the end of the cable 23 is attached to the mounting bracket 21. Fix using screws 142 or the like. Of course, by providing the holder 141 with a connector, it is possible to connect the cable 23 and the electrode or terminal 24 with a connector.
[0092]
Next, a method for manufacturing the probe needle 19 will be described with reference to FIG.
[0093]
First, as shown in FIG. 23A, a needle-like probe material 150 made of tungsten is placed on a block 151 for supporting the probe material 150 as shown in the drawing. Next, since the surface of the needle-like probe material 150 made of tungsten is oxidized and soldering is difficult, as shown in FIG. 23B, after performing the sputter etching to remove the oxide film on the surface, Subsequently, a chromium film 152 / copper film 153 is formed. Then, by removing the needle-like probe material 150 made of tungsten thus formed from the block 151, the probe needle 19 is inserted into the insertion hole 130 formed in the wiring board 25 and fixed with the solder paste 131. It becomes possible to do.
[0094]
The element built-in type probe 10 shown in FIG. 9 is completed by the manufacturing method described above. Of course, as shown in FIG. 4, by attaching a plurality of element-incorporated probes 10 to the probe card 35, it becomes possible to simultaneously inspect a plurality of chips 1 having a wafer level CSP 50 shape.
[0095]
As described above, according to the embodiment of the present invention, the RF or the like is provided on the wiring board 25 in which the electrodes or terminals (including connectors) 24 for connecting the probe needle 19, the communication cable, and the power cable are implanted. For example, a wireless chip (corresponding to a high frequency) is used as a core component of a communication module by using an element-incorporated probe 10 formed by mounting a non-volatile memory element such as a flash memory or the like and protecting it with a mold resin 20. It has become possible to inspect the operation and characteristics of a chip to be inspected such as a semiconductor device.
[0096]
In addition, according to the embodiment of the present invention, it is possible to shorten the probe needle in the element built-in type probe, and it is suitable for inspection of a high-frequency compatible semiconductor element that has a large adverse effect due to the long probe needle length. It becomes possible.
[0097]
【The invention's effect】
According to the present invention, for example, it is possible to check an inspection of a wireless chip that is a core component of a communication module in an operating state.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram showing an embodiment of an inspection system for performing an operation and characteristic inspection of an analog semiconductor device (wireless chip) compatible with, for example, high frequency according to the present invention.
FIG. 2 is a view showing a partial cross section of a chip to be inspected according to the present invention.
FIG. 3 shows a state in which a probe needle of a probe with a built-in element according to the present invention is brought into contact with, for example, solder bumps of chips to be inspected arranged on a wafer level CSP placed on a holder provided on an XYZθ stage. It is a perspective view shown.
FIG. 4 shows a probe card (holding) according to the interval between a plurality of chips to be inspected arranged on a wafer level CSP placed on a holder provided on an XYZθ stage. It is the front view which showed the case where it attaches and comprises on a board | substrate.
FIGS. 5A to 5E are views showing steps A to E of a method for manufacturing a wafer level CSP in which chips to be inspected according to the present invention are arranged.
FIGS. 6A to 6E are diagrams showing steps F to I of a method for manufacturing a wafer level CSP in which chips to be inspected according to the present invention are arranged.
7A is a diagram showing a process J of a manufacturing method of a wafer level CSP in which chips to be inspected according to the present invention are arranged, and FIG. 7B is a diagram in which a non-defective chip to be inspected is mounted on a printed circuit board. It is a figure for demonstrating the state which creates the module for communication.
FIG. 8 is a perspective view showing a wafer level CSP in which chips to be inspected according to the present invention obtained by step J shown in FIG. 7A are arranged.
FIG. 9 is an external perspective view showing an embodiment of an element-embedded probe according to the present invention.
FIGS. 10A to 10F are views showing manufacturing steps (1) to (6) of the main body of the element-embedded probe according to the present invention.
FIGS. 11A to 11E are views showing manufacturing steps (7) to (11) of the main body of the element-embedded probe according to the present invention. FIGS.
FIGS. 12A to 12C are views showing manufacturing steps (12), (13), and (15) of the body of the element-embedded probe according to the present invention.
FIGS. 13A to 13C are views showing manufacturing steps (16) to (18) of the body of the element-embedded probe according to the present invention. FIGS.
FIGS. 14A to 14C are views showing manufacturing steps (19) to (21) of the main body of the element-embedded probe according to the present invention. FIGS.
FIG. 15 is a diagram showing a manufacturing process (22) of the main body of the element-embedded probe according to the present invention.
FIGS. 16A to 16C are views for explaining a method of attaching an electrode or a terminal in the element built-in type probe according to the present invention. FIGS.
FIGS. 17A and 17B are views for explaining a method of attaching electrodes or terminals for connecting a communication cable and / or a power cable in the element-embedded probe according to the present invention. FIGS.
FIGS. 18A to 18C are views for explaining a mounting method of a mounting bracket in the element-embedded probe according to the present invention.
FIGS. 19A to 19C are diagrams for explaining a method of connecting a communication cable and / or a power cable to electrodes using terminals in the element built-in type probe according to the present invention.
FIG. 20 is a diagram for explaining a method of connecting a communication cable and / or a power cable to an electrode using a terminal in the element-embedded probe according to the present invention.
FIG. 21 is a view showing the structure of a conductor film formed by sputtering film formation on the wiring board of the element built-in probe according to the present invention.
FIG. 22 is a schematic view showing a structure in which wiring layers are multilayered in a wiring board of an element-embedded probe according to the present invention.
FIGS. 23A to 23C are views for explaining a method of forming a probe needle implanted in the element-embedded probe according to the present invention. FIGS.
FIG. 24 is a structural cross-sectional view showing the relationship among a stainless steel substrate, a first layer of nickel electroplating, and an insulating layer for manufacturing the wiring board of the element built-in probe according to the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Chip to be tested (wireless chip), 2 ... Radio, 3 ... RAM, 4 ... DSP (digital signal processor), 5 ... μP (microprocessor), 6 ... I / O, 10 ... Probe with built-in element, 11 ... Flash memory (nonvolatile memory), 12 ... crystal oscillator, 13 ... balun (amplifier), 14 ... LNA (low noise amplifier), 15 ... RF switch, 16 ... BPF (bandpass filter), 17, 17a, 17b ... Power wiring, 18 ... Signal wiring, 19, 19a to 19h ... Probe needle, 20 ... Mold resin, 21 ... Mounting bracket, 22 ... Wiring, 23 ... Communication cable and power cable, 23a, 23b ... Communication cable, 23c ... Power cable 24, 24a to 24d ... electrodes or terminals (including connectors), 25 ... wiring board, 28 ... first layer wiring, 28a ... Lobe needle implantation part, 29 ... wiring of second layer, 30 ... power supply, 31 ... computer for evaluation, 32 ... computer, 35 ... probe card (holding substrate), 50 ... wafer (wafer level CSP), 54 ... pad 55 ... Protective film, 56 ... Wiring for rewiring, 57 ... Bump pad, 58 ... Wafer, 59 ... Surface protective film, 60 ... Solder bump, 61 ... Power feeding film, 62 ... Reverse pattern of wiring, 63 ... Solder ball, 64 ... Printed circuit board, 65 ... Electro copper plating, 66 ... Electro nickel plating, 67 ... Pad / wiring joint, 70 ... XYZθ stage, 71 ... Holder, 101 ... Stainless steel substrate, 102 ... Electro nickel plating film, 103 ... Insulation Layer 104 conductive film 108 feeding film 111 copper electroplating film 112 electro nickel plating film 113 bump pad 115 Wiring board, 121 ... solder ball, 114 ... cover coat, 120 (11 to 16) ... electronic component, 122 ... underfill, 125a ... pattern, 126 ... base of probe needle, 130 ... hole for attaching probe needle, 131 ... Solder paste, 135, 143 ... Solder, 140 ... Terminal insertion hole, 141 ... Holder, 142 ... Screw, 150 ... Probe material, 151 ... Block, 152 ... Chrome film, 153 ... Copper film.

Claims (5)

A first insulating layer; a first wiring layer formed on the first insulating layer; a second insulating layer formed on the first insulating layer and covering the first wiring layer; formed on the second insulating layer And a second wiring layer electrically connected to the first wiring layer through the second insulating layer, and a second wiring layer formed on the second insulating layer and having an opening exposing the upper surface of the second wiring layer. A wiring board having three insulating layers, a probe needle implanted in the first wiring layer of the wiring board and projecting downward from the first insulating layer, and a second wiring layer electrically connected to the second wiring layer, respectively. A method for manufacturing a probe with a built-in element comprising connected electronic components and terminals,
The manufacturing method includes:
A first step of connecting the electronic component and the terminal by solder to the upper surface of the second wiring layer exposed from the third insulating layer through the opening;
A second step of covering the electronic component and the terminal with a mold resin and curing the mold resin;
By polishing the upper surface of the mold resin, it has rows and a third step in this order to expose the upper surface of the terminal of the electronic component in a state of being incorporated in the mold resin from the mold resin,
The probe needle is inserted into a hole formed from the first insulating layer to the second insulating layer through the first wiring layer after the third step and filled with a solder paste. A method for manufacturing an element-embedded probe   The electronic component includes one of the second wiring layers connected to the electronic component, the first wiring layer connected to the one second wiring layer, and the first wiring layer connected to the first wiring layer. 2. The element built-in type according to claim 1, wherein the terminal is electrically connected through the other one of the two wiring layers to the terminal soldered to the upper surface of the other second wiring layer. Probe manufacturing method.   The probe needle is soldered to the upper surface of the one second wiring layer through the first wiring layer in which the probe needle is implanted and one of the second wiring layers connected to the first wiring layer. 2. The method of manufacturing an element-embedded probe according to claim 1, wherein the probe is electrically connected to the terminal.   The underfill is injected between the third insulating layer and the electronic component between the first step and the second step to fix the electronic component to the wiring board. 2. A method for producing the element built-in probe according to 1.   The method of manufacturing a probe with a built-in element according to claim 1, wherein a cable is soldered to an upper surface of the terminal exposed from the mold resin.

Images