JP4206203B2 - プログラマブルロジック集積回路デバイスの相互接続ならびに入力／出力リソース - Google Patents

プログラマブルロジック集積回路デバイスの相互接続ならびに入力／出力リソース Download PDF

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Publication number
JP4206203B2
JP4206203B2 JP2000603150A JP2000603150A JP4206203B2 JP 4206203 B2 JP4206203 B2 JP 4206203B2 JP 2000603150 A JP2000603150 A JP 2000603150A JP 2000603150 A JP2000603150 A JP 2000603150A JP 4206203 B2 JP4206203 B2 JP 4206203B2
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Japan
Prior art keywords
conductors
input
signal
programmable logic
logic
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Expired - Fee Related
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JP2000603150A
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English (en)
Japanese (ja)
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JP2002538634A5 (enExample
JP2002538634A (ja
Inventor
ンガイ，トニー
ペダースン，ブルース
シューマレイブ，サーゲイ
シュライカー，ジェームズ
ヒュン，ウェイ−ジェン
ハットン，マイケル
マルリ，ビクター
パテル，ラケシュ
ジェイ カザリアン，ピーター
リーバー，アンドリュー
ダブリュー メンデル，ディビッド
パーク，ジム
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Altera Corp
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Altera Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/17744—Structural details of routing resources for input/output signals

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  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2000603150A 1999-03-04 2000-03-02 プログラマブルロジック集積回路デバイスの相互接続ならびに入力／出力リソース Expired - Fee Related JP4206203B2 (ja)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US12278899P 1999-03-04 1999-03-04
US60/122,788 1999-03-04
US14250899P 1999-07-06 1999-07-06
US14243199P 1999-07-06 1999-07-06
US14251399P 1999-07-06 1999-07-06
US60/142,508 1999-07-06
US60/142,431 1999-07-06
US60/142,513 1999-07-06
PCT/US2000/005628 WO2000052826A2 (en) 1999-03-04 2000-03-02 Interconnection and input/output resources for programmable logic integrated circuit devices

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP2006146010A Division JP4637790B2 (ja) 1999-03-04 2006-05-25 プログラマブルロジック集積回路デバイスの相互接続ならびに入力／出力リソース
JP2006146009A Division JP4813257B2 (ja) 1999-03-04 2006-05-25 プログラマブルロジック集積回路デバイスの相互接続ならびに入力／出力リソース

Publications (3)

Publication Number Publication Date
JP2002538634A JP2002538634A (ja) 2002-11-12
JP2002538634A5 JP2002538634A5 (enExample) 2006-07-20
JP4206203B2 true JP4206203B2 (ja) 2009-01-07

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Family Applications (7)

Application Number Title Priority Date Filing Date
JP2000603150A Expired - Fee Related JP4206203B2 (ja) 1999-03-04 2000-03-02 プログラマブルロジック集積回路デバイスの相互接続ならびに入力／出力リソース
JP2006146009A Expired - Fee Related JP4813257B2 (ja) 1999-03-04 2006-05-25 プログラマブルロジック集積回路デバイスの相互接続ならびに入力／出力リソース
JP2006146010A Expired - Fee Related JP4637790B2 (ja) 1999-03-04 2006-05-25 プログラマブルロジック集積回路デバイスの相互接続ならびに入力／出力リソース
JP2008270378A Expired - Fee Related JP5144462B2 (ja) 1999-03-04 2008-10-20 プログラマブルロジック集積回路デバイスの相互接続ならびに入力／出力リソース
JP2011235492A Withdrawn JP2012044708A (ja) 1999-03-04 2011-10-26 プログラマブルロジック集積回路デバイスの相互接続ならびに入力／出力リソース
JP2012141122A Pending JP2012186863A (ja) 1999-03-04 2012-06-22 プログラマブルロジック集積回路デバイスの相互接続ならびに入力／出力リソース
JP2014131068A Expired - Fee Related JP5820508B2 (ja) 1999-03-04 2014-06-26 プログラマブルロジック集積回路デバイスの相互接続ならびに入力／出力リソース

Family Applications After (6)

Application Number Title Priority Date Filing Date
JP2006146009A Expired - Fee Related JP4813257B2 (ja) 1999-03-04 2006-05-25 プログラマブルロジック集積回路デバイスの相互接続ならびに入力／出力リソース
JP2006146010A Expired - Fee Related JP4637790B2 (ja) 1999-03-04 2006-05-25 プログラマブルロジック集積回路デバイスの相互接続ならびに入力／出力リソース
JP2008270378A Expired - Fee Related JP5144462B2 (ja) 1999-03-04 2008-10-20 プログラマブルロジック集積回路デバイスの相互接続ならびに入力／出力リソース
JP2011235492A Withdrawn JP2012044708A (ja) 1999-03-04 2011-10-26 プログラマブルロジック集積回路デバイスの相互接続ならびに入力／出力リソース
JP2012141122A Pending JP2012186863A (ja) 1999-03-04 2012-06-22 プログラマブルロジック集積回路デバイスの相互接続ならびに入力／出力リソース
JP2014131068A Expired - Fee Related JP5820508B2 (ja) 1999-03-04 2014-06-26 プログラマブルロジック集積回路デバイスの相互接続ならびに入力／出力リソース

Country Status (4)

Country Link
EP (1) EP1092268B1 (enExample)
JP (7) JP4206203B2 (enExample)
DE (1) DE60038659T2 (enExample)
WO (1) WO2000052826A2 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000052825A1 (en) 1999-03-04 2000-09-08 Altera Corporation Interconnection resources for programmable logic integrated circuit devices
US6590419B1 (en) * 1999-10-12 2003-07-08 Altera Toronto Co. Heterogeneous interconnection architecture for programmable logic devices
US6930510B2 (en) 2003-03-03 2005-08-16 Xilinx, Inc. FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same
JP2005268536A (ja) 2004-03-18 2005-09-29 Matsushita Electric Ind Co Ltd プログラマブル・ロジック・デバイスおよびその設計方法
US7389485B1 (en) 2006-03-28 2008-06-17 Xilinx, Inc. Methods of routing low-power designs in programmable logic devices having heterogeneous routing architectures
KR101420817B1 (ko) 2008-01-15 2014-07-21 삼성전자주식회사 3 차원의 직렬 및 병렬 회로들을 가지고 차례로 적층된집적회로 모듈들을 전기적으로 접속하는 반도체 집적회로장치 및 그 장치의 형성방법
US8987868B1 (en) 2009-02-24 2015-03-24 Xilinx, Inc. Method and apparatus for programmable heterogeneous integration of stacked semiconductor die
US7893712B1 (en) 2009-09-10 2011-02-22 Xilinx, Inc. Integrated circuit with a selectable interconnect circuit for low power or high performance operation
JP5336398B2 (ja) * 2010-02-01 2013-11-06 ルネサスエレクトロニクス株式会社 半導体集積回路、半導体集積回路の構成変更方法
US9015023B2 (en) 2010-05-05 2015-04-21 Xilinx, Inc. Device specific configuration of operating voltage
WO2013024751A1 (ja) * 2011-08-12 2013-02-21 株式会社デンソー 集積回路

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4761768A (en) * 1985-03-04 1988-08-02 Lattice Semiconductor Corporation Programmable logic device
JPS6264124A (ja) * 1985-09-13 1987-03-23 Ricoh Co Ltd プログラマブル・ロジツク・デバイス
US4771285A (en) * 1985-11-05 1988-09-13 Advanced Micro Devices, Inc. Programmable logic cell with flexible clocking and flexible feedback
DE3684573D1 (de) * 1985-12-06 1992-04-30 Advanced Micro Devices Inc Programmierbare logische vorrichtung.
JPS6323419A (ja) * 1986-07-15 1988-01-30 Ricoh Co Ltd プログラマブル・ロジツク・デバイス
JPS63276327A (ja) * 1987-05-08 1988-11-14 Hitachi Ltd ダイナミック型ロジック・アレイ
JP2548301B2 (ja) * 1988-05-25 1996-10-30 富士通株式会社 プログラマブル論理回路装置
JP2772051B2 (ja) * 1988-09-08 1998-07-02 川崎製鉄株式会社 プログラマブル入出力回路及びプログラマブル論理素子
JPH02174249A (ja) * 1988-12-27 1990-07-05 Nec Corp Ｅｃｌ型ゲートアレイ集積回路装置
JP3179800B2 (ja) * 1991-07-22 2001-06-25 株式会社日立製作所 半導体集積回路装置
US5633830A (en) * 1995-11-08 1997-05-27 Altera Corporation Random access memory block circuitry for programmable logic array integrated circuit devices
JP3429844B2 (ja) * 1994-04-22 2003-07-28 沖電気工業株式会社 モード切り替えインタフェース回路
US5465056A (en) * 1994-06-30 1995-11-07 I-Cube, Inc. Apparatus for programmable circuit and signal switching
JPH08102492A (ja) * 1994-08-02 1996-04-16 Toshiba Corp プログラム可能な配線回路及びテストボード装置
US5442306A (en) * 1994-09-09 1995-08-15 At&T Corp. Field programmable gate array using look-up tables, multiplexers and decoders
JPH09181598A (ja) * 1995-12-18 1997-07-11 At & T Corp フィールドプログラマブルゲートアレイ
JPH09293784A (ja) * 1996-04-26 1997-11-11 Nippon Telegr & Teleph Corp <Ntt> フィールドプログラマブルゲートアレイ
US5894565A (en) * 1996-05-20 1999-04-13 Atmel Corporation Field programmable gate array with distributed RAM and increased cell utilization
US5763556A (en) * 1996-05-21 1998-06-09 Exxon Chemical Patents Inc. Copolymers of ethylene and geminally disubstituted olefins
US5999016A (en) * 1996-10-10 1999-12-07 Altera Corporation Architectures for programmable logic devices
US5977793A (en) * 1996-10-10 1999-11-02 Altera Corporation Programmable logic device with hierarchical interconnection resources
US5963050A (en) * 1997-02-26 1999-10-05 Xilinx, Inc. Configurable logic element with fast feedback paths
US6215326B1 (en) * 1998-11-18 2001-04-10 Altera Corporation Programmable logic device architecture with super-regions having logic regions and a memory region

Also Published As

Publication number Publication date
JP5144462B2 (ja) 2013-02-13
JP2009065694A (ja) 2009-03-26
WO2000052826A3 (en) 2001-01-25
JP4813257B2 (ja) 2011-11-09
JP2012044708A (ja) 2012-03-01
JP5820508B2 (ja) 2015-11-24
DE60038659D1 (de) 2008-06-05
JP4637790B2 (ja) 2011-02-23
JP2006246534A (ja) 2006-09-14
DE60038659T2 (de) 2009-06-18
EP1092268A2 (en) 2001-04-18
EP1092268B1 (en) 2008-04-23
JP2012186863A (ja) 2012-09-27
JP2002538634A (ja) 2002-11-12
JP2006287964A (ja) 2006-10-19
JP2014200106A (ja) 2014-10-23
WO2000052826A2 (en) 2000-09-08

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