JP4199774B2 - Electronic component mounting structure - Google Patents

Electronic component mounting structure Download PDF

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JP4199774B2
JP4199774B2 JP2006032979A JP2006032979A JP4199774B2 JP 4199774 B2 JP4199774 B2 JP 4199774B2 JP 2006032979 A JP2006032979 A JP 2006032979A JP 2006032979 A JP2006032979 A JP 2006032979A JP 4199774 B2 JP4199774 B2 JP 4199774B2
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metallized layer
electronic component
semiconductor element
component mounting
layer
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JP2006128734A (en
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太 作
信二 米盛
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering

Description

本発明は、半導体素子等の電子部品を搭載するための電子部品搭載構造体に関し、特に電子部品を基体に接合するためのメタライズ層に関するものである。   The present invention relates to an electronic component mounting structure for mounting an electronic component such as a semiconductor element, and more particularly to a metallized layer for bonding the electronic component to a substrate.

従来、ＩＣ，ＬＳＩ等の半導体素子や表面弾性波素子等の電子部品を搭載するための電子部品搭載用基板として、セラミック材料から成る基体に電子部品を搭載するためのメタライズ層を被着させて成る電子部品搭載用基板が知られている。このような電子部品搭載用基板が用いられる例として、例えばリードレスの半導体素子収納用パッケージ（チップキャリア）の基本構成を図３に示す。   Conventionally, as an electronic component mounting substrate for mounting an electronic component such as a semiconductor element such as an IC or LSI or a surface acoustic wave element, a metallized layer for mounting the electronic component is attached to a base made of a ceramic material. An electronic component mounting board is known. As an example in which such an electronic component mounting substrate is used, for example, a basic configuration of a leadless semiconductor element storage package (chip carrier) is shown in FIG.

同図において、１１はセラミックスから成る絶縁基体（以下、基体という）、１２は基体１１の上面略中央部の凹部の底面に半導体素子１５をロウ材を介して載置固定するためのメタライズ層、１３は電子部品１５を外部電気回路（図示せず）に接続するためのメタライズ層、１４は蓋体、１５は半導体素子、１６は半導体素子１５の電極とメタライズ層１３とを接続するためのボンディングワイヤを示す。   In the figure, 11 is an insulating base made of ceramics (hereinafter referred to as the base), 12 is a metallized layer for mounting and fixing the semiconductor element 15 on the bottom surface of the recess at the substantially central portion of the top surface of the base 11 via a brazing material, 13 is a metallized layer for connecting the electronic component 15 to an external electric circuit (not shown), 14 is a lid, 15 is a semiconductor element, 16 is a bond for connecting the electrode of the semiconductor element 15 and the metallized layer 13. The wire is shown.

これら基体１１、メタライズ層１２、メタライズ層１３で電子部品搭載用基板が構成され、この電子部品搭載用基板と蓋体１４とで半導体素子収納用パッケージ（以下、半導体パッケージという）を構成される。そして、パッケージの内部に半導体素子１５を収容する。   The substrate 11, the metallized layer 12, and the metallized layer 13 constitute an electronic component mounting substrate, and the electronic component mounting substrate and the lid body 14 constitute a semiconductor element housing package (hereinafter referred to as a semiconductor package). Then, the semiconductor element 15 is accommodated in the package.

基体１１は、アルミナ（Ａｌ2Ｏ3）セラミックスや窒化アルミニウム（ＡｌＮ）セラミックス等の各種セラミックスから成り、電気的に絶縁する機能を有し、また半導体素子１５の特性に応じてその種類が適宜選定される。メタライズ層１２は、基体１１の上面略中央部の凹部の底面に被着形成され、半導体素子１５の底面にクラッドしている金（Ａｕ）−シリコン（Ｓｉ）や金−ゲルマニウム（Ｇｅ）等のロウ材を介して半導体素子１５を強固に接合するための所謂下地金属層として機能し、タングステン（Ｗ）やモリブデン（Ｍｏ）−マンガン（Ｍｎ）等から成る金属ペーストを焼結して成る。 The substrate 11 is made of various ceramics such as alumina (Al 2 O 3 ) ceramics and aluminum nitride (AlN) ceramics, has a function of electrically insulating, and the type is appropriately selected according to the characteristics of the semiconductor element 15. Is done. The metallized layer 12 is deposited and formed on the bottom surface of the recess at the substantially central portion of the upper surface of the base 11 and is clad on the bottom surface of the semiconductor element 15 such as gold (Au) -silicon (Si) or gold-germanium (Ge). It functions as a so-called base metal layer for firmly bonding the semiconductor element 15 via the brazing material, and is formed by sintering a metal paste made of tungsten (W), molybdenum (Mo) -manganese (Mn), or the like.

メタライズ層１３は、半導体素子１５を外部電気回路（図示せず）に接続するための導電路として機能し、メタライズ層１２と同様、タングステン（Ｗ）やモリブデン（Ｍｏ）−マンガン（Ｍｎ）等から成る金属ペーストを焼結して成る。   The metallized layer 13 functions as a conductive path for connecting the semiconductor element 15 to an external electric circuit (not shown). Like the metallized layer 12, the metallized layer 13 is made of tungsten (W), molybdenum (Mo) -manganese (Mn), or the like. Sintered metal paste.

なお、このような基体１１，メタライズ層１２，メタライズ層１３から成る電子部品搭載用基板は、表面に金属ペーストをスクリーン印刷により印刷塗布した未焼成セラミックシート（グリーンシート）を複数枚積層するとともに高温で焼成することによって形成される。また、メタライズ層１２，メタライズ層１３の表面には酸化腐食を有効に防止するためのニッケル（Ｎｉ）メッキや金メッキ等のメッキが施されている。   The electronic component mounting substrate composed of the substrate 11, the metallized layer 12, and the metallized layer 13 is formed by laminating a plurality of unfired ceramic sheets (green sheets) on which a metal paste is printed and applied by screen printing. It is formed by baking. Further, the surfaces of the metallized layer 12 and the metallized layer 13 are plated with nickel (Ni) plating or gold plating for effectively preventing oxidative corrosion.

これらメタライズ層１２，メタライズ層１３が被着形成された基体１１の上面に、鉄（Ｆｅ）−ニッケル（Ｎｉ）−コバルト（Ｃｏ）合金等の金属材料またはアルミナセラミックス等のセラミックスから成る蓋体１４を、金−錫（Ｓｎ）ロウ材等の低融点ロウ材で接合することによって、半導体パッケージ内部に半導体素子１５を気密に収納しその作動性を良好なものとする。   A lid 14 made of a metal material such as iron (Fe) -nickel (Ni) -cobalt (Co) alloy or ceramics such as alumina ceramics is formed on the upper surface of the base 11 on which the metallized layer 12 and the metallized layer 13 are deposited. Are bonded with a low melting point brazing material such as a gold-tin (Sn) brazing material, so that the semiconductor element 15 is hermetically accommodated in the semiconductor package and the operability thereof is improved.

このように、基体１１、メタライズ層１２、メタライズ層１３から成る電子部品搭載用基板と蓋体１４とで構成される半導体パッケージの内部に半導体素子１５を収容するとともに、ボンディングワイヤ１６で半導体素子１５と半導体パッケージを電気的に接続し、蓋体１４を接合することによって最終製品としての半導体装置が完成する。   As described above, the semiconductor element 15 is accommodated in the semiconductor package constituted by the electronic component mounting substrate including the base body 11, the metallized layer 12, and the metallized layer 13 and the lid body 14, and the semiconductor element 15 is bonded by the bonding wire 16. And the semiconductor package are electrically connected to each other, and the lid 14 is joined to complete a semiconductor device as a final product.

しかしながら、この従来の電子部品搭載用基板によれば、半導体素子１５をその底面にクラッドしてあるロウ材を介してメタライズ層１２表面に接合した際、メタライズ層１２表面の凹凸に起因して、半導体素子１５の位置決めを正確に行うことが困難となったり、半導体素子１５とメタライズ層１２との間が接合されない部位、即ちボイド等が発生し、半導体素子１５とメタライズ層１２との接合強度が損なわれるという問題点を有していた。   However, according to this conventional electronic component mounting substrate, when the semiconductor element 15 is bonded to the surface of the metallized layer 12 via the brazing material clad on the bottom surface thereof, due to the unevenness of the surface of the metallized layer 12, It becomes difficult to accurately position the semiconductor element 15, or a portion where the semiconductor element 15 and the metallized layer 12 are not bonded, that is, a void or the like is generated, and the bonding strength between the semiconductor element 15 and the metallized layer 12 is increased. It had the problem of being damaged.

このメタライズ層１２表面の凹凸は、主としてスクリーン印刷における印刷版の網目の痕に起因している。 The unevenness on the surface of the metallized layer 12 is mainly caused by the traces of the printing plate in screen printing.

基体１１表面の凹凸を小さくするためには、その表面を研磨等により平坦にする方法があるが、コストや作業性の観点から、実質上実施するのは困難である。一方、金属ペーストの粘度を小さなものとしておけば、メタライズ層１２表面の凹凸を小さくできるが、この場合、メタライズ層１２にピンホールやにじみが発生してしまう。   In order to reduce the unevenness of the surface of the substrate 11, there is a method of flattening the surface by polishing or the like, but it is substantially difficult to implement from the viewpoint of cost and workability. On the other hand, if the metal paste has a low viscosity, the irregularities on the surface of the metallized layer 12 can be reduced, but in this case, pinholes and blurring occur in the metallized layer 12.

従って、本発明は上記問題点に鑑み完成されたもので、その目的は、電子部品の位置決めを正確に行うことが容易であるとともに、電子部品とメタライズ層との接合を強固なものとすることによって、電子部品を長期間にわたり正常かつ安定に作動させ得る電子部品搭載構造体を提供することにある。   Accordingly, the present invention has been completed in view of the above problems, and its purpose is to facilitate the accurate positioning of the electronic component and to strengthen the bonding between the electronic component and the metallized layer. Thus, an electronic component mounting structure capable of operating electronic components normally and stably over a long period of time is provided.

本発明の電子部品搭載構造体は、基体と、該基体上に形成され、周縁部が中央部よりも高く、且つ該中央部の表面が、断面視して下に凸の曲面状を成す下地金属層と、該下地金属層上に配置され、平坦な下面を有する電子部品と、前記下地金属層及び電子部品間に配置されるとともに、この両者を接合するロウ材と、を備えており、前記下地金属層の前記周縁部の頂部は、前記電子部品の下面周縁部を取り囲むように形成され、前記頂部と前記電子部品の下面の縁部との距離は０．０１〜０．１ｍｍであることを特徴とする。 Electronic component mounting structure of the present invention comprises a substrate, formed on said substrate, higher than the peripheral portion is a central portion, and the surface of the central portion, the base forming a convex curved below in cross section a metal layer disposed on the lower ground metal layer comprises an electronic component having a flat lower surface, while being disposed between the base metal layer and the electronic component, and the brazing material you joining the two, the The top of the peripheral portion of the base metal layer is formed so as to surround the peripheral portion of the lower surface of the electronic component, and the distance between the top portion and the edge of the lower surface of the electronic component is 0.01 to 0.1 mm. characterized in that there.

また本発明の電子部品搭載構造体は、前記下地金属層の前記周縁部と前記中央部との高低差が１〜３μｍであることを特徴とする。   The electronic component mounting structure according to the present invention is characterized in that a height difference between the peripheral edge portion and the central portion of the base metal layer is 1 to 3 μm.

更に本発明の電子部品搭載構造体は、前記下地金属層は、その表面における算術平均粗さが０．２〜１μｍであることを特徴とする。   Furthermore, the electronic component mounting structure according to the present invention is characterized in that the base metal layer has an arithmetic average roughness of 0.2 to 1 μm on the surface thereof.

本発明は、電子部品を下地電極層（メタライズ層）に接合する際の位置決めが非常に容易となるとともに電子部品の底面にクラッドしてあるロウ材を介して下地電極層（メタライズ層）に接合する際、それらの間にボイド等を発生させることなく、強固に接合できる。   In the present invention, positioning when joining an electronic component to a base electrode layer (metallized layer) is very easy, and the electronic component is joined to the base electrode layer (metallized layer) via a brazing material clad on the bottom surface of the electronic component. When doing so, it is possible to join firmly without generating voids or the like between them.

以下、本発明の電子部品搭載構造体について説明する。具体的には、半導体素子を搭載するためのリードレスの半導体パッケージ（チップキャリア）を例に説明する。図１は電子部品搭載用基板を用いたチップキャリアの実施の形態の一例を示す断面図、図２は本発明の要部であるメタライズ層の拡大断面図である。   Hereinafter, the electronic component mounting structure of the present invention will be described. Specifically, a leadless semiconductor package (chip carrier) for mounting a semiconductor element will be described as an example. FIG. 1 is a cross-sectional view showing an example of an embodiment of a chip carrier using an electronic component mounting substrate, and FIG. 2 is an enlarged cross-sectional view of a metallized layer which is a main part of the present invention.

同図において、１はアルミナセラミックスや窒化アルミニウムセラミックス等の電気絶縁材料から成る基体、２，３はメタライズ層、４は蓋体である。この基体１、メタライズ層２，３で電子部品搭載用基板が構成され、この電子部品搭載用基板と蓋体４とで電子部品としての半導体素子５を収容するための容器を構成する。   In the figure, 1 is a base made of an electrically insulating material such as alumina ceramics or aluminum nitride ceramics, 2 and 3 are metallized layers, and 4 is a lid. The substrate 1 and the metallized layers 2 and 3 constitute an electronic component mounting substrate, and the electronic component mounting substrate and the lid 4 constitute a container for housing a semiconductor element 5 as an electronic component.

基体１はその上面略中央部に半導体素子５を収容するための空所を形成する段状の凹部を有しており、この凹部底面にはメタライズ層２が被着形成されている。また、メタライズ層２はタングステン（Ｗ）やモリブデン（Ｍｏ）−マンガン（Ｍｎ）等から成る金属ペーストを焼結して成り、その上面に半導体素子５を金−シリコンや金−ゲルマニウム等のロウ材を介して接合するための下地金属層として機能する。   The base body 1 has a stepped recess for forming a space for accommodating the semiconductor element 5 at the substantially central portion of the upper surface, and a metallized layer 2 is deposited on the bottom surface of the recess. The metallized layer 2 is formed by sintering a metal paste made of tungsten (W), molybdenum (Mo) -manganese (Mn), or the like, and the semiconductor element 5 is brazed on the upper surface of the brazing material such as gold-silicon or gold-germanium. It functions as a base metal layer for bonding via.

また、このメタライズ層２が被着形成されている基体１は、その上面から側面を介し底面にかけて導出しているメタライズ層３が形成されており、基体１上面のメタライズ層３には半導体素子５の電極がボンディングワイヤ６を介して電気的に接続され、また基体１底面のメタライズ層３は外部電気回路の配線導体に半田等のロウ材を介しロウ付けされる。   Further, the base 1 on which the metallized layer 2 is deposited is formed with a metallized layer 3 which is led out from the top surface to the bottom surface through the side surface, and the semiconductor element 5 is formed on the metallized layer 3 on the top surface of the base 1. The metallized layer 3 on the bottom surface of the substrate 1 is brazed to a wiring conductor of an external electric circuit via a brazing material such as solder.

これら基体１，メタライズ層２，メタライズ層３は、表面に金属ペーストを印刷塗布した未焼成セラミックシート（グリーンシート）を複数枚積層するとともに還元性雰囲気（Ｈ2−Ｎ2ガス）中、約１４００〜１６００℃の高温で焼成することによって形成される。 The base 1, metallized layer 2, and metallized layer 3 are each formed by laminating a plurality of unfired ceramic sheets (green sheets) having a metal paste printed on the surface thereof, and in a reducing atmosphere (H 2 -N 2 gas), about 1400. It is formed by firing at a high temperature of ˜1600 ° C.

なお、この未焼成セラミックシートは、その原料粉末に適当な有機バインダや溶剤等を添加混合しペースト状と成すとともに、このペーストをドクターブレード法やカレンダーロール法によってシート状と成すことによって形成される。   The unfired ceramic sheet is formed by adding and mixing an appropriate organic binder or solvent to the raw material powder to form a paste, and forming the paste into a sheet by a doctor blade method or a calender roll method. .

また、金属ペーストは、タングステン、モリブデン−マンガン等の高融点金属粉末に適当な溶剤、溶媒を添加混合することによって作製され、未焼成セラミックシートの表面にはスクリーン印刷等の膜厚法を採用することによって印刷塗布される。   The metal paste is prepared by adding and mixing an appropriate solvent and solvent to a refractory metal powder such as tungsten or molybdenum-manganese, and a film thickness method such as screen printing is adopted on the surface of the unfired ceramic sheet. Is applied by printing.

更に、メタライズ層２は、その上面に耐食性に優れかつロウ材との濡れ性に優れる金属、具体的には厚さ０．５〜９μｍのＮｉ層や０．５〜５μｍのＡｕ層等の金属層をメッキ法により被着させておくと良い。   Further, the metallized layer 2 is a metal having excellent corrosion resistance and excellent wettability with the brazing material on its upper surface, specifically, a metal such as a Ni layer having a thickness of 0.5 to 9 μm or an Au layer having a thickness of 0.5 to 5 μm. The layer is preferably deposited by plating.

また、メタライズ層２の厚さは１５μｍ以下がよく、この場合厚さが薄いことから、未焼成セラミックシートに金属ペーストを印刷塗布し、しかる後、同時焼成してメタライズ層２を有する基体１を得る場合、セラミックスから成る基体１とモリブデン−マンガン，タングステン等から成るメタライズ層２との熱膨張差による歪みは極めて小さくなる。その結果、メタライズ層２にクラックや割れが発生したり、基体１とメタライズ層２との間で剥がれが発生することはない。   Further, the thickness of the metallized layer 2 is preferably 15 μm or less. In this case, since the thickness is thin, a metal paste is printed and applied to an unfired ceramic sheet, and then simultaneously fired to form a substrate 1 having the metallized layer 2. When obtained, the strain due to the difference in thermal expansion between the substrate 1 made of ceramics and the metallized layer 2 made of molybdenum-manganese, tungsten or the like becomes extremely small. As a result, no cracks or cracks occur in the metallized layer 2, and no peeling occurs between the substrate 1 and the metallized layer 2.

なお、基体１の凹部底面に被着形成するメタライズ層２の厚さを１５μｍ以下とするには、未焼成セラミックシートに金属ペーストをスクリーン印刷法により印刷塗布する際、印刷版のレジスト厚みを薄くすることによって、実行できる。   In order to reduce the thickness of the metallized layer 2 deposited on the bottom surface of the concave portion of the substrate 1 to 15 μm or less, the thickness of the resist of the printing plate is reduced when a metal paste is printed on the unfired ceramic sheet by screen printing. You can do that.

一方、メタライズ層２の厚さは５μｍ以上がよく、５μｍ未満では金属ペーストの印刷時にかすれてメタライズ層２を所定のパターンに形成することが困難となる点で不適である。   On the other hand, the thickness of the metallized layer 2 is preferably 5 μm or more, and if it is less than 5 μm, it is unsuitable in that it becomes difficult to form the metallized layer 2 in a predetermined pattern when it is printed with a metal paste.

また、メタライズ層２は、その周縁部が中央部よりも高く形成された形状（凹形状）である。このように、メタライズ層２の周縁部が中央部よりも高く形成された凹形状であることから、この上に半導体素子５を搭載すると、半導体素子５がぐらつくことがないので極めて正確に位置決めされる。このようなメタライズ層２の形状は、金属ペーストの粘度およびチキソトロピー、印刷厚みを適度に調整することによって、印刷された金属ペーストの外周縁に表面張力の影響による盛り上りを形成することにより、周縁部が中央部よりも高く形成され凹形状とすることができる。   The metallized layer 2 has a shape (concave shape) in which the peripheral edge is formed higher than the central portion. As described above, since the peripheral portion of the metallized layer 2 has a concave shape formed higher than the central portion, when the semiconductor element 5 is mounted thereon, the semiconductor element 5 does not wobble so that the positioning is extremely accurate. The The shape of the metallized layer 2 is formed by appropriately adjusting the viscosity and thixotropy of the metal paste and the printing thickness, thereby forming a bulge due to the influence of surface tension on the outer periphery of the printed metal paste. The part can be formed higher than the central part and have a concave shape.

このメタライズ層２の周縁部の最高部（頂部）は、半導体素子５下面の周縁部にほぼ相当するように形成されるか、または、半導体素子５下面の周縁部を囲むように形成されることが好ましい。この場合、半導体素子５の下面がメタライズ層２に良好に接合されることとなる。   The highest part (top) of the peripheral part of the metallized layer 2 is formed so as to substantially correspond to the peripheral part of the lower surface of the semiconductor element 5, or formed so as to surround the peripheral part of the lower surface of the semiconductor element 5. Is preferred. In this case, the lower surface of the semiconductor element 5 is favorably bonded to the metallized layer 2.

より好ましくは、メタライズ層２の周縁部の最高部が半導体素子５下面の周縁部を囲むとともに、その最高部と半導体素子５下面の縁部（輪郭）との距離が、０．０１〜０．１ｍｍであることがよい。０．０１ｍｍ未満では、半導体素子５をメタライズ層２上に接合させる前に半導体素子５下面をメタライズ層２に対しスクラブ（擦りつける）することにより、ロウ材を溶け易くしかつメタライズ層２の気泡を追い出すスクラブ工程を行う際に、そのスクラブが困難になり、ロウ材を溶け易くしかつメタライズ層２の気泡を追い出すという効果が得られなくなる。０．１ｍｍを超えると、メタライズ層２の面積が大きくなり、半導体パッケージが大型化して実用性が低下する。   More preferably, the highest portion of the peripheral portion of the metallized layer 2 surrounds the peripheral portion of the lower surface of the semiconductor element 5, and the distance between the highest portion and the edge portion (contour) of the lower surface of the semiconductor element 5 is 0.01-0. It is good that it is 1 mm. When the thickness is less than 0.01 mm, the lower surface of the semiconductor element 5 is scrubbed (rubbed) against the metallized layer 2 before the semiconductor element 5 is bonded to the metallized layer 2, thereby facilitating the melting of the brazing material and the bubbles in the metalized layer 2. When the scrubbing process for expelling is performed, scrubbing becomes difficult, and the effects of facilitating melting of the brazing material and expelling bubbles of the metallized layer 2 cannot be obtained. If it exceeds 0.1 mm, the area of the metallized layer 2 becomes large, the semiconductor package becomes large, and the practicality decreases.

さらに、メタライズ層２は、その周縁部と中央部との高低差が３μｍ以下であるとともに表面の算術平均粗さが１μｍ以下とされている。このように、メタライズ層２の周縁部と中央部との高低差が３μｍ以下であるとともに表面の算術平均粗さが１μｍ以下の平滑な面であることから、メタライズ層２に半導体素子５を介して接合する際にメタライズ層２と半導体素子５との間にメタライズ層２の凹凸に起因するボイドの形成が抑止され、半導体素子５とメタライズ層２との接合を強固なものとできる。このメタライズ層２の外周縁と中央部との高低差が３μｍを超える場合や表面の算術平均粗さが１μｍを越える場合、半導体素子５とメタライズ層２との間で接合されない部位、即ちボイド等が発生し、半導体素子５とメタライズ層２との接合強度が損なわれる。   Further, the metallized layer 2 has a height difference of 3 μm or less between the peripheral edge portion and the central portion and an arithmetic average roughness of the surface of 1 μm or less. Thus, since the height difference between the peripheral edge portion and the central portion of the metallized layer 2 is 3 μm or less and the arithmetic average roughness of the surface is a smooth surface of 1 μm or less, the semiconductor element 5 is interposed in the metallized layer 2. Therefore, the formation of voids due to the unevenness of the metallized layer 2 between the metallized layer 2 and the semiconductor element 5 is suppressed, and the bonding between the semiconductor element 5 and the metallized layer 2 can be strengthened. When the height difference between the outer peripheral edge and the central portion of the metallized layer 2 exceeds 3 μm, or when the arithmetic average roughness of the surface exceeds 1 μm, a portion that is not bonded between the semiconductor element 5 and the metallized layer 2, that is, a void Occurs, and the bonding strength between the semiconductor element 5 and the metallized layer 2 is impaired.

メタライズ層２の周縁部と中央部との高低差を３μｍ以下とするとともに表面の算術平均粗さを１μｍ以下の平滑なものとするには、金属ペーストを印刷塗布してこれを乾燥させた後、金属ペーストの平滑性を促進するために、金属ペースト上に樹脂製フィルムを載せ、これを油圧プレス装置等の加圧装置により上方よりプレスし、適度に圧力を加えることによって成される。   In order to make the height difference between the peripheral portion and the central portion of the metallized layer 2 3 μm or less and to make the arithmetic mean roughness of the surface smooth 1 μm or less, the metal paste is printed and applied and dried. In order to promote the smoothness of the metal paste, a resin film is placed on the metal paste, this is pressed from above with a pressurizing device such as a hydraulic press device, and moderately pressurized.

なお、メタライズ層２の周縁部と中央部との高低差が１μｍ未満であると、半導体素子５とメタライズ層２との間に大きなロウ材の溜まりが形成されず、半導体素子５とメタライズ層２との接合強度が小さいものとなりやすいので、メタライズ層２の周縁部と中央部との高低差は１μｍ以上であることが好ましい。また、メタライズ層２表面の算術平均粗さが０．２μｍ未満であると、メタライズ層２の表面粗さに起因する係止力が弱くなりメタライズ層２と半導体素子５との接合強度が小さいものとなりやすいので、メタライズ層２の表面の算術平均粗さは０．２μｍ以上であることが好ましい。   If the difference in height between the peripheral edge portion and the central portion of the metallized layer 2 is less than 1 μm, a large pool of brazing material is not formed between the semiconductor element 5 and the metallized layer 2, and the semiconductor element 5 and the metallized layer 2. Therefore, the difference in height between the peripheral edge portion and the central portion of the metallized layer 2 is preferably 1 μm or more. Further, when the arithmetic average roughness of the surface of the metallized layer 2 is less than 0.2 μm, the locking force resulting from the surface roughness of the metallized layer 2 becomes weak and the bonding strength between the metallized layer 2 and the semiconductor element 5 is small. Therefore, the arithmetic average roughness of the surface of the metallized layer 2 is preferably 0.2 μm or more.

また、蓋体４は、Ｆｅ−Ｎｉ−Ｃｏ合金等から成る金属板または基体１と同じ種類のセラミック板から成り、例えば金属板から成る場合、蓋体４は、これが接合される基体１の部位に被着形成されたメタル層にシーム溶接等によって接合され、半導体素子５を半導体パッケージ内部に気密に収容することとなり、最終製品としての半導体装置となる。   The lid 4 is made of a metal plate made of Fe-Ni-Co alloy or the like or a ceramic plate of the same type as the base 1. For example, when the lid 4 is made of a metal plate, the lid 4 is a part of the base 1 to which the lid 4 is joined. The semiconductor element 5 is bonded to the metal layer deposited by seam welding or the like, and the semiconductor element 5 is hermetically accommodated in the semiconductor package, so that a semiconductor device as a final product is obtained.

このように、上述の電子部品搭載用基板は、凹部を有する基体１の凹部底面にメタライズ層２が、また、基体１の上面から側面を介し底面にかけてメタライズ層３が被着形成されたものであり、凹部底面のメタライズ層２の上面に半導体素子５を接合するとともに、上面部と半導体素子５の電極とをボンディングワイヤ６で電気的に接合した後、蓋体４をシーム溶接等によって基体１上面に接合し半導体素子５を気密に収容することにより半導体装置となる。しかる後、基体１底面部のメタライズ層３は外部電気回路の配線導体に半田等のロウ材を介しロウ付けされ、半導体素子５と外部電気回路との信号の入出力が可能となる。   As described above, the electronic component mounting substrate described above is formed by depositing the metallized layer 2 on the bottom surface of the concave portion of the base body 1 having the concave portions and the metallized layer 3 from the top surface of the base body 1 to the bottom surface through the side surfaces. Yes, the semiconductor element 5 is bonded to the upper surface of the metallized layer 2 on the bottom surface of the recess, and the upper surface portion and the electrode of the semiconductor element 5 are electrically bonded to each other by the bonding wire 6. A semiconductor device is obtained by bonding to the upper surface and accommodating the semiconductor element 5 in an airtight manner. Thereafter, the metallized layer 3 on the bottom surface of the substrate 1 is brazed to the wiring conductor of the external electric circuit via a brazing material such as solder, and signals can be input / output between the semiconductor element 5 and the external electric circuit.

かくして、本発明は、基体１表面に、周縁部が中央部よりも高く形成されかつ周縁部と中央部との高低差が３μｍ以下であるとともに表面の算術平均粗さが１μｍ以下とされたメタライズ層２を被着形成したことにより、半導体素子５をメタライズ層２に接合する際の位置決めが非常に容易となるとともに半導体素子５の底面にクラッドしてあるロウ材を介してメタライズ層２に接合する際、それらの間にボイド等を発生させることなく、強固に接合できる。   Thus, the present invention is a metallization in which the peripheral portion is formed higher on the surface of the substrate 1 than the central portion, the height difference between the peripheral portion and the central portion is 3 μm or less, and the arithmetic average roughness of the surface is 1 μm or less. Since the layer 2 is deposited, the positioning when the semiconductor element 5 is bonded to the metallized layer 2 is very easy, and the semiconductor element 5 is bonded to the metallized layer 2 via the brazing material clad on the bottom surface of the semiconductor element 5. When doing so, it is possible to join firmly without generating voids or the like between them.

なお、本発明は、上記実施の形態に限定されず、本発明の要旨を逸脱しない範囲内において種々の変更を行うことは何等支障ない。例えば、メタライズ層２，メタライズ層３は、電気抵抗の非常に低い銅（Ｃｕ）から成っていても良く、この場合、外部電気回路と半導体素子５との高周波信号の入出力を非常に速くできる。また、基体１は、半導体素子５の特性に応じて、ムライト（３Ａｌ2Ｏ3・２ＳｉＯ2）セラミックスやガラスセラミックス等の比較的、比誘電率の低いものを採用することにより、高周波信号の入出力を非常に速くできる。 It should be noted that the present invention is not limited to the above-described embodiment, and various modifications are not hindered without departing from the gist of the present invention. For example, the metallized layer 2 and the metallized layer 3 may be made of copper (Cu) having a very low electric resistance. In this case, input / output of a high-frequency signal between the external electric circuit and the semiconductor element 5 can be made very fast. . The substrate 1 is made of a material having a relatively low dielectric constant, such as mullite (3Al 2 O 3 .2SiO 2 ) ceramics or glass ceramics, depending on the characteristics of the semiconductor element 5, so that a high frequency signal can be input. Output can be very fast.

また、上述の実施形態例では、本発明に用いられる電子部品搭載用基板として半導体素子が搭載されるチップキャリアを用いる場合を例にとって説明したが、本発明は、表面弾性波素子等の他の種類の電子部品を搭載するための電子部品搭載構造体にも適用可能である。   Further, in the above-described embodiment, the case where a chip carrier on which a semiconductor element is mounted is used as an electronic component mounting substrate used in the present invention has been described as an example. The present invention can also be applied to an electronic component mounting structure for mounting various types of electronic components.

本発明の電子部品搭載構造体をチップキャリアに適用した一実施形態を示す断面図である。It is sectional drawing which shows one Embodiment which applied the electronic component mounting structure of this invention to the chip carrier. 図１の電子部品搭載構造体のメタライズ層の拡大断面図である。It is an expanded sectional view of the metallization layer of the electronic component mounting structure of FIG. 従来の電子部品搭載構造体の断面図である。It is sectional drawing of the conventional electronic component mounting structure.

符号の説明Explanation of symbols

２・・・メタライズ層
５・・・半導体素子 2 ... Metallized layer 5 ... Semiconductor element

Claims (3)

基体と、
該基体上に形成され、周縁部が中央部よりも高く、且つ該中央部の表面が、断面視して下に凸の曲面状を成す下地金属層と、
該下地金属層上に配置され、平坦な下面を有する電子部品と、前記下地金属層及び電子部品間に配置されるとともに、この両者を接合するロウ材と、
を備えており、前記下地金属層の前記周縁部の頂部は、前記電子部品の下面周縁部を取り囲むように形成され、前記頂部と前記電子部品の下面の縁部との距離は０．０１〜０．１ｍｍであることを特徴とする電子部品搭載構造体。 A substrate;
Is formed on the substrate, higher than the peripheral portion is a central portion, is and the surface of the central portion, and the underlying metal layer forming a curved convex downward in cross section,
An electronic component disposed on the base metal layer and having a flat lower surface; and a brazing material disposed between the base metal layer and the electronic component and joining the two;
A top portion of the peripheral portion of the base metal layer is formed so as to surround a peripheral portion of a lower surface of the electronic component, and a distance between the top portion and an edge portion of the lower surface of the electronic component is 0.01 to An electronic component mounting structure characterized by being 0.1 mm . 前記下地金属層の前記周縁部と前記中央部との高低差は１〜３μｍである請求項１に記載の電子部品搭載構造体。 The electronic component mounting structure according to claim 1, wherein a height difference between the peripheral edge portion and the central portion of the base metal layer is 1 to 3 μm. 前記下地金属層は、その表面における算術平均粗さが０．２〜１μｍである、請求項１または請求項２に記載の電子部品搭載構造体。 The electronic component mounting structure according to claim 1, wherein the base metal layer has an arithmetic average roughness of 0.2 to 1 μm on a surface thereof.
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