JP4185133B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having an insulating gate structure using an insulating substrate such as glass or a silicon film provided on an insulating film formed on various substrates, such as a thin film transistor (TFT) or a thin film diode (TFD). ), Or a thin film integrated circuit to which these are applied, in particular, a method for manufacturing a thin film integrated circuit for an active liquid crystal display device (liquid crystal display), and in particular, a maximum process temperature of 700 ° C. or lower, preferably 650 ° C. or lower The present invention relates to a method for manufacturing a gate insulating film for forming the semiconductor device by a process.

  In recent years, semiconductor devices having TFTs on an insulating substrate such as glass, for example, active liquid crystal display devices and image sensors that use TFTs for driving pixels have been developed. As these substrates, glass substrates having a strain point of 750 ° C. or less, typically 550 to 680 ° C. are generally used from the viewpoint of mass productivity and price. Therefore, when such a glass substrate is used, the maximum process temperature is required to be 700 ° C. or lower.

  A thin film silicon semiconductor is generally used for TFTs used in these devices. Thin film silicon semiconductors are roughly classified into two types: those made of amorphous silicon semiconductor (a-Si) and those made of crystalline silicon semiconductor. Amorphous silicon semiconductors are most commonly used because they have a low production temperature, can be produced relatively easily by a vapor phase method, and are mass-productive. However, field effect mobility, conductivity, etc. Since the physical properties are inferior to those of crystalline silicon semiconductors, in order to obtain higher speed characteristics in the future, it is strongly required to establish a method for manufacturing TFTs made of crystalline silicon semiconductors.

  In the case of a TFT using amorphous silicon having a low mobility, the characteristics of the gate insulating film have not been a problem. For example, in a TFT using amorphous silicon, a silicon nitride film having inferior electrical characteristics than silicon oxide is used as a gate insulating film. However, in a TFT using a crystalline silicon film with high mobility, the characteristics of the gate insulating film are as large as the characteristics of the silicon film itself.

  In particular, as the technology for obtaining a crystalline silicon film has improved, the demand for a high-quality gate insulating film has increased greatly. In particular, even if the channel formation region is substantially composed of one single crystal or a plurality of crystals, the TFT is made of a crystalline silicon film in which all the crystal orientations are the same (this crystal state is called a monodomain). However, unlike a TFT using normal polycrystalline silicon, the contribution to the deterioration of the grain boundary characteristics is very small, and the electrical characteristics are almost determined by the characteristics of the gate insulating film.

  That is, in a normal polycrystalline structure, the crystal orientations of two crystals constituting a grain boundary are different from each other, resulting in a high grain boundary barrier (barrier). However, in the monodomain structure, even if it is composed of a plurality of crystals, the crystal orientations of the two crystals sandwiching the boundary corresponding to the grain boundary in the normal polycrystal are the same. The barrier is very low and almost no different from single crystals. Therefore, in the monodomain structure, the contribution of the grain boundary to the characteristics of the TFT is small and is almost determined by the gate insulating film.

A thermal oxide film is known as an excellent gate insulating film suitable for such a purpose. For example, a gate insulating film could be obtained using a thermal oxidation method on a substrate that can withstand high temperatures such as a quartz substrate. (For example, Japanese Patent Publication No. 3-71793)
Since a thermal oxide film has very few defects that trap when a charge such as hot electrons is injected, a highly reliable element can be manufactured with little deterioration in characteristics.

  In order to obtain a silicon oxide film that can be used as a gate insulating film by the thermal oxidation method, a high temperature of 950 ° C. or higher is required, and there is no substrate material other than quartz that can withstand such a high temperature treatment. In order to use a glass substrate having a low strain point as described above, the maximum process temperature must be 700 ° C. or less, preferably 650 ° C. or less. However, the conventional thermal oxidation method can satisfy this requirement. There wasn't.

  Because of these problems, the gate insulating film must be formed using a physical vapor deposition (PVD) method such as a sputtering method, or a chemical vapor deposition (CVD) method such as a plasma CVD method or a thermal CVD method. I didn't get it. In these methods, the maximum process temperature could be 650 ° C. or less.

  However, the insulating film produced by the PVD method or the CVD method has a high concentration of dangling bonds and hydrogen, and the interface characteristics are not good. Therefore, it is weak against injection of hot electrons or the like, and charge trap centers are easily formed due to unpaired bonds and hydrogen. For this reason, when used as a gate insulating film of a TFT, there is a problem that the electric field mobility and the subthreshold characteristic value (S value) are not good, or there is a large leakage current of the gate electrode, and the ON current is reduced (deteriorated).・ There was a problem that the change over time) was large. For this reason, a technique for producing a thermal oxide film at a low temperature has been demanded.

  The present invention provides means for solving the above problems. That is, an object of the present invention is to provide a method for producing a gate insulating film by a thermal oxidation method using a crystalline silicon film at a maximum process temperature of 700 ° C. or lower.

In the present invention, a thermal oxide film is formed on the surface of the silicon film at a low temperature of 400 to 700 ° C., typically 550 to 650 ° C., by heat-treating the silicon film in a special atmosphere. In the present invention, oxygen, ozone, or nitrogen oxides (generally expressed as NO _x : 0.5 ≦ x ≦ 2.5) containing thermally excited or pyrolyzed components are used. By performing thermal annealing at 400 to 700 ° C. in a highly reactive atmosphere, the silicon film is thermally oxidized to obtain a silicon oxide film. As the nitrogen oxide used in the thermal oxidation in the present invention, any of dinitrogen monoxide (N ₂ O), nitrogen monoxide (NO), nitrogen dioxide (N ₂ O), or a mixed gas thereof is preferable. .

However, it is not preferable that these atmospheres contain hydrides such as water (H ₂ O) because the resulting thermal oxide film contains hydrogen. Similarly, it was not preferable that carbon dioxide (CO, CO _2, etc.) was also contained. The concentration of water or carbon dioxide in the atmosphere is 1 ppm or less, preferably 10 ppb or less.
Hereinafter, a gas having nitrogen oxide (or oxygen) that is thermally excited or decomposed is referred to as reactive nitrogen oxide (reactive oxygen). In the present invention, the reactive nitrogen oxide (reactive oxygen) may consist only of nitrogen oxide (oxygen), or may contain argon or other inert gas.

The upper limit of the oxidation temperature is determined by the type of substrate used. Of course, the higher the temperature of thermal oxidation, the easier the oxidation action proceeds. In a Corning 7059 substrate, which is a typical glass substrate, 550 to 650 ° C. was appropriate. In the present invention, various glass substrates having a strain temperature (strain point) of 750 ° C. or lower, typically 550 to 680 ° C. as represented by Corning 7059 glass (non-alkali, borosilicate glass) are used. Use it.
An example of an apparatus for carrying out the present invention is shown in FIG. In carrying out the present invention, first, a first reaction chamber 1 for thermally exciting nitrogen oxide or oxygen and ozone, and a reactive nitrogen oxide or oxygen obtained by the first reaction chamber, etc. And a second reaction chamber for oxidizing the silicon film at a temperature of 400 to 700 ° C. is necessary. In FIG. 1A, 1 is a first reaction chamber and 5 is a second reaction chamber. And these reaction chambers and the channel | path 4 between them need to be maintained at appropriate temperature. The heaters 2, 3, 6 are for that purpose.

  The first reaction chamber is required to have a sufficiently high temperature to make nitrogen oxides reactive. That is, it is necessary that the temperature be higher than the temperature at which the nitrogen oxides decompose. The optimum temperature varies depending on the type of gas. For example, in the case of dinitrogen monoxide, it is preferably set to 750 to 950 ° C. In the case of oxygen, a temperature higher than 1000 to 1200 ° C. is necessary for thermal excitation and decomposition.

When the temperature of the passage 4 between the first reaction chamber and the second reaction chamber is extremely low, the gas molecules excited in the first reaction chamber return to the ground state, and the reactivity decreases. Therefore, in order to maintain the reactivity, it is necessary to maintain an appropriate temperature in the passage 4 as well. The temperature of the passage 4 is preferably an intermediate temperature between the first reaction chamber and the second reaction chamber. That is, if the temperature of the first reaction chamber 1 is T _A , the temperature of the passage 4 is T _B , and the temperature of the second reaction chamber 5 is T _C , then T _A ≧ T _B ≧ T _C. Moreover, it is desirable that the inner wall of the passage 4 is made of a material mainly composed of quartz so that reactive gas molecules do not react. Preferably, high-purity quartz made of 90 mol% or more silicon oxide is used.

When the inner wall is a metal, the excited state or atomic atoms / molecules are recombined and stabilized. However, in the case of quartz, such an effect is small. For example, many atoms and molecules are in an activated state even if they are separated from the first reaction chamber by 50 to 100 cm.
It is preferable to place a large number of substrates 8 on the susceptor 7 in the second reaction chamber 5 so that a large number of substrates can be processed at a time. In the present invention, the first reaction chamber is considerably hotter than the second reaction chamber, and since the high-temperature gas flows into the second reaction chamber, the temperature control is difficult. If there is a temperature distribution in the reaction chamber, a large number of substrates cannot be processed simultaneously. Therefore, it is necessary to improve the uniformity of the temperature distribution in the second reaction chamber 5 by optimizing the length and temperature of the passage 4. It is also effective to lower the atmospheric pressure below atmospheric pressure.

  In the example of FIG. 1A, it is difficult to make many gas molecules reactive in the first reaction chamber. This is because in order for the gas to be excited or decomposed, it is necessary to obtain thermal energy from the walls of the reaction chamber, but the opportunity to contact the walls of the reaction chamber while staying in the first reaction chamber This is because the number of gas molecules with is only a small part of the whole. Strictly speaking, the reaction is also caused by the kinetic energy of other gas molecules, but the energy applied is obtained directly or indirectly from the walls of the reaction chamber by other gas molecules. Of course, the present invention can be practiced if there are a small number of reactive molecules. However, it goes without saying that the greater the number, the greater the effect.

  In order to make many gas molecules reactive, as shown in FIG. 1B, a material 9 that easily conducts heat, such as metal, or absorbs infrared rays is formed in the first reaction chamber. What is necessary is just to provide. Preferably, such a material has a large surface area, such as a net, so that a large amount of gas can be contacted without obstructing the gas flow. More preferably, the material 9 has a catalytic action. For example, platinum, palladium, (reduced) nickel, titanium, vanadium, cobalt and the like. The catalyst may be powdery or granular in addition to the network.

When such a material is touched, the gas molecules become reactive as in the case of touching the walls of the reaction chamber, and the larger the surface area, the more gas molecules can be made reactive. Furthermore, more reactive gas can be obtained if such a material has a catalytic action. Further, for example, it is also effective to set a temperature higher than the temperature of the first reaction chamber by passing an electric current through the net-like metal 9.
If the method as described above is employed, the temperature of the first reaction chamber can be lowered as compared with the case of FIG.

In order to improve the oxidation rate, not only 1 atmospheric pressure (atmospheric pressure) but also oxidation in a pressurized atmosphere exceeding 15 atm by pressurization is effective. For example, in an atmosphere of 10 atm, an oxidation rate 10 times higher than that in an atmosphere of 1 atm can be obtained. Also, the oxidation temperature can be lowered.
FIG. 5 shows the relationship between the thickness of the thermal oxide film obtained using the apparatus of FIG. 1 and the oxidation time. As the oxidizing atmosphere, dinitrogen monoxide was used. It can be seen that the higher the temperature and the higher the pressure, the easier the oxidation action proceeds.

  In order to form crystalline silicon to be an active layer in the present invention, an amorphous silicon film obtained by a CVD method such as a plasma CVD method or a low pressure CVD method is used as a starting material. There is a street way. The first is a method of crystallizing by forming an amorphous silicon film and then performing thermal annealing at a temperature of 500 to 650 ° C. for an appropriate time. During the crystallization, an element that promotes crystallization of amorphous silicon, such as nickel, iron, platinum, palladium, or cobalt, may be added. When these elements are added, the crystallization temperature can be lowered and the crystallization time can be shortened.

If these elements are contained in high concentrations, the semiconductor properties of silicon are impaired, so it is desirable that the concentrations be low enough that they are sufficient for crystallization and have little influence on the semiconductor properties. In other words, the minimum value in the silicon film measured by secondary ion mass spectrometry (SIMS) is preferably a concentration of 1 × 10 ^{15 to} 3 × 10 ¹⁹ atoms / cm ³ . Since the concentration distribution of the element that promotes crystallization varies depending on the processing method of the silicon film, the minimum value may be obtained at the interface or in the vicinity of the center of the film.

The second method is a so-called laser annealing method in which an amorphous silicon film is crystallized by irradiating strong light such as laser. Which one of the first and second methods is selected may be determined in consideration of the characteristics of TFTs required by those implementing the present invention, available devices, capital investment, and the like. .
Further, the first method and the second method may be combined. For example, after crystallizing by thermal annealing, a method of further increasing crystallinity by laser annealing may be used. In particular, when thermal annealing was performed with the addition of a crystallization-promoting element such as nickel, it was observed that amorphous portions remained at the grain boundaries and the like. A laser annealing method is effective for achieving this.

Conversely, by thermally annealing a silicon film crystallized by a laser annealing method, the stress strain of the film caused by laser annealing can be relaxed.
Although the thermal oxide film obtained by the present invention can be used as a gate insulating film as it is, in order to improve the characteristics, the obtained thermal oxide film is made of ammonia (NH ₃ ), hydrazine (N ₂ H _4). ) Or the like in a hydrogen nitride atmosphere such as 400 ° C. to 700 ° C. By this thermal annealing step, the dangling bonds of the thermal oxide film are completely filled with nitrogen, and part of the oxygen is replaced with nitrogen, so that an electrically stable silicon oxynitride film can be obtained.

  Further, only the thermal oxide film obtained by the present invention may be used as the gate insulating film. However, if the thermal oxide film does not reach the target thickness, a PVD method, a CVD method, or the like is further provided thereon. Alternatively, an insulating film mainly composed of silicon oxide may be stacked to use a multilayered insulating film as the gate insulating film. Insulating films obtained by PVD, CVD, etc. have remarkably poor characteristics compared to thermal oxide films. However, if at least the surface of the active layer is covered with a thermal oxide film of 20 nm or more, the influence on the TFT characteristics Is small enough.

  As a method for manufacturing such an insulating film, for example, a sputtering method may be used as the PVD method, and a plasma CVD method, a low pressure CVD method, or an atmospheric pressure CVD method may be used as the CVD method. Other film forming methods can also be used. As the plasma CVD method and the low pressure CVD method, a method using TEOS as a raw material may be used. In order to deposit a silicon oxide film using TEOS and oxygen as raw materials by the plasma CVD method, the substrate temperature is preferably 200 to 500 ° C. In addition, the reaction using TEOS and ozone in the low pressure CVD method proceeds at a relatively low temperature (for example, 375 ° C. ± 20 ° C.), and a silicon oxide film that is not damaged by plasma can be obtained.

Similarly, a silicon oxide film that is not damaged by plasma can be obtained by reacting monosilane (SiH ₄ ) and oxygen (O ₂ ) or monosilane and nitrogen oxides such as dinitrogen monoxide as main raw materials by low pressure CVD. .
A combination of monosilane and nitrogen oxide may be used for the plasma CVD method. Further, among the plasma CVD methods, the ECR-CVD method using discharge under ECR (electron cyclotron resonance) conditions can reduce the damage caused by the plasma, so that a better gate insulating film can be formed.

According to the knowledge of the present inventor, an insulating film mainly composed of silicon oxide which is hard to some extent is suitable as a gate insulating film of TFT. As a specific index, the etching rate by buffer hydrofluoric acid at 23 ° C. mixed at a ratio of hydrofluoric acid 1, ammonium fluoride 50, and acetic acid 50 is 100 nm / min or less, typically 30-80 nm / min. It was found that a silicon oxide film is preferable. On average, 1 × 10 ¹⁷ to 1 × 10 ²¹ atoms / cm ³ of nitrogen is contained, and many silicon oxide films satisfy such an etching rate condition.

  The insulating film formed over the thermal oxide film in this manner is preferably subjected to thermal annealing in an atmosphere such as dinitrogen monoxide in order to further improve the characteristics. In that case, it is good to set it as 300-700 degreeC. In addition, if the insulating film is irradiated with ultraviolet light during thermal annealing, the effect of annealing can be enhanced, and the same effect can be achieved even at lower temperatures. This is because by making the dinitrogen monoxide active by ultraviolet light, it is possible to react better with the insulating film deposited by CVD or PVD.

  Similarly, the insulating film may be processed by generating plasma in an atmosphere containing dinitrogen monoxide. Also in this case, dinitrogen monoxide is excited and activated by plasma, and can react with the insulating film. Further, in this plasma treatment, it is necessary to lower the pressure of dinitrogen monoxide in order to generate plasma. Therefore, in order to make the reaction more complete, after the plasma treatment, monoxide of 0.1 atm or higher is used. Thermal annealing may be performed at 400 to 700 ° C. in a dinitrogen atmosphere.

  According to the present invention, the characteristics of the TFT are greatly improved. In the gate insulating film obtained by the present invention, since there are few defects that trap electrons especially when hot electrons or the like are injected, the deterioration of characteristics can be prevented and the reliability of the element is improved. Moreover, since the thermal oxide film according to the present invention is thin, there are no pinholes, so that the yield can be improved. In particular, the gate insulating film has been conventionally formed by using various PVD methods and CVD methods. However, such a film forming method generates flakes and particles, which requires much time for maintenance of the apparatus. Although the mass productivity is lowered, in the present invention, such flakes and particles are hardly generated. As a result, the maintenance time of the apparatus was shortened and the mass productivity was improved. In addition, the initial investment in carrying out the present invention is equal to or less than that of the conventional PVD method and CVD method. Thus, the present invention is an industrially useful invention.

(Function)
In order to advance the oxidation reaction of silicon, it was necessary to form atomic oxygen having an oxidizing action or an oxidizing molecule having high reactivity equivalent to that in the atmosphere. However, a very high temperature is required to obtain atomic oxygen or the like from oxygen molecules. For this reason, thermal oxidation did not proceed unless the temperature was 1000 ° C. or higher in a dry oxygen atmosphere.

  The present invention heats nitrogen oxides, oxygen, and ozone, and thermally excites or decomposes them to obtain atomic oxygen or excited nitrogen oxides under appropriate conditions. It pays attention to the fact that the lifetime is sufficiently long and spatial movement is possible. In other words, gas molecules and atoms that are heated to high temperatures and made reactive are guided to a lower temperature reaction chamber and used for thermal oxidation, so thermal oxidation proceeds even at low temperatures compared to conventional thermal oxidation methods. To do. In the present invention, in order to obtain more atomic oxygen or nitrogen oxide molecules in an excited state, it is preferable to use nitrogen oxide, oxygen, and ozone by heating them to a temperature equal to or higher than their decomposition temperature.

  In the present invention, when a silicon film crystallized by thermal annealing is used, the following effects are accompanied. In general, the thinner the gate insulating film and the active layer, the better the characteristics of improved mobility and reduced off-current. On the other hand, the initial amorphous silicon film is easily crystallized as the film thickness increases. Therefore, conventionally, there has been a contradiction in terms of characteristics and process regarding the thickness of the active layer. The present invention solves this contradiction for the first time. That is, a thick amorphous silicon film is formed before crystallization to obtain a silicon film having good crystallinity, and then the silicon film is oxidized. By doing so, the silicon film is thinned, and the characteristics as a TFT are improved. Further, this thermal oxidation has a feature that the amorphous component and the crystal grain boundary in which recombination centers are likely to exist are easily oxidized, and as a result, the number of recombination centers in the active layer is reduced. This increases the product yield.

  When the present invention is applied to an active layer made of a crystalline silicon film crystallized by adding an element that promotes crystallization of an amorphous silicon film such as nickel, cobalt, iron, platinum, palladium, etc. It has the effect of. The crystallinity of the silicon film crystallized by adding such crystallization-promoting elements is particularly good, and the field effect mobility is very high. A good one was desired. The gate insulating film according to the present invention is suitable for it. In addition, in the thermal oxidation process of the present invention, the amorphous region remaining in the crystal grain boundary or the like can be crystallized, and the crystallinity can be further improved.

When the present invention is applied to an active layer using a silicon film subjected to laser annealing, in addition to the effect of improving the characteristics of the gate insulating film during the thermal oxidation process of the present invention, laser annealing This also has the effect of simultaneously relaxing the strain on the silicon film generated by the annealing process.
Further, when it is used for a silicon film having a very good crystallinity such as a monodomain structure, the gate insulating film is required to have the same characteristics as a thermal oxide film, but the thermal oxide film obtained by the present invention has its purpose. It conforms to.

  FIG. 2 shows a cross-sectional view of the manufacturing process of this embodiment. First, a base film 202 of silicon oxide having a thickness of 200 nm was formed on a substrate (Corning 7059) 201 by a sputtering method. The substrate is annealed at a temperature higher than the strain point before or after the formation of the base film, and then slowly cooled to a temperature below the strain point at a temperature drop rate of 0.1 to 1.0 ° C./min. Subsequent shrinkage of the substrate in the process (including the thermal oxidation process of the present invention and the subsequent thermal annealing process) accompanied by a temperature rise is easy, and mask alignment becomes easy. Since the strain point of the Corning 7059 substrate is 593 ° C., annealing is performed at 620 to 660 ° C. for 1 to 4 hours, and thereafter, 0.03 to 1.0 ° C./min, preferably 0.1 to 0.3 ° C./min. It is good to take out when it cools and the temperature falls to 400-500 degreeC.

  Next, an intrinsic (I-type) amorphous silicon film having a thickness of 50 to 150 nm, for example, 100 nm was formed by plasma CVD. Then, it is crystallized by thermal annealing at 600 ° C. for 48 hours in a nitrogen atmosphere (atmospheric pressure), and the silicon film is patterned to a size of 10 to 1000 μm square to form an island-like silicon film (active layer of TFT) 203. Formed. (Fig. 1 (A))

Thereafter, the thermal oxidation treatment of the present invention was performed to form a thermal oxide film 204 on the surface of the active layer 203. In this example, the apparatus shown in FIG. 1 was used. Moreover, dinitrogen monoxide was used as a gas used for thermal oxidation. In this example, the temperature T _A of the first reaction chamber 1 was preferably 750 to 950 ° C., and the temperature T _C of the second reaction chamber 5 was preferably 500 to 650 ° C. In this example, T _A was 850 ° C. and T _B was 600 ° C. Further, the temperature T _B of the passage 4 was 750 ° C. in between. The pressure in each reaction chamber was atmospheric pressure. The flow rate of dinitrogen monoxide was 5 liters / minute in this example. Furthermore, the thermal oxidation time was 0.5 to 6 hours, for example, 2 hours in this example. As a result, a thermal oxide film 204 having a thickness of about 100 nm was formed. (Fig. 2 (B))

  It should be noted that due to such thermal oxidation, the surface of the initial silicon film was reduced by 5 nm or more, and as a result, the contamination of the outermost surface portion of the silicon film did not reach the silicon-silicon oxide interface. That is. That is, a clean silicon-silicon oxide interface was obtained. Since the thickness of the silicon oxide film is twice that of the silicon film to be oxidized, the silicon film having a thickness of 100 nm is obtained by oxidizing the silicon film having a thickness of 100 nm. The thickness was 50 nm.

After the gate insulating film was formed by thermal oxidation, polycrystalline silicon (containing 0.01 to 0.2% phosphorus) having a thickness of 300 to 800 nm, for example, 600 nm was formed by low pressure CVD. Then, the silicon film was etched to form the gate electrode 205. Further, an impurity imparting N conductivity type (phosphorus in this case) was added to the active layer 203 by ion doping (also called plasma doping) in a self-aligning manner using this silicon film as a mask. As the doping gas, phosphine (PH ₃ ) was used, and the acceleration voltage was set to 60 to 90 kV, for example, 80 kV. The dose was 1 × 10 ¹⁴ to 8 × 10 ¹⁵ atoms / cm ² , for example, 1 × 10 ¹⁵ atoms / cm ² . As a result, N-type impurity regions (source and drain) 206 and 207 were formed.

Thereafter, light annealing was performed by laser light irradiation. As the laser light, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was used, but other lasers may be used. The laser light was irradiated at an energy density of 200 to 400 mJ / cm ² , for example, 250 mJ / cm ^2, and ² to 10 shots, for example, 2 shots were irradiated at one place. The effect may be increased by heating the substrate to about 200 to 450 ° C. during the laser light irradiation. (Fig. 2 (C))

  Further, the light annealing step may be a method by lamp annealing using near infrared light. Near-infrared rays are more easily absorbed by crystallized silicon than amorphous silicon, and effective annealing comparable to thermal annealing at 1000 ° C. or higher can be performed. On the other hand, the glass substrate (far infrared light is absorbed by the glass substrate, but visible / near infrared light (wavelength 0.5 to 4 μm) is hardly absorbed) is hardly absorbed. Since it is not heated and only a short processing time is required, it can be said that it is an optimal method in a process in which shrinkage due to heat of the glass substrate is a problem.

  Subsequently, a silicon oxide film 208 having a thickness of 600 nm was formed as an interlayer insulator by a plasma CVD method. Further, contact holes were formed, and TFT electrodes / wirings 209 and 210 were formed of a metal material, for example, a multilayer film of titanium nitride and aluminum. The TFT was completed through the above steps. (Fig. 2 (D))

The mobility of the TFT obtained by the method described above was 110 to 150 cm ² / Vs, and the S value was 0.2 to 0.5 V / digit. Further, when a P-channel TFT in which boron is doped in the source / drain by a similar method is also produced, the mobility is 90 to 120 cm ² / Vs, the S value is 0.4 to 0.6 V / digit, Compared with the case where the gate insulating film is formed by the PVD method or the CVD method, the mobility is 20% or more higher and the S value is reduced by 20% or more.
Also, from the viewpoint of reliability, the TFT manufactured in this example showed a good result that is not inferior to a TFT manufactured by high-temperature thermal oxidation at 1000 ° C.

  This embodiment relates to a manufacturing process of a TFT used for controlling an active matrix pixel. FIG. 3 shows a manufacturing process of this example. First, as in Example 1, the glass substrate (Corning 7059) was annealed at 620 to 660 ° C. higher than the strain point (593 ° C.), for example, 640 ° C. for 1 to 4 hours, for example 1 hour, and then 0.03 It was gradually cooled at ˜1 ° C./min, for example 0.2 ° C./min, and taken out when the temperature dropped to 400 to 500 ° C., for example 450 ° C.

  The substrate 301 subjected to such treatment was cleaned, and a silicon oxide base film 302 having a thickness of 200 nm was formed by plasma CVD using TEOS (tetraethoxysilane) and oxygen as source gases. Then, an intrinsic (I-type) amorphous silicon film 303 having a thickness of 50 to 150 nm, for example, 100 nm was formed by plasma CVD. Next, a silicon oxide film 305 having a thickness of 50 to 200 nm, for example, 100 nm was continuously formed by a plasma CVD method. Then, the silicon oxide film 305 was selectively etched to form a region 306 where amorphous silicon was exposed. Then, a nickel film 307 having an average thickness of 2 to 5 nm was formed on the entire surface by sputtering. The nickel film may not be a continuous film. Further, a spin coating method may be used instead of the sputtering method.

Here, nickel has a function of promoting crystallization of amorphous silicon. By using nickel, crystallization can be performed at a lower temperature and in a shorter time than the normal solid phase growth temperature.
Thereafter, heat annealing was performed in a nitrogen atmosphere at 500 to 620 ° C., for example, 550 ° C. for 8 hours, and the silicon film 303 was crystallized. Crystallization proceeded in a direction parallel to the substrate as indicated by the arrow, starting from a region 306 where the nickel and silicon films were in contact. In the figure, a region 304 indicates a crystallized portion, and a region 303 indicates an uncrystallized (amorphous) portion. (Fig. 3 (A))

Next, the silicon oxide film 305 was removed, and after patterning the silicon film 304, dry etching was performed to form an island-shaped active layer region 308. At this time, a region indicated by 306 in FIG. 3A is a region where nickel is directly introduced, and is a region where nickel is present at a high concentration. It has also been confirmed that nickel is also present at a high concentration at the tip of crystal growth. In these regions, it has been found that the nickel concentration is nearly an order of magnitude higher than the middle region. Therefore, in this example, in the active layer 308, these high nickel concentration regions were not overlapped with the channel formation region. The nickel concentration in the active layer of this example was about 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atoms cm ^{−3 as} measured by SIMS (secondary ion mass spectrometry).

After forming the active layer, the gate insulating film 309 was formed by performing the thermal oxidation process of the present invention. Also in this example, the thermal oxidation apparatus of FIG. 1 was used. For the thermal oxidation, a mixed gas of dinitrogen monoxide and argon (dinitrogen monoxide: argon = 1: 1) is used, the temperature T _A of the first reaction chamber 1 is 700 ° C., and the temperature T _{B of the} passage 4 is 650. The temperature T _C of the second reaction chamber was 600 ° C. The pressure in the reaction chamber was 1 atm, the flow rate of the reaction gas was 3 liters / minute, and the thermal oxidation time was 2 hours. In this example, reticulated platinum was provided in the first reaction chamber 1 as a catalyst. For this reason, since the temperature of the first reaction chamber was decreased as compared with Example 1, and the decomposition of dinitrogen monoxide could be promoted, a smaller amount of dinitrogen monoxide could be used. It was possible to obtain the same effect. Thus, a silicon oxide film 309 having a thickness of about 100 nm was obtained. (Fig. 3 (B))

Subsequently, an aluminum film (containing 0.01 to 0.2% scandium) having a thickness of 300 to 800 nm, for example, 600 nm was formed by a sputtering method. Then, the aluminum film was etched to form the gate electrode 310. (Figure 3 (C))
Further, the surface of the aluminum electrode was anodized to form an oxide layer 311 on the surface. This anodization was performed in an ethylene glycol solution containing 1 to 5% tartaric acid. The solution was adjusted to pH = 6.8-7.2 using ammonia. The thickness of the obtained oxide layer 311 was 200 nm. Note that since the oxide 311 has a thickness for forming an offset gate region in a subsequent ion doping step, the length of the offset gate region can be determined in the anodic oxidation step. (Fig. 3 (D))

Next, an impurity imparting N conductivity type (phosphorus in this case) is added in a self-aligned manner to the active layer 308 by ion doping using the gate electrode portion, that is, the gate electrode 310 and the surrounding oxide layer 311 as a mask. . As the doping gas, phosphine (PH ₃ ) was used, and the acceleration voltage was set to 60 to 90 kV, for example, 80 kV. The dose was 1 × 10 ¹⁴ to 8 × 10 ¹⁵ atoms / cm ² , for example, 4 × 10 ¹⁵ atoms / cm ² . As a result, N-type impurity regions 312 and 313 can be formed. As is apparent from the figure, the impurity region and the gate electrode are offset by a distance x. Such an offset state is particularly effective in reducing leakage current (also referred to as off-current) when a reverse voltage (minus in the case of an N-channel TFT) is applied to the gate electrode. In particular, in the TFT for controlling the pixels of the active matrix as in this embodiment, it is desired that the leakage current is low so that the charge accumulated in the pixel electrode does not escape in order to obtain a good image. It was effective.

Thereafter, light annealing was performed by laser light irradiation. As the laser light, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was used. The laser light was irradiated at an energy density of 200 to 400 mJ / cm ² , for example, 250 mJ / cm ^2, and ² to 10 shots, for example, 2 shots were irradiated at one place. The effect may be increased by heating the substrate to about 200 to 450 ° C. during the laser light irradiation. (Figure 3 (E))
Subsequently, a silicon oxide film 314 having a thickness of 600 nm was formed as an interlayer insulator by a plasma CVD method. Further, a transparent conductive film (ITO film) having a thickness of 80 nm was formed on the silicon oxide film 314 by sputtering, and this was etched to form a pixel electrode 315.

Then, contact holes were formed in the interlayer insulator 314 and the gate insulating film 309, and TFT electrodes and wirings 316 and 317 were formed of a metal material, for example, a multilayer film of titanium nitride and aluminum. Finally, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere of 1 atm to complete an active matrix pixel circuit having TFTs. (Fig. 3 (F))
An active matrix circuit was formed as described above. In order to protect the circuit, a protective film (passivation film) such as silicon nitride may be formed so as to cover the TFT.

  FIG. 4 shows a cross-sectional view of the manufacturing process of this example. First, as for the substrate 401, Corning 7059 was used in the same manner as in Example 1, and a 200 nm thick silicon oxide base film 402 was formed by a plasma CVD method using TEOS as a raw material. Then, an intrinsic (I-type) amorphous silicon film having a thickness of 10 to 100 nm, for example, 80 nm was formed by plasma CVD.

  Then, a trace amount of an element that promotes crystallization of amorphous silicon, such as nickel, iron, platinum, palladium, and cobalt, was added to the amorphous silicon film and thermally annealed to obtain a crystalline silicon film. In this example, a nickel acetate solution was dropped on the amorphous silicon film, and a very thin film of nickel acetate was formed on the amorphous silicon film by a spin dry method. Then, nickel was introduced into the amorphous silicon film and crystallized by performing thermal annealing at 550 ° C. for 4 hours in a nitrogen atmosphere.

Thereafter, in order to further improve the crystallinity, laser annealing was performed using a KrF excimer laser (wavelength 248 nm). An appropriate laser energy density was 250 to 350 mJ / cm ² . In this example, it was set to 300 mJ / cm ² . As described above, a crystalline silicon film could be obtained. The crystalline silicon film thus obtained has a monodomain structure that is relatively large (-10 μm square) crystal grains and exhibits the same crystal orientation in the range of several to ten-fold times. Was.

  Next, a silicon nitride film was formed and etched to form a silicon nitride mask 405. Then, using the mask 405, the silicon film was etched by a 30 nm dry etching method to form a thick region 403 and a thin region 404 of the silicon film. The thick region 405 of the silicon film becomes an active layer of the TFT. In this example, such an active layer was randomly formed, and many of them were observed in which the channel formation region of the TFT had a monodomain structure. (Fig. 4 (A))

  Further, with the mask 405 attached, the thermal oxidation treatment of the present invention was performed to oxidize the thin region 404 and form a silicon oxide film 407. In this example, the apparatus shown in FIG. 6 was used. In this apparatus, a portion corresponding to the first reaction chamber 1 in FIG. 1 is not particularly provided, and a reaction chamber 61 is heated by partially heating a reaction gas introduction pipe 63 with a heater 64 to make the gas reactive. It has the structure introduced into. A plurality of susceptors 65 were provided in the reaction chamber 61, and a substrate 66 was installed in each. The reaction chamber 61 is kept at a constant temperature by a heater 62. In the present embodiment, the inner diameter of the introduction pipe 63 is 20 to 25 mmφ. The distance from the position of the heater 64 to the reaction chamber was suitably 10 to 150 cm.

In the apparatus of FIG. 6, the temperature of the introduction pipe in the portion where the heater 64 is provided is a temperature at which the gas decomposes, and the temperature from the portion to the reaction chamber is higher than the temperature T _C of the reaction chamber 61. It was made to become.
In this embodiment, dinitrogen monoxide was used as the thermal oxidation atmosphere. Nitrogen monoxide was allowed to flow through the introduction pipe 63 at a flow rate of 5 liters / minute. In the heater 64, it was good to set the temperature to 750 to 950 ° C. The temperature of the reaction chamber 61 was preferably 500 to 650 ° C. In this example, the temperature of the heater 64 was 900 ° C., and the temperature of the reaction chamber 61 was 550 ° C. Under the above conditions, thermal oxidation was performed for 4 hours. As a result, a silicon oxide film 407 having a thickness of about 100 nm was formed. As a result, the thick silicon film regions 403 were surrounded by the silicon oxide 407 and insulated from each other.

Thereafter, the mask 405 was removed to expose the surface of the thick silicon film region 403. Then, a silicon oxide film 408 was formed on the surface by the same method as the thermal oxidation of the silicon oxide 407 described above. However, since the oxidation time was 1 hour at this time, the thickness of the silicon oxide film 408 was 50 nm. Thus, the active layer 406 was formed. (Fig. 4 (B))
Subsequently, an aluminum film (containing 0.01 to 0.2% scandium) having a thickness of 300 to 800 nm, for example, 600 nm was formed by a sputtering method. Then, the aluminum film was etched to form a gate electrode 409. (Fig. 4 (C))

Further, the surface of the aluminum electrode was anodized to form an oxide layer 410 on the surface. This anodization was performed in the same manner as in Example 2. The thickness of the obtained oxide layer 410 was 200 nm. (Fig. 4 (D))
Next, an impurity imparting N conductivity type (phosphorus in this case) is added in a self-aligned manner to the active layer 406 by ion doping using the gate electrode portion, that is, the gate electrode 409 and the surrounding oxide layer 410 as a mask. . As the doping gas, phosphine (PH ₃ ) was used, and the acceleration voltage was set to 60 to 90 kV, for example, 80 kV. The dose was 1 × 10 ¹⁴ to 8 × 10 ¹⁵ atoms / cm ² , for example, 4 × 10 ¹⁴ atoms / cm ² . As a result, N-type impurity regions 411 and 412 could be formed.

Thereafter, light annealing was performed by laser light irradiation. As the laser light, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was used. The laser light was irradiated at an energy density of 200 to 400 mJ / cm ² , for example, 250 mJ / cm ^2, and ² to 10 shots, for example, 2 shots were irradiated at one place. (Fig. 4 (E))

  Subsequently, a silicon nitride film 413 was formed as an interlayer insulator by a plasma CVD method. Then, the silicon nitride interlayer insulator 413 and the silicon oxide film 408 were etched to form contact holes 414. Buffered hydrofluoric acid (for example, a mixture of hydrofluoric acid and ammonium fluoride) was used for etching the contact holes. The silicon nitride film formed by plasma CVD has a lower etching rate than the silicon oxide film formed by PVD or CVD, but in this embodiment the silicon oxide film 408 was obtained by thermal oxidation. Therefore, the etching rate was about the same as that of the silicon nitride interlayer insulator 413.

  For this reason, the obtained contact holes have almost the same diameter from top to bottom. Such a structure is effective in preventing disconnection of the wiring at the contact hole portion. Conversely, if the diameter of the lower part of the contact hole is larger than that of the upper part, the disconnection of the wiring tends to occur. In this embodiment, the silicon nitride interlayer insulator 413 also serves as a protective film for preventing water and mobile ions from entering the TFT from the outside.

After forming the contact hole, an aluminum film was formed by sputtering, and this was etched to form a source electrode / wiring 415. Further, a polyimide film 416 having a thickness of 200 nm was formed by spin coating. Then, the polyimide film 416, the silicon nitride interlayer insulator 413, and the gate insulating film 408 were etched to form contact holes 417.
Then, a transparent conductive film (ITO film) was formed and etched to form a pixel electrode 418. Thus, an active matrix circuit can be formed. (Fig. 4 (F))

In this embodiment, the thickness of the gate insulating film is 50 nm, which is thinner than those of the other embodiments, but there are no pinholes compared to those formed by using the conventional PVD method and CVD method, and the breakdown voltage is reduced. However, there was no problem in practical use. Further, in the case of having a mono-domain structure TFT as in this embodiment, the characteristics are suppressed if the gate insulating film is thicker than necessary. In that respect, if the thickness is about 50 nm as in this example, the characteristics of the monodomain structure could be sufficiently exhibited.
Further, in Examples 1 and 2, the step of the active layer is 150 nm including the gate insulating film, and the gate electrode / wiring disconnection occurs when the gate electrode has insufficient step coverage. There was also. In this respect, this embodiment is advantageous because the step coverage is extremely small.

FIG. 7 shows a cross-sectional view of the manufacturing process of this example. First, a base silicon oxide film 702 (thickness: 200 nm) and a crystalline island-shaped silicon film 703 having a thickness of 75 nm were formed over a glass substrate 401. The thermal oxidation treatment of the present invention was performed to oxidize the silicon film 703 to form a silicon oxide film 704. In this example, as in Example 3, the structure of the first reaction chamber 1 in the reactor having the structure of FIG. 1A is shown in FIG. 6A (cross-sectional view) and FIG. The one shown in the top view) was used.
In this example, 1 atm and 100% dinitrogen monoxide was flowed at a flow rate of 5 liters / minute. The temperature in the reaction chamber 2 was preferably 500 to 650 ° C. In this embodiment, the temperature was 550 ° C. Under the above conditions, thermal oxidation was performed for 1 hour. As a result, a silicon oxide film 704 having a thickness of about 50 nm was formed. (Fig. 7 (A))

  Thereafter, a silicon oxide film region 705 having a thickness of 50 nm was formed by plasma CVD. Monosilane and dinitrogen monoxide were used as raw materials. The substrate temperature was 400 to 500 ° C., for example, 430 ° C. Subsequently, an aluminum film (containing 0.01 to 0.2% scandium) having a thickness of 300 to 800 nm, for example, 600 nm was formed by a sputtering method. Then, the aluminum film was etched to form a gate electrode 706. (Fig. 7 (B))

Further, the surface of the aluminum electrode was anodized to form an oxide layer 707 on the surface. This anodization was performed in the same manner as in Example 2. The thickness of the obtained oxide layer 707 was 200 nm.
Next, an impurity imparting N conductivity type (phosphorus in this case) is added in a self-aligning manner to the active layer 704 by ion doping using the gate electrode portion, that is, the gate electrode 706 and the surrounding oxide layer 707 as a mask. . As the doping gas, phosphine (PH ₃ ) was used, and the acceleration voltage was 80 kV. The dose was 4 × 10 ¹⁴ atoms / cm ² . As a result, an N-type impurity region 708 could be formed. (Fig. 7 (C))

Thereafter, light annealing was performed by laser light irradiation. As the laser light, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was used.
Subsequently, a silicon nitride film 709 was formed as an interlayer insulator by a plasma CVD method. Then, the silicon nitride interlayer insulator 709 was etched to form a contact hole 710.

After forming the contact hole, an aluminum film was formed by sputtering, and this was etched to form a source electrode / wiring 711. Further, a silicon oxide film 712 having a thickness of 200 nm was formed by plasma CVD. Then, the silicon oxide film 712 and the silicon nitride interlayer insulator 709 were etched to form contact holes 713.
Then, a transparent conductive film (ITO film) was formed and etched to form a pixel electrode 714. Thus, an active matrix circuit can be formed. (Fig. 7 (D))
In this embodiment, the gate insulating film can be made sufficiently thick in a short time by forming a double layer of the thermal oxide film and the silicon oxide film formed by the plasma CVD method.

The conceptual diagram of the thermal oxidation apparatus for implementing this invention is shown. An example of a manufacturing process of the TFT of the present invention is shown. (See Example 1) An example of a manufacturing process of the TFT of the present invention is shown. (See Example 2) An example of a manufacturing process of the TFT of the present invention is shown. (See Example 3) The mode of low temperature (600 degrees C or less) thermal oxidation using this invention is shown. The conceptual diagram of the thermal oxidation apparatus for implementing this invention is shown. An example of a manufacturing process of the TFT of the present invention is shown. (See Example 4)

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ...... 1st reaction chamber 2 ...... Heater of 1st reaction chamber 3 .... Heater of passage 4 ...... Passage 5 ...... 2nd reaction chamber 6 ...・ Second reaction chamber heater 7... Susceptor 8... Substrate 9...

Claims (7)

Thermally exciting an atmosphere containing oxygen, ozone or nitrogen oxides in a first reaction chamber at a first temperature;
A semiconductor film containing silicon as a main component is disposed through a passage having a second temperature not higher than the first temperature, and is excited in a second reaction chamber having a third temperature not higher than the second temperature. A method of manufacturing a semiconductor device that oxidizes a surface of the semiconductor film by introducing oxygen, ozone, or nitrogen oxide,
A method for manufacturing a semiconductor device, comprising: a catalyst in the first reaction chamber; and exciting the oxygen, ozone, or nitrogen oxide by contacting the catalyst. In claim 1 ,
The method for manufacturing a semiconductor device, wherein the catalyst is a net-like metal and is heated to a temperature higher than the first temperature by passing an electric current. In claim 2 ,
The method for manufacturing a semiconductor device, wherein the catalyst is any one of platinum, palladium, reduced nickel, titanium, vanadium, and cobalt. In any one of Claim 1 thru | or 3 ,
The method for manufacturing a semiconductor device, wherein the third temperature is 400 to 700 ° C. In any one of Claims 1 thru | or 4 ,
A method for manufacturing a semiconductor device, wherein a heater is provided separately for each of the first reaction chamber, the passage, and the second reaction chamber. In any one of Claims 1 thru | or 5 ,
A method for manufacturing a semiconductor device, wherein an inner wall of the passage is made of a material whose main component is quartz. In any one of claims 1 to 6,
The method for manufacturing a semiconductor device is characterized in that the inside of the second reaction chamber is 1 atm or more and 15 atm or less.

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