JP4184644B2 - Regulator circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a regulator circuit, and more particularly to a regulator circuit with reduced standby current.
[0002]
[Prior art]
FIG. 6 shows a configuration example of a conventional regulator circuit. All transistors are bipolar. The input voltage terminal BIN is supplied with voltage from a voltage source VA. The emitter of the PNP transistor Q3 and the resistor R1 are connected to the input voltage terminal BIN. The other end of the resistor R1 is connected to the other end of a series circuit of diodes D1 to D3 whose one end is grounded. The other end of the resistor R1 is also connected to the base of the NPN transistor Q2. The collector of the transistor Q3 is connected to the voltage output terminal Vcc. The base of the transistor Q3 is connected to the collector of the transistor Q2. The voltage output terminal Vcc is grounded by a capacitor C1 and grounded by a series circuit of resistors R2 and R3. The connection point between the resistors R2 and R3 is connected to the inverting input of the comparator 102. The band gap voltage Vbg is input to the non-inverting input. The output of the comparator 102 is connected to the base of the grounded-emitter transistor Q1, and its collector is connected to the emitter of the transistor Q2.
[0003]
The operation of the conventional regulator circuit shown in FIG. 6 will be described. A power supply voltage VA is connected to the battery input terminal BIN. In the initial state, the voltage output Vcc is 0V. The voltage output Vcc is divided by voltage dividing resistors R2 and R3 to obtain a divided voltage Vs. The comparator 102 compares the divided voltage Vs with the band gap voltage Vbg. In the initial state, since the band gap voltage Vbg is higher than the divided voltage Vs, the output voltage of the comparator 102 increases. As a result, the base voltage of the transistor Q1 increases and the collector current increases. The collector current of the transistor Q1 becomes the base current of the transistor Q3 via the emitter and collector of the transistor Q2. As a result, the collector current of the transistor Q3 increases and the output voltage Vcc rises.
[0004]
When the output voltage Vcc continues to rise and the divided voltage Vs becomes higher than the band gap voltage Vbg, the output of the comparator 102 is inverted and falls. As a result, the collector current of the transistor Q1 decreases, the collector current of the transistor Q3 decreases, and the output voltage Vcc stops increasing. As a result, the output voltage Vcc is stabilized when the divided voltage Vs and the band gap voltage Vbg become equal. Since the band gap voltage Vbg used as the reference voltage is a very stable voltage, the output voltage Vcc is similarly stable.
[0005]
[Problems to be solved by the invention]
In recent years, a low standby current has been strongly demanded as a demand for an on-vehicle regulator circuit and the like. This is because the increase in the number of electrical units mounted on the vehicle tends to cause the battery to rise when left for a long time.
[0006]
In the conventional circuit shown in FIG. 6, the output current Ib1 of the comparator 102 and the current of the bias circuit must be set in accordance with the base current Ib3 at the collector maximum output current of the output transistor Q3 and the base current Ib2 of the transistor Q2. . Normally, the collector maximum output current of the output transistor Q3 is required to be 100 mA or more. Therefore, when the current amplification factor β = 100 of each of the transistors Q1 to Q3, Ib3 is 1 mA or more, and Ib2 and Ib3 are 10 μA or more. Therefore, the output current of the comparator 102 and the bias circuit current must be 10 μA or more, for example, 20 μA. Although this value seems to be small at first glance, it consumes a current of 40 μA or more. Thus, the conventional regulator circuit shown in FIG. 6 has a problem that the low standby current is insufficient.
[0007]
[Means for Solving the Problems]
The present invention has been made to solve the above-mentioned problems, and the first feature thereof is (a) a voltage input terminal, (b) a voltage output terminal, and (c) an emitter connected to the voltage input terminal. A first bipolar transistor having a collector connected to the voltage output terminal, and (d) a first resistor and a second resistor, one end of which is the collector of the first bipolar transistor and the voltage output terminal. A voltage-dividing circuit connected to a current path that connects to the other end and grounded at the other end; and (e) a current path that connects the first resistor and the second resistor to an inverting input terminal or a non-inverting input terminal. A differential circuit having a non-inverting input terminal or an inverting input terminal connected to a reference voltage source, and (f) a second circuit having an emitter or a collector grounded and a base connected to an output terminal of the differential circuit. The bipolar tiger And register, connected to the collector or emitter of the (g) source and the second bipolar transistor, and a D MOS transistor connected to the base of the drain of the first bipolar transistor, and (h) said voltage input terminal wherein a current path connecting the emitter of the first bipolar transistor and the anode side is connected to the gate of the D MOS transistor, the cathode side is to and a bias circuit including a diode connected to ground.
[0008]
The second feature of the present invention is that (a) a voltage input terminal, (b) a voltage output terminal, and (c) an emitter is connected to the voltage input terminal, and a collector is connected to the voltage output terminal. Divided voltage comprising a bipolar transistor and (d) a first resistor and a second resistor, one end connected to a current path connecting the collector of the bipolar transistor and the voltage output terminal, and the other end grounded A circuit, and (e) an inverting input terminal or a non-inverting input terminal connected to a current path connecting the first resistor and the second resistor, and a non-inverting input terminal or an inverting input terminal connected to a reference voltage source And (f) a first MOS transistor or a D MOS transistor whose source or drain is grounded and whose gate is connected to the output terminal of the differential circuit, and (g) the source is the first Is connected to the MOS transistor or the drain or the source of the D MOS transistor connected to a second D MOS transistor having a drain connected to the base of the bipolar transistor, and an emitter of the bipolar transistor and (h) said voltage input terminal current path to and the anode side to the gate of the second D MOS transistor is connected, the cathode side is to and a bias circuit including a diode connected to ground.
[0009]
Further, the third feature of the present invention is that (a) a voltage input terminal, (b) a voltage output terminal, and (c) an emitter is connected to the voltage input terminal, and a collector is connected to the voltage output terminal. Divided voltage comprising a bipolar transistor and (d) a first resistor and a second resistor, one end connected to a current path connecting the collector of the bipolar transistor and the voltage output terminal, and the other end grounded (E) a differential circuit having an inverting input terminal connected to a current path connecting the first resistor and the second resistor, and a non-inverting input terminal connected to a reference voltage source; And a DMOS (double diffusion MOS) transistor having a source grounded, a gate connected to the output terminal of the differential circuit, and a drain connected to the base of the bipolar transistor.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. It should be noted that the same components as those already described are denoted by the same reference numerals and the description thereof is omitted to avoid duplication of description.
(First embodiment)
FIG. 1 is a diagram showing a first embodiment of a regulator circuit of the present invention. As shown in FIG. 1, the regulator circuit according to the first embodiment includes (a) a voltage input terminal BIN, (b) a voltage output terminal Vcc, and (c) an emitter connected to the voltage input terminal BIN. Comprises a bipolar transistor Q3 connected to the voltage output terminal Vcc, and (d) a resistor R2 and a resistor R3, one end of which is connected to the current path connecting the collector of the bipolar transistor Q3 and the voltage output terminal Vcc, and the other end. Is grounded, and (e) the inverting input terminal is connected to the current path connecting the resistors R2 and R3, and the non-inverting input terminal is connected to the reference voltage source (bandgap voltage Vbg). A differential circuit (comparator 102); and (f) a bipolar transistor Q1 having an emitter grounded and a base connected to the output terminal of the comparator 102; G) a source connected to the collector of the bipolar transistor Q1, a DMOS transistor M1 having a drain connected to the base of the bipolar transistors Q3, and a current path connecting the emitter of the (h) voltage input terminal BIN and bipolar transistors Q3, A bias circuit including a diode whose anode side is connected to the gate of the DMOS transistor M1 and whose cathode side is grounded.
[0011]
Next, the operation of the first embodiment will be described. A power supply voltage VA is connected to the battery input terminal BIN. In the initial state, the voltage output Vcc is 0V. The voltage output Vcc is divided by voltage dividing resistors R2 and R3 to obtain a divided voltage Vs. The comparator 102 compares the divided voltage Vs with the band gap voltage Vbg. In the initial state, since the band gap voltage Vbg is higher than the divided voltage Vs, the output voltage of the comparator 102 increases. As a result, the base voltage of the bipolar transistor Q1 increases and the collector current increases. The collector current of the bipolar transistor Q1 becomes the base current of the transistor Q3 via the drain and source of the DMOS transistor M2. As a result, the collector current of the transistor Q3 increases and the output voltage Vcc rises.
[0012]
When the output voltage Vcc continues to rise and the divided voltage Vs becomes higher than the band gap voltage Vbg, the output of the comparator 102 is inverted and falls. As a result, the collector current of the transistor Q1 decreases, the collector current of the transistor Q3 decreases, and the output voltage Vcc stops increasing. As a result, the output voltage Vcc is stabilized when the divided voltage Vs and the band gap voltage Vbg become equal. Since the band gap voltage Vbg used as the reference voltage is a very stable voltage, the output voltage Vcc is similarly stable.
[0013]
According to the first embodiment, since the bipolar transistor Q2 shown in FIG. 6 is replaced with the DMOS transistor M1 shown in FIG. 1, the base current of the bipolar transistor Q2 required in the conventional circuit shown in FIG. Ib2 becomes unnecessary. Accordingly, only a minimum current necessary for generating a predetermined voltage is allowed to flow through the bias circuit including the resistor R1 and the diodes D1 to D3, so that the current consumption can be reduced. In addition, since the DMOS transistor has a higher breakdown voltage than the bipolar transistor, there is an effect that the breakdown voltage is improved.
[0014]
A normal MOS transistor can be used instead of the DMOS transistor. The bipolar transistor Q1 may be either an npn type or a pnp type. In that case, needless to say, it is necessary to take measures such as reversing the inverting input and the non-inverting input of the comparator 102.
[0015]
(Second Embodiment)
FIG. 2 is a diagram showing a second embodiment of the regulator circuit of the present invention. As shown in FIG. 2, the regulator circuit according to the second embodiment has (a) a voltage input terminal BIN, (b) a voltage output terminal Vcc, and (c) an emitter connected to the voltage input terminal BIN. Comprises a bipolar transistor Q3 connected to the voltage output terminal Vcc, and (d) a resistor R2 and a resistor R3, one end of which is connected to the current path connecting the collector of the bipolar transistor Q3 and the voltage output terminal Vcc, and the other end. Is grounded, and (e) the inverting input terminal is connected to the current path connecting the resistors R2 and R3, and the non-inverting input terminal is connected to the reference voltage source (bandgap voltage Vbg). A differential circuit (comparator 102), (f) a DMOS transistor M2 whose source is grounded, and whose gate is connected to the output terminal of the comparator 102; Source connected to the drain of DMOS transistor M2, a DMOS transistor M1 having a drain connected to the base of the bipolar transistors Q3, and a current path connecting the emitter of the (h) voltage input terminal BIN and bipolar transistors Q3, DMOS transistor A bias circuit including a diode whose anode side is connected to the gate of M1 and whose cathode side is grounded.
[0016]
The operation of the second embodiment is substantially the same as the operation of the first embodiment. However, according to the second embodiment, the bipolar transistor Q1 shown in FIG. 1, since replaced with DMOS transistor M 2 shown in FIG. 2, the driving current of the comparator 102 in comparison with the conventional current Ib1 is Very little is required and the circuit operating current can be reduced. As a result, current consumption can be reduced.
[0017]
Since the DMOS transistor M1 does not require a large drain-source breakdown voltage for the DMOS transistor M2, for example, a normal MOS transistor can be used instead of the DMOS transistor M2. The DMOS transistor M2 may be either an n-channel type or a p-channel type. In that case, needless to say, it is necessary to take measures such as reversing the inverting input and the non-inverting input of the comparator 102.
[0018]
(Third embodiment)
FIG. 3 is a diagram showing a third embodiment of the regulator circuit of the present invention. As shown in FIG. 3, the regulator circuit of the third embodiment has a current path that connects the output terminal of the comparator 102 and the gate of the DMOS transistor M2 to the regulator circuit of the second embodiment. A Zener diode ZD, which is connected and whose anode is grounded, is added.
[0019]
The operation of the third embodiment is substantially the same as the operation of the second embodiment. However, in the third embodiment, since the Zener diode ZD is added between the gate and the ground of the DMOS transistor M2, the upper limit of the gate voltage of the DMOS transistor M2 is limited by the Zener diode ZD. It becomes possible to avoid the occurrence of gate breakdown.
[0020]
A normal MOS transistor can be used instead of the DMOS transistor. The DMOS transistor M2 may be either an n-channel type or a p-channel type. In that case, needless to say, it is necessary to take measures such as reversing the inverting input and the non-inverting input of the comparator 102.
[0021]
(Fourth embodiment)
FIG. 4 is a diagram showing a fourth embodiment of the regulator circuit of the present invention. As shown in FIG. 4, the regulator circuit of the fourth embodiment includes (a) a voltage input terminal BIN, (b) a voltage output terminal Vcc, and (c) an emitter connected to the voltage input terminal BIN, Comprises a bipolar transistor Q3 connected to the voltage output terminal Vcc, and (d) a resistor R2 and a resistor R3, one end of which is connected to the current path connecting the collector of the bipolar transistor Q3 and the voltage output terminal Vcc, and the other end. And (e) a differential circuit (comparator 102) having an inverting input terminal connected to a current path connecting the resistor R2 and the resistor R3, and a non-inverting input terminal connected to a reference voltage source. ) And (f) DM whose source is grounded, whose gate is connected to the output terminal of the comparator 102, and whose drain is connected to the base of the bipolar transistor Q3. It includes a S (double diffused MOS) transistor. In the fourth embodiment, the bias circuit composed of the resistor R1 and the diodes D1 to D3 of the first embodiment is deleted, the transistor Q1 is replaced with a DMOS transistor M2, and the drain of the DMOS transistor M2 is a bipolar transistor. It is connected directly to the base of Q3.
[0022]
The operation of the fourth embodiment is almost the same as the operation of the second embodiment. However, in the fourth embodiment, since a bias circuit is unnecessary, current consumption can be reduced accordingly. Moreover, since the drain-source breakdown voltage of the DMOS transistor is high, this configuration does not cause a breakdown voltage problem. Furthermore, since the on-resistance of the DMOS transistor is very low, the element size when the same current flows can be reduced, and the cost can be reduced.
[0023]
(Fifth embodiment)
FIG. 5 is a diagram showing a fifth embodiment of the regulator circuit of the present invention. As shown in FIG. 5, the regulator circuit of the fifth embodiment has a current path that connects the output terminal of the comparator 102 and the gate of the DMOS transistor M2 to the regulator circuit of the fourth embodiment. A Zener diode ZD, which is connected and whose anode is grounded, is added.
[0024]
The operation of the fifth embodiment is substantially the same as the operation of the fourth embodiment. However, in the fourth embodiment, since the Zener diode ZD is added between the gate and the ground of the DMOS transistor M2, the upper limit of the gate voltage of the DMOS transistor M2 is limited by the Zener diode ZD. It becomes possible to avoid the occurrence of gate breakdown.
[0025]
A normal MOS transistor can be used instead of the DMOS transistor.
[0026]
【The invention's effect】
According to the present invention, it is possible to reduce the standby current of the regulator circuit, and even when the battery is left for a long period of time, it is difficult for the in-vehicle battery or the like to rise.
[Brief description of the drawings]
FIG. 1 is a diagram showing a first embodiment of a regulator circuit of the present invention.
FIG. 2 is a diagram showing a second embodiment of a regulator circuit of the present invention.
FIG. 3 is a diagram showing a third embodiment of a regulator circuit of the present invention.
FIG. 4 is a diagram showing a fourth embodiment of the regulator circuit of the present invention.
FIG. 5 is a diagram showing a fifth embodiment of a regulator circuit of the present invention.
FIG. 6 is a diagram showing a configuration example of a conventional regulator circuit.
[Explanation of symbols]
102 comparator (differential circuit), 104 voltage divider circuit,
BIN voltage input terminal, Vcc voltage output terminal,
Q1-Q3 bipolar transistors, R1-R3 resistors,
Vbg band gap voltage (reference voltage source),
D1-D3 diode

Claims (5)

(B) a voltage input terminal, (b) a voltage output terminal,
(C) a first bipolar transistor having an emitter connected to the voltage input terminal and a collector connected to the voltage output terminal;
(D) a voltage dividing circuit comprising a first resistor and a second resistor, one end connected to a current path connecting the collector of the first bipolar transistor and the voltage output terminal, and the other end grounded When,
(E) Difference in which an inverting input terminal or a non-inverting input terminal is connected to a current path connecting the first resistor and the second resistor, and a non-inverting input terminal or an inverting input terminal is connected to a reference voltage source Dynamic circuit,
(F) a second bipolar transistor whose emitter or collector is grounded and whose base is connected to the output terminal of the differential circuit;
(G) a source connected to the collector or emitter of the second bipolar transistor, and a D MOS transistor having a drain connected to the base of said first bipolar transistor,
(H) a current path connecting the emitter of said voltage input terminal and the first bipolar transistor and the anode side is connected to the gate of the D MOS transistor, the cathode side and a bias circuit including a diode connected to ground A regulator circuit characterized by that. (B) a voltage input terminal, (b) a voltage output terminal,
(C) a bipolar transistor having an emitter connected to the voltage input terminal and a collector connected to the voltage output terminal;
(D) a voltage dividing circuit comprising a first resistor and a second resistor, one end connected to a current path connecting the collector of the bipolar transistor and the voltage output terminal, and the other end grounded;
(E) Difference in which an inverting input terminal or a non-inverting input terminal is connected to a current path connecting the first resistor and the second resistor, and a non-inverting input terminal or an inverting input terminal is connected to a reference voltage source Dynamic circuit,
(F) a first MOS transistor or a D MOS transistor whose source or drain is grounded and whose gate is connected to the output terminal of the differential circuit;
(G) a source connected to the drain or source of said first MOS transistor or D MOS transistor, and a second D MOS transistor having a drain connected to the base of the bipolar transistor,
(H) a current path connecting the emitter of said voltage input terminal and said bipolar transistors and, and a bias circuit including an anode side connected to the gate of the second D MOS transistor, the cathode side is grounded diode A regulator circuit characterized by that. Furthermore, the cathode is connected to a current path connecting the gate of the output terminal and the first D MOS transistor of the differential circuit, the regulator circuit according to claim 2, wherein the anode and a Zener diode connected to ground. (B) a voltage input terminal, (b) a voltage output terminal,
(C) a bipolar transistor having an emitter connected to the voltage input terminal and a collector connected to the voltage output terminal;
(D) a voltage dividing circuit comprising a first resistor and a second resistor, one end connected to a current path connecting the collector of the bipolar transistor and the voltage output terminal, and the other end grounded;
(E) a differential circuit having an inverting input terminal connected to a current path connecting the first resistor and the second resistor, and a non-inverting input terminal connected to a reference voltage source;
(F) a regulator comprising: a DMOS (double diffusion MOS) transistor having a source grounded, a gate connected to an output terminal of the differential circuit, and a drain connected to a base of the bipolar transistor; circuit.  5. The regulator circuit according to claim 4, further comprising a Zener diode having a cathode connected to a current path connecting an output terminal of the differential circuit and a gate of the DMOS transistor, and an anode grounded.

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