JPH0668521B2 - Power supply voltage detection circuit - Google Patents

Description

The present invention relates to a power supply voltage detection circuit used in a semiconductor integrated circuit, and in particular, it selectively detects a plurality of power supply voltage levels. The present invention relates to a multi-value level detection circuit for

(Prior Art) As shown in FIG. 10 (a) or (b), the conventional power supply voltage detection circuit has two intermediate level voltages V _A and V _{B having} different level transition tendencies with respect to the power supply voltage V _DD . Generate this both voltage V
_A, the V _B was compared by the voltage comparator CP, the two voltages V _A, was used to detect the V _DD voltage level is V _B becomes equal. In this case, the voltage V _A, one V _A of V _B to the reference voltage and the other V _B and compare the voltage, the series circuit or the power supply voltage dividing resistor R between resistors R or diode D and a constant current source I _{O 1} and R ₂ .

By the way, the above-mentioned circuit is, for example, an LSI (Large Scale Integrated Circuit)
When it is provided inside, the circuit constant is fixed and therefore only the voltage at one set point can be detected. Therefore, in order to detect a multi-valued power supply level by the conventional power supply voltage detection circuit described above, it is necessary to prepare a plurality of sets of power supply voltage detection circuits having different circuit constants. There arises a problem that the occupied pattern area increases and the current consumption increases.

(Problems to be Solved by the Invention) In the present invention, when a plurality of sets of conventional power supply voltage detection circuits as described above are provided in an integrated circuit to detect a multi-valued level of the power supply voltage, the pattern area increases and It was made to solve the problem of increased current consumption,
An object of the present invention is to provide a power supply voltage detection circuit that has a simple circuit configuration for selectively detecting multi-valued power supply levels, has a small pattern area, and consumes less current.

[Structure of the Invention] (Means for Solving Problems) A power supply voltage detection circuit of the present invention includes a bias circuit for generating a constant voltage bias and a bias from the bias circuit to generate a plurality of reference voltages. A reference voltage circuit that
A power supply voltage dividing circuit for generating a plurality of power supply voltage dividing voltages; a voltage comparator for comparing one divided voltage generated by the power source voltage dividing circuit with one reference voltage generated by the reference voltage circuit; Receiving the output of the voltage comparator, while controlling the reference voltage circuit to selectively output a plurality of reference voltages, and controlling the power supply voltage dividing circuit, the reference voltage output from the reference voltage circuit. A control circuit for selectively outputting a corresponding power supply voltage division voltage, wherein the control circuit responds to the changed power supply voltage when the power supply voltage changes and the output of the voltage comparator changes. The reference voltage circuit and the power supply voltage division circuit are controlled so that the reference voltage and the power supply voltage division voltage are output.

(Operation) It is possible to control so as to output a required voltage from the reference voltage circuit and the power supply voltage dividing circuit by the control signal, and it is possible to selectively detect a multivalued power supply level. Therefore, it is not necessary to prepare a plurality of sets of power supply voltage detection circuits, and it is sufficient to prepare some reference voltage circuits or power supply division circuits having different constants, so that the circuit pattern area can be small and the current consumption can be small. It can be small.

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a power supply voltage detection circuit for detecting a multivalued power supply level provided in an LSI. That is, reference numeral 1 is a power supply voltage dividing circuit that selects one of a plurality of divided values obtained by dividing the power supply voltage V _DD according to a control signal input and outputs the selected voltage. _{Reference numeral} 2 is a bias circuit that outputs a constant level bias voltage that does not depend on the value of the power supply voltage V _DD .
Reference numerals 3 ₁ , 3 ₂ , ... Are reference voltage circuits that perform constant current operation by receiving the bias voltage and generate reference voltages different from each other. Correspondingly, they are operated by the switch circuits 4 ₁ , 4 ₂ ,. Inactive control is performed. Reference numeral 5 is a selection gate for selectively deriving each output voltage (a plurality of reference voltage outputs) of the reference voltage circuits 3 ₁ , 3 ₂ , ... In response to a control signal input. A voltage comparator 6 compares the selected output voltage of the selection gate 5 with the divided output voltage of the power supply voltage dividing circuit 1. Reference numeral 7 denotes a control signal which is selectively supplied to the switch circuits 4 ₁ , 4 ₂ , ... Corresponding to a multivalued power supply voltage level to be detected, and a predetermined divided output voltage is supplied to the power supply voltage dividing circuit 1. Is a control circuit for supplying a control signal for taking out the control signal and a control signal for controlling the selection operation of the selection gate 5,
The output of the voltage comparator 6 is sent as a detection output in association with the multivalued power supply voltage level to be detected.

The power supply voltage dividing circuit 1 is, for example, as shown in FIG.
Alternatively, it is configured as shown in (b). That is, the second
The circuit in Fig. (A) is composed of multiple N-channel MOS transistors (four in this example) of the same size, with the gate and drain connected to each other between the V _DD power supply end and the V _SS power supply end (ground end). The transistors T _{1 to} T ₄ are connected in series and the transistor T
_3, N-channel MOS transistor T ₅ which is switch-controlled by the switch control signal S1 between an interconnection point and the installation end of the T ₄ is connected to the interconnection point and the ground terminal of the transistor T _2, T ₃ In between, an N-channel MOS transistor T ₆ which is switch-controlled by a switch control signal S2
Are connected, and the divided output voltage is taken out from the interconnection point of the transistors T ₁ and T ₂ . In this case, when the transistor T ₆ is turned on, the divided output voltage is When the transistor T ₅ is turned on, the divided output voltage becomes Then, when the transistors T ₅ and T ₆ are both turned off, the divided output voltage becomes become.

Also, in the circuit of FIG. 2 (b), four N-channel MOS transistors T _{1 to} T ₄ are connected between the V _DD power supply terminal and the ground terminal similarly to the circuit of FIG. 2 (a). However, a P-channel MOS for controlling the switch is provided between the interconnection point of the transistors T ₁ and T ₂ and the V _DD power source terminal and between the interconnection point of the transistors T ₂ and T ₃ and the V _DD power source terminal, respectively. The transistors T ₇ and T ₈ are connected to each other, and the transistors T ₃ and T ₄ are connected.
The divided output voltage is taken out from the interconnection point of. Therefore, when the transistor T ₈ is turned on, the divided output voltage becomes When the transistor T ₇ is turned on, the divided output voltage becomes Then, when the transistors T ₇ and T ₈ are both turned off, the divided output voltage becomes become.

In the circuits shown in FIGS. 2 (a) and 2 (b), the transistors T _{1 to} T ₄ whose gates and drains are connected to each other are biased in the state where the power supply voltage is divided, so that they are in the weak inversion region. It becomes possible to operate with very low current consumption.

On the other hand, the bias circuit 2 has, for example, FIGS.
It is configured as shown in (d), and is designed to have low current consumption, constant current consumption, and constant voltage output. That is, the circuit of FIG. 3 (a) includes a P-channel MOS transistor T _9, T _10, which are current-mirror connected, a resistor R, and N-channel MOS transistors T _11, T ₁₂ are connected as shown . In addition, the circuit of FIG. 3 (b) has P-channel MOS transistors T ₁₃ and T ₁₄
, Resistor R, and N-channel MO connected in current mirror
The S transistors T ₁₅ and T ₁₆ are connected as shown.
The circuit shown in FIG. 3 (c) includes P-channel MOS transistors T ₁₇ and T ₁₈ connected in a current mirror, N-channel MOS transistors T ₁₉ and T ₂₀ connected in a current mirror, and a resistor R.
And are connected as shown. Further, the circuit of FIG. 3 (d) is composed of a resistor R and a P channel connected in a current mirror.
The MOS transistors T ₂₁ , T ₂₂ and the N-channel MOS transistors T ₂₃ , T ₂₄ connected in the current mirror are connected as shown.

On the other hand, the combinational circuit of the reference voltage circuits 3 ₁ , 3 ₂ , ... And the switch circuits 4 ₁ , 4 ₂ , ... Is respectively configured as shown in FIGS. 4 (a) to 4 (d), respectively. The reference voltages V _{r1 to} V _r4 can be easily set according to the magnitude of the bias voltage input, and the circuit operation can be stopped by the switch control inputs OP1 to OP4. That is, Fig. 4 (a)
Is a P-channel MOS transistor T ₂₅ whose gate and drain are connected to each other, and an N-channel for bias input.
MOS transistor T ₂₆ and N channel MO for switch input
The S-transistor T ₂₇ is connected in series, and generates the reference voltage V _r1 using the gate threshold voltage of the P-channel transistor T ₂₅ . The circuit of FIG. 4 (b) has a resistor R and an N-channel MOS transistor T ₂₈ for bias input.
And a N-channel MOS transistor T ₂₉ for switch input are connected in series, and a reference voltage V _r2 is generated by utilizing the voltage drop of the resistor R. The circuit of FIG. 4 (c) has an N-channel transistor T ₃₀ whose gate and drain are connected to each other, a resistor R, an N-channel MOS transistor T ₃₁ for bias input, and an N-channel for switch input.
The MOS transistor T ₃₂ is connected in series, and the reference voltage V _r3 is generated by utilizing the gate threshold voltage of the N-channel transistor T ₃₀ and the voltage drop of the resistor R. Also, FIG.
The circuit (d) is an NPN transistor Q whose base and collector are connected to each other, an N-channel MOS transistor T ₃₃ for bias input, and a MOS transistor T for switch input.
₃₄ and ₃₄ are connected in series, and the base-emitter voltage of the NPN transistor Q is used to generate the reference voltage V _r4 .

As the NPN transistor Q for the resistance element in the circuit of FIG. 4 (d), a bipolar transistor parasitic in the MOS process can be used, the characteristics of the MOS process due to variations are small, and the pattern area is small. It has the advantage of being small, and since it can be built in without changing the manufacturing process of the MOS LSI, it does not affect the manufacturing cost of the LSI.

Here, the circuit shown in FIG. 3 (a) is adopted as the bias circuit 2, and the reference voltage circuits 3 ₁ , 3 ₂ , ...
FIG. 4 (d) shows a combinational circuit with ₁ , 4, ₂ ...
FIG. 5 shows a part of the power supply voltage detection circuit in the case of adopting the circuit of FIG.
Further, as a combinational circuit of the reference voltage circuits 3 ₁ , 3 ₂ , ... And the switch circuits 4 ₁ , 4 ₂ , ..., The bias input transistor T ₃₃ and the switch input transistor T ₃₄ in the circuit of FIG. A plurality of series circuits of and may be connected in parallel to form a circuit as shown in FIG. In this case, the bias input transistor in each series circuit
It is necessary to make the constants of T ₃₃ different.

On the other hand, the voltage comparator 6 is realized by using a MOS transistor differential amplifier as shown in FIG. 7 (a) or (b), for example. That is, the circuit of FIG. 7 (a) includes N-channel MOS transistors T ₇₁ and T ₇₂ for differential amplification, an N-channel MOS transistor T ₇₃ for a constant current source whose bias voltage is applied to its gate, and a current mirror. It consists of connected load P-channel MOS transistors T ₇₄ and T ₇₅ . Also, the seventh
FIG circuit (b) is a differential amplification P-channel MOS transistors T _76, T ₇₇ for a P-channel MOS transistor T ₇₈ of the constant-current source bias voltage is applied to the gate, current mirror connected load N-channel MOS transistor for
It consists of T ₇₉ and T ₈₀ . In the circuits shown in FIGS. 7 (a) and 7 (b), the bias voltage from the bias circuit (FIG. 1 and FIG. 2) can be used as it is, so that low current consumption operation is possible.

Next, an alternative detection operation of the multi-valued power supply level by the power supply voltage detection circuit will be described. When the control circuit 7 selectively turns on the switch circuits 41, 42, ..., The reference voltage circuits 3 ₁ , 3 ₂ , ...
The corresponding first, second, ... Reference voltages V _r1 , V _r2 ,
.. alternatively occurs, which is selected by the control of the selection gate 5 by the control circuit 7 and becomes one input of the voltage comparator 6. In addition, the power supply voltage dividing circuit 1
Generates a divided voltage V _div under the control of the control circuit 7 and uses it as the other input of the voltage comparator. Now, when the power supply voltage V _DD changes for some reason, the magnitude relationship between the set of reference voltage and the divided output voltage selected corresponding to one power supply level to be detected in the multivalued power supply level is changed. A change occurs, the change is detected by the voltage comparator 6, and the control circuit 7 outputs a signal indicating that one power supply level to be detected is detected. Therefore, by controlling the selection of the reference voltage and the divided output voltage corresponding to the multi-valued power supply level to be detected by the control circuit 7, it becomes possible to selectively detect the multi-valued power supply level.

In the above operation, since the selection gate 5 and the control circuit 7 perform a digital circuit operation, current consumption is small. Further, the select gate 5 and the control circuit 7 can be configured by using the MOS transistor of the minimum size in the chip, and the pattern area is very small.

According to the power supply voltage detection circuit of the above embodiment, a plurality of reference voltage circuits having different circuit constants are selectively controlled in order to detect multi-valued power supply levels, and a plurality of divided output voltages from one power supply voltage division circuit. Is controlled so that it is generated selectively, and one each of a bias circuit for generating a constant voltage bias, a voltage comparator, and a control circuit is shared for multilevel detection, and thus an unnecessary redundant circuit. No need to add. Therefore, when the detection circuit is built in an LSI or the like, the pattern area on the chip can be small, and the current consumption can be constant and low. Further, by the control circuit, it is also possible to control so as to change the detection level with the sequential movement of the power supply level,
There is also an advantage that the degree of freedom in design regarding detection of multi-valued levels becomes very high.

In the above embodiment, the control signal selectively controls a plurality of reference voltage circuits and the power supply voltage dividing operation of one power supply voltage dividing circuit is controlled. A power supply voltage division circuit (one that generates different divided output voltages) is selectively controlled, and a reference voltage generation operation of one reference voltage circuit (one that alternately generates different reference voltages) is controlled. May be.

Next, as one application example of the present invention, referring to FIG. 8, a power supply voltage detection circuit used in an LSI (for example, an electronic desk calculator LSI) powered by a battery in which a generated voltage fluctuates like a solar cell is referred to. Explain. That is, 81 is a power supply voltage dividing circuit that selectively outputs a binary divided output voltage V _{div according} to a control signal, 82 is a bias circuit, 83 is a reference voltage circuit, and 86 is a voltage comparator. 88 is a buffer circuit, becomes V _DD power supply terminal and the P-channel MOS transistor T ₈₁ and the N-channel MOS transistors T ₈₂ for biasing the input between the ground terminal are connected in series, said P-channel transistor T ₈₁ The output of the voltage comparator 86 is applied to the gate of the. Reference numeral 87 denotes a control circuit, which has a two-input first NOR gate G1 to which a power-on signal is given as one input when the LSI power is on, and the output of this NOR gate G1 is given as one input and the other input. And a two-input second NOR gate G2 to which the output of the buffer circuit 88 is given, and a two-input NAND gate G3 to which the output of the first NOR gate G1 and the output of the buffer circuit 88 are also given as inputs. Inverter I1 to which the output of G3 is input
And an inverter I2 to which the output of the second NOR gate G2 is input, and the output of the second NOR gate G2 is provided as the other input of the first NOR gate G1. The output of the inverter I2 is given to the power supply voltage division circuit 81 as a division control signal DIV. Was split generates an output V _div, when the control signal DIV is high Generate a split output of V _div . _T83 is an N-channel MOS transistor for a current path connected between the V _DD power supply terminal and the ground terminal, and the output of the inverter I1 is added to the gate.

Next, the operation of the power supply voltage detection circuit of the LSI using the above solar cell as a power supply will be described with reference to FIG. A power-on signal is input to the first NOR gate G1 when the solar cell power source is in the on state. Now, for example, when the battery voltage gradually rises with sunshine, the output (auto clear signal ACL) of the second NOR gate G2 gradually rises. At this time, the reference voltage circuit 83 generates a reference voltage V _{ref which} is lower than the V _DD potential by the base-emitter voltage of the transistor Q (for example, 0.5 V). At this time, the output of the inverter I2 (division control signal DIV) is at low level, and the power supply voltage division circuit 81 To occur. Then, the voltage comparator 86 (Eg 1.0V), the output potential drops,
The output potential of the buffer circuit 88 becomes high. As a result, the output ACL of the second NOR gate G2 drops to low level, the output DIV of the inverter I2 rises, and the power supply voltage dividing circuit 81 turns off the transistor _T84. To occur. As a result, the voltage comparator 86 The output potential of the buffer circuit 88 becomes high and the output potential of the buffer circuit 88 becomes low. In this state, the illuminance of the incident light on the solar cell is further increased. When (for example, 1.5V), the output potential of the voltage comparator 86 decreases and the output potential of the buffer circuit 88 increases. At this time, since the output of the first NOR gate G1 is at high level, both inputs of the NAND gate G3 are at high level, the outputs thereof are at low level, and the output of the inverter I1 is at high level. Thus, the N-channel transistor T ₈₃ of the current path a current (hundreds μ
A to about several mA) flows and the excessive voltage generated in the solar cell is suppressed. Therefore, even if the voltage level generated by the solar cell fluctuates, a constant voltage suitable for the operation of the LSI can be supplied. As the current path transistor T ₈₃ , it is advantageous to connect a bipolar transistor in Darlington connection in terms of current driving capability, but there is a problem that the current driving capability is likely to change due to variations in the current amplification factor hfe. The MOS transistor has an advantage that the characteristics can be easily set.

As described above, according to the power supply voltage detection circuit of the present invention, the circuit configuration for detecting a multivalued power supply voltage level is simple, and the circuit pattern area when provided in a semiconductor integrated circuit is small. It is small, consumes less current, and allows highly flexible settings such as sequential detection of multi-valued levels, and is effective when applied to LSIs that use solar cells as power sources.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the power supply voltage detection circuit of the present invention, and FIGS. 2 (a) and 2 (b) are circuit diagrams showing different concrete examples of the power supply voltage dividing circuit in FIG. FIGS. 3 (a) to 3 (d) are circuit diagrams showing different specific examples of the bias circuit in FIG. 1, and FIGS. 4 (a) to 4 (d) are different from the reference voltage circuit in FIG. FIG. 5 is a circuit diagram showing a concrete example, FIG. 5 is a circuit diagram showing a concrete example by extracting the bias circuit and a plurality of reference voltage circuits in FIG. 1, and FIG. 6 is a plurality of reference voltages in FIG. 7 is a circuit diagram showing a specific example in which the circuit is replaced with one reference voltage circuit. FIGS. 7 (a) and 7 (b) are circuit diagrams showing different specific examples of the voltage comparator in FIG. FIG. 8 is a circuit diagram showing an example of a power supply voltage detection circuit in an LSI powered by a solar cell according to an application of the present invention, FIG. 9 is a voltage waveform diagram showing the operation of the circuit of FIG. 8, and FIG. a) and (b) are It is a circuit diagram showing a conventional power supply voltage detection circuit, respectively. 1, 81 ...... power supply voltage dividing circuit, 2,82 ...... bias _circuit, 3 _{1, 3} 2, ..., 83 ...... reference voltage _{circuit, 4} 1,
4 _2, ...... switch circuit, 5 ...... selection gate, 6,86
...... Voltage comparator, 7,87 ...... Control circuit.

Claims (3)

[Claims] 1. A bias circuit that generates a constant voltage bias, a reference voltage circuit that receives a bias from the bias circuit to generate a plurality of reference voltages, and a power supply voltage division circuit that generates a plurality of power supply voltage division voltages. And a voltage comparator for comparing the voltage of one divided voltage generated by the power supply voltage dividing circuit with one reference voltage generated by the reference voltage circuit, and receiving the output of the voltage comparator, the reference voltage circuit A plurality of reference voltages are controlled to be selectively output, and the power supply voltage division circuit is controlled to selectively output a power supply voltage division voltage corresponding to the reference voltage output from the reference voltage circuit. A control circuit, wherein when the power supply voltage changes and the output of the voltage comparator changes, the control circuit has a reference voltage and a power supply voltage corresponding to the changed power supply voltage. Power supply voltage detecting circuit, characterized in that it is configured to control the reference voltage circuit and the power supply voltage dividing circuit as the split voltage is output. 2. The reference voltage circuit is a plurality of reference voltage circuits capable of generating different reference voltages and selectively controlled to be operable by the control circuit. 2. The power supply voltage detection circuit according to claim 1, further comprising a selection gate that selectively selects each output of the voltage circuit by the control circuit and guides it to the voltage comparator. 3. The power supply voltage detecting circuit according to claim 1, wherein the power supply voltage dividing circuit controls the magnitude of the power supply voltage dividing voltage by the control signal.