JPS6385369A - Power source voltage detection circuit - Google Patents

Abstract

PURPOSE:To reduce not only the area of a circuit pattern but also current consumption and to detect a multivalue power source level in an alternative way, by outputting a plurality of reference voltages or a plurality of divided voltages of power source voltage in an alternative way. CONSTITUTION:When a control circuit 7 applies ON-control to switch circuits 41, 42... in an alternative way, reference voltage circuits 31, 32... goes into an operation state in an alternative way the corresponding reference voltages are generated in an alternative way to be inputted to a voltage comparator 6 through a selection gate 5. A power source voltage dividing circuit 1 generates divided voltage Vdiv according to control by the control circuit 7 to input the same to the voltage comparator 6. When power source voltage VDD changes by any cause, the magnitude relation of one selected set of reference voltages and divided output voltages changes and this change is detected by the voltage comparator 6 to be outputted from the control circuit 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention (Field of Industrial Application) The present invention relates to a power supply voltage detection circuit used in a semiconductor integrated circuit, and particularly to a power supply voltage detection circuit that selectively detects multiple levels of power supply voltage. This invention relates to a multi-rail detection circuit.

(Prior art) A conventional power supply voltage detection circuit is shown in FIG. 10(a) or (
As shown in b), two intermediate level voltages VA and V have different gradual transition tendencies with respect to the power supply voltage vDD.

The voltage comparator CP compares both voltages VA and V to detect the vDD voltage level at which the two voltages vA and VB are equal. In this case, the above voltage VAs
One side of VB, vA, is used as a quasi voltage; The series circuit with the power supply voltage dividing resistor R1+R
It is generated using 2.

By the way, what about the above circuit? When &e is installed in an LSI (Large Scale Integrated Circuit), the circuit constants are fixed, so only the o'i pressure can be detected at one set point. Therefore, if one tries to detect a long chain power supply rail using the conventional power supply voltage detection circuit described above.

It is necessary to prepare a plurality of sets of power supply voltage detection circuits having different circuit constants, but this causes problems such as an increase in the pattern area occupied on the chip and an increase in current consumption.

(Problems to be Solved by the Invention) The present invention solves the problem that if multiple sets of the above-described conventional power supply voltage detection circuits are provided in an integrated circuit to detect multiple levels of the power supply voltage, the pattern area becomes large. This was developed to solve the problem that the current consumption increases as the power supply threshold increases. It is an object of the present invention to provide a power supply voltage detection circuit that is small and has low current consumption.

[Configuration of the Invention (Ninth Means for Solving Problems) The power supply voltage detection circuit of the present invention includes a constant voltage bias circuit, a reference voltage circuit, a power supply voltage dividing circuit, and a voltage comparator in the same semiconductor substrate. , further comprising a control circuit that controls at least one of the reference voltage circuit and the power supply voltage dividing circuit to selectively output a plurality of reference voltages or to selectively control a plurality of divided voltages. do.

(Function) The reference voltage circuit and the power supply voltage dividing circuit can be controlled to output a required voltage by the control signal, and a long chain power supply level can be detected alternatively. Therefore, there is no need to prepare multiple sets of power supply voltage detection circuits, and it is sufficient to prepare several reference voltage circuits with different constants or power supply dividing circuits, so the circuit pattern area is small. The current consumption is also low.

(Embodiment) Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a power supply voltage detection circuit provided in an LSI for detecting the power supply level of a nine-long chain.

That is, reference numeral 1 denotes a power supply voltage dividing circuit which selects and outputs one of the divided voltages obtained by dividing the power supply voltage VDDt from among a plurality of divided voltages in accordance with a control signal input. 2 is a bias circuit that outputs a constant rail bias voltage that does not directly depend on the power supply voltage vDD. 3! .

31. . . . are reference voltage circuits that perform constant current operation in response to the above bias voltage and generate mutually different reference voltages, and the corresponding switch circuits 41*
The operation and non-operation states are controlled by 41w. Reference numeral 5 denotes a selection node' for selectively deriving each output voltage (a plurality of reference voltage outputs) of the reference voltage circuits 31°3□, . . . in accordance with a control signal input. A voltage comparator 6 compares the selected output voltage of the selection r-t 5 with the divided output voltage of the power supply voltage dividing circuit 1. 7 are the switch circuits 41.4.7 corresponding to the long chain power supply voltage levels to be detected, respectively. , . . . , and also supplies a control signal for extracting a predetermined divided output voltage to the power supply voltage dividing circuit 1 and a control signal for controlling the selection operation of the selection gate 5. A control circuit is used to correlate the output of the voltage comparator 6 with the long-chain power supply voltage level to be detected and send it out as a detection output.

Note that the power supply voltage dividing circuit 1 is illustrated in FIG. 2 (&
) 6 or (b).

That is, the circuit of FIG. 2(a) connects the vDD power supply terminal and the v811
A plurality of (in this example, 41) N-channel MO8) transistors T1 to T4 are connected in series, with their r-) and drains connected to the power supply terminal (ground terminal), respectively, and the transistors An N-channel MO resistor Ts controlled by the switch control signal S1 is connected between the interconnection point of T3tT4 and the ground terminal,
An N-channel MOS transistor T6, which is switch-controlled by a switch control signal S2, is connected between the interconnection point of the transistors 'r, , and 'r3 and the ground terminal. A divided output voltage is taken out. in this case,
When the transistor T6 is turned on and both transistors T5 and T6 are turned off, the divided output voltage becomes 4vDD.

9. In the circuit of Fig. 2(b), four N-channel MOS transistors TI-T4 are connected between the DD power supply terminal and the ground terminal, similar to the circuit of Fig. 2(a) above. However, between the interconnection point of transistors T1, T, and the vDD power supply terminal, and between the interconnection point of transistors T, , T3 and vDDW! , P for switch control between the progenitor and the progenitor.
Channel MO8) U/Jister T7.

Ts is connected so that a divided output voltage is taken out from the interconnection point of transistors T3eT4. Therefore, when the transistor T8 is turned on, the divided output voltage becomes 2vDD, and when the transistor T7 is turned on, the divided output voltage becomes τvDD when both the divided output voltages are turned off.

In addition, in the circuit of FIG. 2(a) #(b) above,
Transistor T1 with dirt and drain connected to each other
T4IIi is biased with the power supply voltage divided, so it operates in the weak inversion region.

It is possible to operate with very low current consumption.

On the other hand, the above-mentioned earth circuit 2 is, for example, as shown in FIG.
The configuration is as shown in (d), and low current consumption, constant current consumption, and constant voltage output are achieved. That is, the circuit of FIG. 3(1) has a current mirror connected 7'cP channel MO8) transistor "9 #T10, a resistor R,
N-channel MOS transistors "11 #"12 are connected as shown. In addition, the circuit of FIG. 3(b) has a P-channel MO8) transistor "13 I T14", a resistor R, and a current mirror connected to each other.
MOS transistors T15 #T16 are connected as shown. Further, in the circuit of FIG. 3(c), current mirror-connected P-channel MO8) transistors T, T, current mirror-connected NT Janel MOS transistors T19*'20, and resistor R are connected as shown in the figure. In addition, the circuit of FIG. 3(d) includes a resistor R, a current mirror connected fcP channel MOS transistor "21*T22," and a current mirror connected N channel MOS transistor T.
, T are connected as shown.

On the other hand, the combination circuits of the reference voltage circuits J1*J2e... and the switch circuits 41*42*... are each configured as shown in FIGS. 4(a) to (d), and both have a bias The reference voltages vr, ~V, can be easily set depending on the magnitude of the voltage input, and the circuit operation can be stopped using the switch control inputs OPZ-OP4. That is, the circuit of FIG. 4(a) consists of a P-channel MO8) transistor T whose y-t and drain are connected to each other.
25, an N-channel MOS transistor T26 for bias input, and an N-channel MOS transistor T27 for switch input are connected in series. Voltages vr and t are generated.The circuit in Figure 4(b) consists of a resistor R and an N-channel MOS for bias input.
Transistor T28 and N-channel MO for switch input
An S transistor T29 is connected in series, and a reference voltage vr2t- is generated using the voltage drop across the resistor R.

Next, the circuit of FIG. 4(e) includes an N-channel transistor T30 whose dirt drains are connected to each other, a resistor R, and an N-channel MOS transistor TS for bias input.
1 and an N-channel MOS transistor T3□ for switch input are connected in series, and a reference voltage vr5 is generated using the r-threshold voltage of the N-channel transistor Tsa and the voltage drop across the resistor R. do. 9. The circuit in Figure 4(d) consists of an NPN transistor Q whose base and collector are connected to each other, and an N-channel MOS for ground input.
) Transistor T33 and MOS for manual switch)
The transistor "34" is connected in series with J, NPN.
A reference voltage vr4 is generated using the pace-emitter voltage of the transistor Q.

Note that N for the resistor element in the circuit shown in FIG. 4(d) above is
The PN type transistor Q can use a bipolar transistor parasitic to the MOS process, has the advantage that characteristics are less affected by variations in the MOS process, and has a small pattern area.
Since it can be built in without changing the manufacturing process,
Does not affect the manufacturing cost of SI.

Here, the circuit shown in FIG. 3 (JL) is adopted as the bias circuit 2, and the circuit shown in FIG. 4 (d) is used as a combination circuit of the reference voltage circuit 31e32m... FIG. 5 shows a part of the power supply voltage detection circuit in the case where circuits having different circuit constants are used. Also, the reference voltage circuit 3! ,
3 meaning... and switch circuit 41eJ! As a combination circuit with e..., a series circuit of the bias input transistor Tss and the switch input transistor T54 in the circuit of FIG. 4(d) is connected in parallel, and a sixth
The circuit may be configured as shown in the figure; in this case, it is necessary to make the constants of the bias input transistors Tss in each series circuit different.

On the other hand, the voltage comparator 6 is realized using, for example, a KMO8) transistor differential amplifier as shown in FIG. 7(a) or (b). That is, the circuit of FIG. 7(a) is
N-channel MOS transistor T71 for differential amplification #
T7□, an N-channel MO8) Lanzostar T73 for a constant current source where a bias voltage is applied to the dart, and a P-channel MO8) Lanzostar T7, T2 for a current mirror-connected load. The circuit of FIG. 7(b) also includes a P-channel MOS transistor T for differential amplification.
74 # T77 and P-channel MO8 for constant current source where bias voltage is applied to dart) Lanzostar T78 and N-channel MO8 for current mirror connected load
) consists of transistors T79 e T2O. In the circuit shown in FIGS. 7(a)*(b), the bias voltage from the bias circuit (FIG. 1, FIG. 2) can be used as is, so low current consumption operation is possible.

Next, an explanation will be given of the operation of alternatively detecting multi-value power supply levels by the power supply voltage voltage detection circuit. The control circuit 7 includes switch circuits 41, 42 . When . The reference voltages V , V , . . . are alternatively generated r1
r2 Is this a choice? -) 5 is selected under the control of the control circuit 7 and becomes one input of the voltage comparator 6. Further, the power supply voltage dividing circuit 1 generates a divided voltage vd1v under the control of the control circuit 7 and uses it as the other input of the voltage comparator. Now, when the power supply voltage vDD changes for some reason, the magnitude relationship between a set of reference voltages and divided output voltages selected corresponding to one power supply level to be detected among the multi-value power supply levels. A situation occurs in which the voltage changes, this change is detected by the voltage comparator 6, and the control circuit 7 outputs a signal indicating that the one power supply level to be detected has been detected.

Therefore, by selectively controlling the reference voltage and divided output voltage corresponding to the multi-value power supply levels to be detected by the control circuit 2, it becomes possible to alternatively detect the multi-value power supply levels.

Note that in the above operation, the selection gate 5 and the control circuit 7 perform digital circuit operations, so current consumption is small. Further, the selection dart 5 and the control circuit 7 can be constructed using a MOS (MOS) transistor with the smallest size on a chip, and the pattern area is extremely small.

According to the power supply voltage detection circuit of the above embodiment, in order to detect multi-value power supply levels, a plurality of reference voltage circuits having different circuit constants are selected and controlled, and a plurality of divided output voltages are output from one power supply voltage dividing circuit. Since the bias circuit for constant voltage bias generation, the voltage comparator, and the control circuit are shared for multilevel detection, unnecessary redundancy is eliminated. No need to add any circuit. Therefore, when the above detection circuit is built into an LSI etc.,
The A-turn area on the chip can be small, and the current consumption can be constant and low. Furthermore, the control circuit described above also allows the detection level to be controlled to change in accordance with the sequential movement of the power supply level, which has the advantage of greatly increasing the degree of freedom in design regarding multi-value level detection. stone.

In the above embodiment, the control signal selectively controls the plurality of reference voltage circuits and controls the power supply voltage dividing operation of one power supply voltage dividing circuit. The power supply voltage dividing circuit (which generates different divided output voltages) is selectively controlled, and the reference voltage generation operation of one reference voltage circuit (which selectively generates different reference voltages) is controlled. You can.

Next, as an application example of the present invention, FIG. 8 shows a power supply voltage detection circuit used in an LSI (for example, an LSI for an electronic desktop calculator) whose power source is a battery whose generated voltage fluctuates, such as a solar cell. I will explain. That is, 81 is a power supply voltage dividing circuit that selectively outputs a divided output voltage vdi7 of just 2 in accordance with a control signal, 82 is a bias circuit, and 82 is a bias circuit.
3 is a reference voltage circuit, and lr6 is a voltage comparator. 88 is a buffer circuit, which connects P between the vDD power supply terminal and the ground terminal.
The channel MO8) Lanzo star T81 and the N-channel MO8) transistor T8□ for bias input are connected in series, and the P-channel transistor T8. The output of the voltage comparator 86 is applied to the gate of the voltage comparator 86.

87 is a control circuit, to which the power-on signal is given as one input when the LSI power is on, and the output of the two-man powered first NOA p-)GZ is given as one input. and a two-man powered NAND G2 to which the output of the buffer circuit 88 is given as the other input; r-) GJ, an inverter 1 to which the output of this NAND y-to G3 is input, and an ink-1 to which the output of the second node f-) G2 is input.
The output of the second NOR gate G2 is provided as the other input of the first NOR gate G1.

The output of the inverter I2 is the power supply voltage dividing circuit 81.
This power supply voltage dividing circuit 81 generates a divided output vd1v of TvDD when the control signal DIV is at a low level, and the control signal D
When IV is at no level, KTvDD divided output vd
Generate iv. Ta2 is an N-channel MO8) transistor for a current path connected between the vDD power supply end and the ground end, and the output of the inverter 1 is added to the dirt.

Next, the operation of the power supply voltage detection circuit of an LSI using the solar cell as a power source will be explained with reference to FIG.

When the solar battery power source is on, an arm-warning signal is input to the first Noah f-)GJ. Now, for example, when the battery voltage gradually rises with sunlight, the output (auto clear signal ACL) of the second Noah f-)G2 gradually rises. At this time, the reference voltage circuit 83 generates a reference voltage vrlIlf that is lower than the voltage level between vDD' and the emitter voltage of the transistor Q (for example, by 0.5 V). Also, at this time, the output of the inverter 2 (division control signal DIV) is at a low level, and when the voltage comparator 86 becomes vr@lf>TvI)D (tatoeba 1.OV), its output potential decreases and the buffer The output potential of circuit 88 becomes high. This allows the second Noah r-)G2
The output ACL of the inverter 2 falls to a low level, and the output DIV of the inverter 2 is not high.
If DD is not present, its output 'α' becomes high, and the output potential of the buffer circuit 88 becomes low. In this state, the illuminance of the incident light on the solar cell further increases to V. f) a
When Von (fc for example 1.5 V) becomes ゛1
The output level of the pressure comparator 86 decreases, and the buffer circuit 8
The output of 8 becomes higher. At this time, the first noader)
Since the output of GJ is at a high level, both GJs (nandodar) are at a high level, their outputs are not at a low level, and the output of inverter fz is at a high level. This allows the N-channel transistor for the current path to 8. A current (from several hundred μA to several mA) flows through the solar cell, suppressing the excessive voltage generated in the solar cell. therefore,
Even if the voltage level generated by solar cells fluctuates, the LSI
A constant pressure suitable for the operation is supplied. In addition, as for the current path transistor T8M, it is advantageous to connect a pie I-Ra transistor in Darlington connection in terms of current drive capability, but the above current and drive capability are likely to change due to variations in current amplification 1"fe. However, MOS) Lanzostar has the advantage that it is easier to set the characteristics.

[Effects of the Invention] As described above, according to the power supply voltage detection circuit of the present invention, the circuit configuration for detecting multi-value power supply voltage levels is simple, and the circuit pattern area when provided in a semiconductor integrated circuit is reduced. It is small, requires low current consumption, and can be set with a high degree of freedom, such as sequentially detecting multilevel levels, and is effective when applied to LSIs that use solar cells as a power source.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a simple embodiment of the power supply voltage detection circuit of the present invention, and FIGS. 2(a) and (b) are circuit diagrams showing different specific examples of the power supply voltage dividing circuit in FIG. Figure 3 (
, ) to (d) are circuit diagrams showing different specific examples of the bias circuit in FIG. 1, and FIG. Circuit diagram shown, 5th
The figure is a circuit diagram showing a specific example of the bias circuit and a plurality of reference voltage circuits in FIG. 1, and FIG. A circuit diagram showing a specific example of replacing the entire At pressure circuit with a reference voltage circuit, FIG. 7(a),
(b) is a circuit diagram showing a different specific example of the voltage comparator in FIG. 1, and FIG. 8 is a circuit diagram showing an example of a power supply voltage detection circuit in an LSI using a solar cell as a power source according to an application example of the present invention. 9 are voltage waveform diagrams showing the operation of the circuit of FIG. 8, and FIGS. 10(a) and 10(b) are circuit diagrams showing conventional power supply voltage detection circuits, respectively. 1.8I...power supply voltage divider circuit, 2,82...bias circuit, 3! , 3. ,...,83...Reference voltage circuit, 41.4. , . . . switch circuit, 5 . . . selection dart, 6.86 . . . voltage comparator, 7, 87 . . . control circuit.

Claims (3)

[Claims] (1) A bias circuit that is provided in a semiconductor integrated circuit and generates a constant voltage bias, a reference voltage circuit that can generate multiple reference voltages by applying bias from this bias circuit, and multiple power supply voltage division voltages. a voltage comparator that compares one divided voltage generated from the power supply voltage divider circuit with one reference voltage generated from the reference voltage circuit; and the reference voltage circuit and the power supply. 1. A power supply voltage detection circuit comprising: a control circuit that controls at least one of the voltage dividing circuits to selectively output a plurality of reference voltages or to selectively output a plurality of divided voltages. (2) The reference voltage circuit is a plurality of reference voltage circuits that are capable of generating different reference voltages and are selectively controlled to be operable by the control circuit, and the plurality of reference voltage circuits are 2. The power supply voltage detection circuit according to claim 1, further comprising a selection gate for selectively selecting each output by said control circuit and guiding the selected output to said voltage comparator. (3) The power supply voltage detection circuit according to claim 1 or 2, wherein in the power supply voltage dividing circuit, the magnitude of the power supply voltage divided voltage is controlled by the control signal.