JP4183957B2 - Mute circuit and reference voltage generation circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a reference voltage generation circuit and a mute circuit using the same, and more particularly to a reference voltage generation circuit for generating a reference voltage and controlling the generated reference voltage, and an analog amplification of the reference voltage generated by the reference voltage generation circuit The present invention relates to a mute circuit that is applied to an analog common voltage terminal of a circuit and controls a generated reference voltage to mute an output signal of the analog amplifier circuit.
[0002]
[Prior art]
In general, in an analog amplifier circuit as shown in FIG. 4, when the analog amplifier circuit is powered up, the output VOUT of the analog amplifier circuit is changed from a high impedance unstable state to a stable state in which a signal is output. For this reason, a current flows instantaneously to the output load. When the output load is a headphone or the like, a noise (or pop noise) is generated, which is inconvenient for hearing. The same is true when the analog amplifier circuit is powered down, and the output VOUT of the analog amplifier circuit changes from a stable state in which a signal is output to an unstable state of high impedance, and a noise is generated. Therefore, when the analog amplifier circuit is powered up or down, it is necessary to mute the output signal of the analog amplifier circuit so that pop noise does not occur.
[0003]
As a method for muting the output of the analog amplifier circuit so as not to generate a clicking sound, there are methods as shown in FIGS. During the mute, the analog common voltage VC of the analog amplifier circuit is set to 0V and the output VOUT of the analog amplifier circuit is set to 0V. During the mute, the analog amplifier circuit is powered up or powered down. As shown in FIG. 5, when the analog amplifier circuit is powered up, the power down signal is changed from H to L to cancel the power down, and then the mute signal is changed from H to L to cancel the mute. As shown in FIG. 6, when the analog amplifier circuit is powered down, the mute signal is muted from L to H, and then the power down signal is switched from L to H to power down. Therefore, since the output VOUT is always 0 V during mute, no squeal is generated when the power-down signal changes.
[0004]
However, as shown in FIGS. 5 and 6, if the analog common voltage VC changes suddenly from 0 V to the constant voltage VA (or from VA to 0 V) when the mute signal is changed, a noise is also generated here.
[0005]
As shown in FIG. 5, at the rise of the analog common voltage VC, the analog common voltage VC changes from 0V to VA, and the output VOUT also changes from 0V to VA. If the time at which the analog common voltage VC changes from 0 V to VA is t11 and t12, respectively, a gulp sound is generated at times t11 and t12. As the slope VA / (t12-t11) of the analog common voltage VC at the time t11 is larger, a loud noise occurs at the output VOUT. Similarly, at time t12, as the slope of the analog common voltage VC is larger, a loud noise is generated.
[0006]
As shown in FIG. 6, when the analog common voltage VC falls, the analog common voltage VC changes from VA to 0V, and the output VOUT also changes from VA to 0V. If the times at which the analog common voltage VC changes from VA to 0 V are t21 and t22, respectively, a bonfire is generated at times t21 and t22. As the slope VA / (t22-t21) of the analog common voltage VC at time t21 is larger, a loud noise is generated at the output VOUT. Similarly, at time t22, as the slope of the analog common voltage VC is larger, a loud noise is generated. Therefore, the analog common voltage VC needs to be gradually changed from 0 V to VA (or from VA to 0 V) in order to prevent the generation of a clicking sound at the output VOUT when the mute signal is changed.
[0007]
A conventional circuit (mute circuit) for muting an output signal by changing the analog common voltage VC of the analog amplifier circuit includes a circuit as shown in FIG. In FIG. 7, the mute circuit includes an analog amplifier circuit and a reference voltage generation circuit. The analog common terminal of the analog amplifier circuit is connected to the voltage generation terminal of the reference voltage generation circuit. The voltage generation terminal is connected to a voltage source that generates a constant voltage VS via a resistor R21 and a switch SW21, and the voltage generation terminal is grounded via a resistor R22 and a switch SW22. Further, the voltage generation terminal is grounded via the capacitor C2.
[0008]
When the analog common voltage VC rises, the switch SW21 is turned on and the switch SW22 is turned off from the state where the switch SW21 is turned off and the switch SW22 is turned on.
[0009]
FIG. 8 is a timing chart showing states of the analog common voltage VC and the analog output VOUT at the time of rising in the mute circuit of FIG. As shown in FIG. 8, the analog common voltage VC is expressed by the following formula: VC = VS × {1−e− ^{t / (R21 × c2)} }, and the analog common voltage VC rises from 0V and finally reaches VS. The time (settling time) that is settled and reaches 95% of the steady state (the state where the analog common voltage VC is VS) can be arbitrarily determined by the capacitor C2 and the resistor R21. The settling time at this time is 3 × C2 × R21. Since the noise converges gently to the steady value VS, the above-mentioned noise generated at time t12 is small in this circuit configuration.
[0010]
When the analog common voltage VC falls, the switch SW21 is turned on and the switch SW22 is turned off, so that the switch SW21 is turned off and the switch SW22 is turned on.
[0011]
FIG. 9 is a timing chart showing the states of the analog common voltage VC and the analog output VOUT at the time of falling in the mute circuit of FIG. As shown in FIG. 9, the analog common voltage VC drops from VS and is finally settled to 0V, and the time (settling time) to reach 95% of the steady state (the state where the analog common voltage VC is 0V) is the capacitor C2. And resistance R22 can be arbitrarily determined. The settling time at this time is 3 × C2 × R22. Since the noise converges gently to the steady value of 0 V, the above-mentioned noise generated at time t22 is small in this circuit configuration.
[0012]
Further, in FIG. 8, the slope of the analog common voltage VC at time t1 at the time of rising is determined by the capacitor C2 and the resistor R21, and becomes VS / (C2 × R21). Similarly, in FIG. 9, the slope of the analog common voltage VC at time t2 at the time of falling is VS / (C2 × R22). For example, the capacitance value and the resistance value that can be normally used are on the order of VS = 1V, C2 = 1 μF, and R21 = R22 = 100 kΩ, respectively. At this time, the slope of the analog common voltage VC (output VOUT) at the time t1 at the time of rising (or the time t2 at the time of falling) is about 10 V / s.
[0013]
[Problems to be solved by the invention]
However, since the analog common voltage VC needs to rise or fall completely within the time required by the application used, the resistance and cap values are thereby determined. Therefore, the slope at the time of rising or falling of the analog common voltage VC is determined by the values of the resistor and the capacitor, and cannot be made more gentle.
[0014]
In addition, the analog common voltage VC is allowed to rise or fall completely within a predetermined time, and in order to make the slope of the analog common voltage VC rising or falling gentle, Even if the value is increased as much as possible, there is a problem that the circuit scale increases.
[0015]
Accordingly, an object of the present invention is to further reduce the slope of the analog common voltage VC at the time of rising or falling without changing the values of the resistor and the capacitor, without affecting the settling time, and It is an object to provide a mute circuit and a reference voltage generation circuit that can reduce the generation of a clapping sound at an output VOUT of a circuit.
[0016]
[Means for Solving the Problems]
In the invention of claim 1 in order to achieve the above object, it generates a predetermined reference voltage, having a base reference voltage generating circuit you output from voltage generating terminal a reference voltage the generated, said voltage generating terminal A mute for connecting the operational reference voltage terminal of the operational amplifier to apply the generated reference voltage to the operational reference voltage terminal, and controlling the potential of the operational reference voltage terminal to the ground level to mute the output signal of the operational amplifier a circuit, the reference voltage generating circuit, a voltage source is, P-type MOS transistor and the first to the drain source gate is grounded and the input terminal of the voltage source side and an output terminal of said voltage generating terminal side is connected through the switch and the first resistor to the voltage generating terminal, the voltage generating terminal grounded via the capacitor, the voltage generation terminal, source gate is connected to said voltage source Scan a is grounded via an N-type MOS transistor the drain and the input terminal on the ground side to the output terminal of said voltage generating terminal side and the second switch and a second resistor, during muting, the first The switch is turned off and the second switch is turned on to bring the potential of the operation reference voltage terminal to the ground level. During non-mute operation, the first switch is turned on and the second switch is turned off. the potential before Symbol operation reference voltage terminal by a was performed muting circuit according to the reference voltage.
[0017]
According to a second aspect of the present invention, there is provided a reference voltage generation circuit that generates a predetermined reference voltage and outputs the generated reference voltage from a voltage generation terminal, and the voltage generation terminal is connected to an operation reference voltage terminal of an operational amplifier. A mute circuit that applies the generated reference voltage to the operation reference voltage terminal and controls the potential of the operation reference voltage terminal to a ground level to mute the output signal of the operational amplifier, the reference voltage generation circuit the voltage source is, the gate is the ground through the P-type MOS transistor and the first switch and the first resistor to the output terminal of the drain to the source and the input terminal of the voltage source side said voltage generating terminal side Connected to the voltage generating terminal, the voltage generating terminal is grounded via a capacitor, the voltage generating terminal is grounded via a second switch and a second resistor, and a mute operation is performed. The first switch is turned off and the second switch is turned on to set the potential of the operation reference voltage terminal to the ground level. During a non-mute operation, the first switch is turned on, the potential before Symbol operation reference voltage terminal by turning off the second switch was performed muting circuit according to the reference voltage.
[0018]
According to a third aspect of the present invention, there is provided a reference voltage generating circuit that generates a predetermined reference voltage and outputs the generated reference voltage from a voltage generation terminal, and the voltage generation terminal is connected to an operation reference voltage terminal of an operational amplifier. A mute circuit that applies the generated reference voltage to the operation reference voltage terminal and controls the potential of the operation reference voltage terminal to a ground level to mute the output signal of the operational amplifier, the reference voltage generation circuit is the voltage source is connected to the first switch and said voltage generating terminal via the first resistor, the voltage generating terminal grounded via the capacitor, the voltage generating terminal, and a gate wherein the voltage source the connected source is grounded via an N-type MOS transistor the drain and the input terminal on the ground side to the output terminal of said voltage generating terminal side and the second switch and a second resistor, Myu During the operation, the first switch is turned off and the second switch is turned on to set the potential of the operation reference voltage terminal to the ground level. During the non-mute operation, the first switch is turned on. to, and the potential before Symbol operation reference voltage terminal by turning off the second switch implemented muting circuit according to the reference voltage.
[0021]
In the invention of claim 4, generates a predetermined reference voltage, the reference voltage the generated a reference voltage generating circuit for outputting the voltage generating terminal, a voltage source is the voltage source side source gate is grounded Are connected to the voltage generation terminal via a P-type MOS transistor having a drain as an output terminal on the voltage generation terminal side, a first switch, and a first resistor, and the voltage generation terminal is connected via a capacitor. The N-type MOS transistor, the second switch, and the second switch are grounded, the voltage generation terminal is connected to the voltage source, the gate is connected to the voltage source, the source is the input terminal on the ground side, and the drain is the output terminal on the voltage generation terminal side . The first switch is turned off, and the second switch is turned on to bring the potential of the voltage generation terminal to the ground level, and the first switch Turn on, and the potential of the voltage generating terminal by turning off the second switch performing a reference voltage generating circuit according to the reference voltage.
[0022]
In the invention of claim 5, generates a predetermined reference voltage, the reference voltage the generated a reference voltage generating circuit for outputting the voltage generating terminal, a voltage source is the voltage source side source gate is grounded Are connected to the voltage generation terminal via a P-type MOS transistor having a drain as an output terminal on the voltage generation terminal side, a first switch, and a first resistor, and the voltage generation terminal is connected via a capacitor. The voltage generation terminal is grounded via a second switch and a second resistor, the first switch is turned off, and the second switch is turned on to turn on the potential of the voltage generation terminal. Is set to the ground level, the first switch is turned on, and the second switch is turned off to implement the reference voltage generation circuit in which the potential of the voltage generation terminal is the reference voltage.
[0023]
In the invention of claim 6, generates a predetermined reference voltage, a reference voltage the generated reference voltage generating circuit for outputting the voltage generating terminal, the voltage source, a first switch and a first resistor and connected to said voltage generating terminal via the voltage generating terminal grounded via the capacitor, the voltage generating terminal, and a gate input terminal and to the drain of said voltage generation terminal of the ground source connected to said voltage source The voltage is generated by turning off the first switch and turning on the second switch, which is grounded via an N-type MOS transistor serving as an output terminal on the side, a second switch, and a second resistor. Implementation of a reference voltage generation circuit in which the potential of the voltage generation terminal is set to the reference voltage by setting the terminal potential to the ground level, turning on the first switch, and turning off the second switch. It was.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit diagram showing a mute circuit of the present invention and a reference voltage generating circuit of the present invention. The mute circuit includes an analog amplifier circuit and a reference voltage generation circuit. The analog common terminal of the analog amplifier circuit is connected to the voltage generation terminal of the reference voltage generation circuit. The voltage generation terminal is connected in series to a voltage source that generates a constant voltage VS via a P-type MOS transistor M1, a resistor R11, and a switch SW11. The order of connection may be any case, but the preferred order is the order of the voltage generation terminal, the P-type MOS transistor M1, the resistor R11, the switch SW11, and the voltage source that generates the constant voltage VS.
[0027]
The voltage generation terminal is grounded via an N-type MOS transistor M2, a resistor R12, and a switch SW12. The order of connection may be any case, but the preferred order is the order of voltage generation terminal, N-type MOS transistor M2, resistor R12, switch SW12, and ground terminal. The gate of the P-type MOS transistor M1 is grounded, and the gate of the N-type transistor M2 is connected to a voltage source that generates the voltage VS. Further, the voltage generation terminal is grounded via the capacitor C1.
[0028]
FIG. 2 is a circuit diagram schematically showing the mute circuit of the present invention at the time of rising of the analog common voltage VC. The switch SW11 shown in FIG. 1 is on and the switch SW12 is off. The analog common terminal is connected to a voltage source that generates a voltage VS via a P-type MOS transistor M1 and a resistor R11, and the gate of the P-type MOS transistor M1 is grounded. Further, the analog common terminal is grounded via the capacitor C1.
[0029]
FIG. 3 is a circuit diagram schematically showing a mute circuit according to the present invention when the analog common voltage VC falls. The switch SW11 shown in FIG. 1 is off and the switch SW12 is on. The analog common terminal is grounded via an N-type MOS transistor M2 and a resistor R12, and the gate of the N-type MOS transistor M2 is connected to a voltage source that generates a voltage VS. Further, the analog common terminal is grounded via the capacitor C1.
[0030]
Next, operations of the mute circuit and the reference voltage generation circuit in the embodiment of the present invention will be described.
[0031]
In FIG. 2, when the analog common voltage VC rises, the switch SW11 is turned off and the switch SW12 is turned on, so that the switch SW11 is turned on and the switch SW12 is turned off. The initial value of the common voltage VC is 0V. At this time, since the gate voltage and the drain voltage of the P-type MOS transistor M1 are equal, the P-type MOS transistor M1 operates in a saturation region, operates as a constant current source, and a current I11 flows.
[0032]
Therefore, the slope of the analog common voltage VC at the rising time Δt is ΔV / Δt = (ΔQ / C1) × (1 / Δt) = (ΔQ / Δt) × (1 / C1) = I11 / C1. Here, ΔV is a voltage change amount of the analog common voltage VC at time Δt, and ΔQ is a charge change amount of the capacitor C1 at time Δt.
[0033]
For example, capacitance values and current values that can be normally used are in the order of C1 = 1 μF, I11 = 3.3 μA, VS = 1V, P-type MOS transistor M1 has W = 20 μm, L = 5 μm, and N-type MOS The transistor M1 has W = 20 μm and L = 20 μm. At this time, the slope of the analog common voltage VC (output VOUT) at the time of rising is about 3.3 V / s. This value is a level that cannot be heard as a squeal at the output VOUT, and is in a good audible state.
[0034]
Next, when the analog common voltage VC further rises from 0 V, the drain voltage of the P-type MOS transistor M1 also rises, the P-type MOS transistor M1 enters the linear operation region, and the resistance component of the P-type MOS transistor M1 is the resistance R11. Compared with (usually several tens of kΩ to several hundreds kΩ), it becomes a very small value (usually several hundreds of Ω to several kΩ).
[0035]
Therefore, the analog common voltage VC rises gently in the same manner as in FIG. 8 and is finally settled to VS, but it takes 95% of the steady state (the state where the analog common voltage VC is VS) (settling time). Is 3 × C1 × R11 and can be determined by the capacitor C1 and the resistor R11 without being affected by the P-type MOS transistor M1.
[0036]
In FIG. 3, when the analog common voltage VC falls, the switch SW11 is turned on and the switch SW12 is turned off, so that the switch SW11 is turned off and the switch SW12 is turned on. The initial value of the analog common voltage VC at VS is VS. At this time, since the gate voltage and the drain voltage of the N-type MOS transistor M2 are equal, the N-type MOS transistor M2 operates in a saturation region, operates as a constant current source, and a current I12 flows.
[0037]
Therefore, the slope of the analog common voltage VC at the rising time Δt is I12 / C1, which is about 3.3 V / s. This value is much smaller than that in the case where no N-type MOS transistor is inserted, so that the noise at the output VOUT can be further reduced, and a favorable audibility can be obtained.
[0038]
Next, when the analog common voltage VC decreases from VS, the drain voltage of the N-type MOS transistor M2 also decreases, the N-type MOS transistor M2 enters the linear operation region, and the resistance component of the N-type MOS transistor M2 is a resistor R12 normal. Is a very small value (usually several hundred Ω to several kΩ) that is negligible compared to tens of kΩ to several hundred kΩ.
[0039]
Therefore, the analog common voltage VC gradually falls in the same manner as in FIG. 9 and is finally settled to 0V, but it takes 95% of the steady state (the analog common voltage VC is 0V) (settling time). Is 3 × Cl × R12 and can be determined by the capacitor C1 and the resistor R12 without being affected by the N-type MOS transistor.
[0040]
【The invention's effect】
As described above, the reference voltage generating circuit according to the present invention can be configured with a small-scale circuit in which a MOS transistor is inserted into a conventional circuit. The MOS transistor has an effect that the slope at the rise or fall of the output voltage of the reference voltage generation circuit can be further moderated without affecting the settling time determined by the resistor and the capacitor.
[0041]
The mute circuit according to the present invention can be constituted by a small-scale circuit in which a MOS transistor is inserted into a conventional circuit. Since the MOS transistor can further reduce the slope of the analog common voltage VC at the time of rising or falling without affecting the settling time determined by the resistor and the capacitor, the audible noise at the output VOUT of the analog amplifier circuit This has the effect of reducing the occurrence of
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a mute circuit of the present invention and a reference voltage generation circuit of the present invention.
FIG. 2 is a circuit diagram schematically showing a mute circuit of the present invention at the time of rising of an analog common voltage.
FIG. 3 is a circuit diagram schematically showing a mute circuit of the present invention at the fall of an analog common voltage.
FIG. 4 is a circuit diagram showing an analog amplifier circuit.
FIG. 5 is a timing chart showing a state at the time of rising of an analog common voltage and an analog output.
FIG. 6 is a timing chart showing a state when the analog common voltage and the analog output fall.
FIG. 7 is a circuit diagram showing an example of a conventional mute circuit and a conventional reference voltage generation circuit.
FIG. 8 is a timing chart showing a state of an analog common voltage and an analog output at the time of rising in a conventional mute circuit.
FIG. 9 is a timing chart showing an analog common voltage and an analog output state at the time of falling in a conventional mute circuit.
[Explanation of symbols]
C1, C2 Capacitors I11, I12 Current M1 P-type MOS transistor M2 N-type MOS transistors R11, R12, R21, R22 Resistors R11, R12, SW11, SW12, SW21, SW22 Switch VA Constant voltage VC Analog common voltage VOUT Analog output VS Constant Voltage (steady value)

Claims (6)

A reference voltage generation circuit for generating a predetermined reference voltage and outputting the generated reference voltage from a voltage generation terminal; and connecting the voltage generation terminal to an operation reference voltage terminal of an operational amplifier to generate the generated reference voltage A mute circuit for applying to the operation reference voltage terminal and controlling the potential of the operation reference voltage terminal to a ground level to mute the output signal of the operational amplifier;
The reference voltage generation circuit includes:
Voltage source is, the gate is the ground through said P-type MOS transistor and the first switch and the first resistor to the output terminal of the drain to the source and the input terminal of the voltage source side said voltage generating terminal side Connected to the voltage generation terminal,
The voltage generating terminal is grounded via a capacitor;
The voltage generation terminal includes an N-type MOS transistor having a gate connected to the voltage source, a source as an input terminal on the ground side, and a drain as an output terminal on the voltage generation terminal side, a second switch, and a second resistor. Grounded through
During the mute operation, the first switch is turned off and the second switch is turned on to bring the potential of the operation reference voltage terminal to the ground level. During the non-mute operation, the first switch is turned on. The mute circuit is characterized in that the potential of the operation reference voltage terminal is set to the reference voltage by turning off the second switch. A reference voltage generation circuit for generating a predetermined reference voltage and outputting the generated reference voltage from a voltage generation terminal; and connecting the voltage generation terminal to an operation reference voltage terminal of an operational amplifier to generate the generated reference voltage A mute circuit that applies to the operation reference voltage terminal and controls the potential of the operation reference voltage terminal to a ground level to mute the output signal of the operational amplifier;
The reference voltage generation circuit includes:
Voltage source is, the gate is the ground through said P-type MOS transistor and the first switch and the first resistor to the output terminal of the drain to the source and the input terminal of the voltage source side said voltage generating terminal side Connected to the voltage generation terminal,
The voltage generating terminal is grounded via a capacitor;
The voltage generating terminal is grounded via a second switch and a second resistor;
During the mute operation, the first switch is turned off and the second switch is turned on to bring the potential of the operation reference voltage terminal to the ground level. During the non-mute operation, the first switch is turned on. The mute circuit is characterized in that the potential of the operation reference voltage terminal is set to the reference voltage by turning off the second switch. A reference voltage generation circuit for generating a predetermined reference voltage and outputting the generated reference voltage from a voltage generation terminal; and connecting the voltage generation terminal to an operation reference voltage terminal of an operational amplifier to generate the generated reference voltage A mute circuit for applying to the operation reference voltage terminal and controlling the potential of the operation reference voltage terminal to a ground level to mute the output signal of the operational amplifier;
The reference voltage generation circuit includes:
Voltage source is connected to said voltage generating terminal via a first switch and a first resistor,
The voltage generating terminal is grounded via a capacitor;
The voltage generation terminal includes an N-type MOS transistor having a gate connected to the voltage source, a source as an input terminal on the ground side, and a drain as an output terminal on the voltage generation terminal side, a second switch, and a second resistor. Grounded through
During the mute operation, the first switch is turned off and the second switch is turned on to bring the potential of the operation reference voltage terminal to the ground level. During the non-mute operation, the first switch is turned on. The mute circuit is characterized in that the potential of the operation reference voltage terminal is set to the reference voltage by turning off the second switch. A reference voltage generation circuit for generating a predetermined reference voltage and outputting the generated reference voltage from a voltage generation terminal;
Voltage source is, the gate is the ground through said P-type MOS transistor and the first switch and the first resistor to the output terminal of the drain to the source and the input terminal of the voltage source side said voltage generating terminal side Connected to the voltage generation terminal,
The voltage generating terminal is grounded via a capacitor;
The voltage generation terminal includes an N-type MOS transistor having a gate connected to the voltage source, a source as an input terminal on the ground side, and a drain as an output terminal on the voltage generation terminal side, a second switch, and a second resistor. Grounded through
By turning off the first switch and turning on the second switch, the potential of the voltage generation terminal is set to the ground level, the first switch is turned on, and the second switch is turned off. A reference voltage generating circuit characterized in that the potential of the voltage generating terminal is the reference voltage. A reference voltage generation circuit for generating a predetermined reference voltage and outputting the generated reference voltage from a voltage generation terminal;
Voltage source is, the gate is the ground through said P-type MOS transistor and the first switch and the first resistor to the output terminal of the drain to the source and the input terminal of the voltage source side said voltage generating terminal side Connected to the voltage generation terminal,
The voltage generating terminal is grounded via a capacitor;
The voltage generating terminal is grounded via a second switch and a second resistor;
By turning off the first switch and turning on the second switch, the potential of the voltage generation terminal is set to the ground level, the first switch is turned on, and the second switch is turned off. A reference voltage generating circuit characterized in that the potential of the voltage generating terminal is the reference voltage. A reference voltage generation circuit for generating a predetermined reference voltage and outputting the generated reference voltage from a voltage generation terminal;
Voltage source is connected to said voltage generating terminal via a first switch and a first resistor,
The voltage generating terminal is grounded via a capacitor;
The voltage generation terminal includes an N-type MOS transistor having a gate connected to the voltage source, a source as an input terminal on the ground side, and a drain as an output terminal on the voltage generation terminal side, a second switch, and a second resistor. Grounded through
By turning off the first switch and turning on the second switch, the potential of the voltage generation terminal is set to the ground level, the first switch is turned on, and the second switch is turned off. A reference voltage generating circuit characterized in that the potential of the voltage generating terminal is the reference voltage.

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