JP5749137B2 - Audio signal processing circuit and electronic device using the same - Google Patents

Description

  The present invention relates to an audio signal processing circuit that processes an audio signal.

  An electronic device including a speaker and a headphone terminal is equipped with an audio signal processing circuit that amplifies an audio signal. In general, an audio signal processing circuit includes a plurality of stages of amplifiers or buffers connected in series.

  The amplitude of the audio signal increases as the subsequent stage increases. Therefore, from the viewpoint of efficiency, it is preferable to supply different power supply voltages to a plurality of stages of amplifiers. Specifically, a low power supply voltage is supplied to the front-stage amplifier and a high power supply voltage is supplied to the back-stage amplifier, so that both low distortion and high efficiency can be achieved.

Japanese Patent Laid-Open No. 2005-117489 JP 2005-217710 A JP 2004-222077 A JP 11-340759 A JP 2003-283262 A

As a result of studying a multi-stage amplifier, the present inventor has recognized the following problems.
FIG. 1 is a block diagram showing a configuration of an audio signal processing circuit including a two-stage amplifier studied by the present inventor. The first amplifier AMP1 in the previous stage is a gain 1 buffer (voltage follower), and the power supply terminal is supplied with the first power supply voltage VCC1. The second amplifier AMP2 at the subsequent stage is a non-inverting amplifier having a gain g2, and a second power supply voltage VCC2 higher than the first power supply voltage VCC1 is supplied to the power supply terminal.

  The output of the second amplifier AMP2 is supplied to the power amplifier PA via the direct current prevention capacitor C1. The power amplifier PA amplifies the output signal of the second amplifier AMP2 and supplies it to an electroacoustic transducer (hereinafter referred to as a speaker) SPK such as a speaker or a headphone.

In a normal operation state (non-mute state), the DC level of the input voltage and output voltage Va of the first amplifier AMP1 is maintained at a predetermined bias voltage VBIAS1. Preferably, the bias voltage VBIAS1 is the midpoint voltage VCC1 / 2 of the power supply voltage VCC1 for the first amplifier AMP1. When the AC signal component of the audio signal S1 is written as Vsig, the output Va of the first amplifier AMP1 is given by Expression (1).
Va = Vsig + VBIAS1 (1)

  The first amplifier AMP1 is provided with a mute function. The first amplifier AMP1 outputs a predetermined bias voltage VBIAS1 in the mute state. The first amplifier AMP1 is configured such that the mute state and the non-mute state can be switched seamlessly, and may be configured integrally with the amplifier AMP1. When the audio signal processing circuit 100r is activated, the first amplifier AMP1 is set to the mute state.

On the other hand, the output voltage Vb of the second amplifier AMP2 is given by Expression (1) using the input voltage Va and the bias voltage VBIAS3.
Vb = (1 + R1 / R2) × Va−R1 / R2 × VBIAS3 (2)
(1 + R1 / R2) is the gain g2 of the second amplifier AMP2.

Substituting equation (1) into equation (2) yields equation (3).
Vb = g2 × Vsig + VBIAS2 (3)
VBIAS2 = {(1 + R1 / R2) × VBIAS1-R1 / R2 × VBIAS3}
That is, the output voltage Vb of the second amplifier AMP2 has a waveform in which the signal Vsig amplified by the gain g2 is superimposed on the DC level VBIAS2.

  The DC level VBIAS2 of the output voltage Vb of the second amplifier AMP2 is desirably the midpoint voltage VCC2 / 2 of the power supply voltage VCC2 for the second amplifier AMP2. The bias voltage VBIAS3 is set so that VBIAS2 = VCC2 / 2 holds.

  If the bias voltage VBIAS2 is constant, it is removed by the DC blocking capacitor C1, and the audio signal Vb '= g2 * Vsig is supplied to the power amplifier PA. The power amplifier PA amplifies the output signal of the second amplifier AMP2 and supplies it to an electroacoustic transducer (hereinafter referred to as a speaker) SPK such as a speaker or a headphone.

  Now, consider the situation where the second power supply voltage VCC2 rises before the first power supply voltage VCC1. FIG. 2 is a waveform diagram showing the operation of the audio signal processing circuit 100r of FIG. In a situation where the second power supply voltage VCC2 is sufficiently high, the second amplifier AMP2 operates normally, and the output voltage Vb of the second amplifier AMP2 becomes a level corresponding to the input voltage Va. However, when the second power supply voltage VCC2 is low, the second amplifier AMP2 does not operate normally. In this specification, a region where the power supply voltage is high and the amplifier operates normally is referred to as a “stable region”, a region where the power supply voltage is low and the amplifier does not operate normally is referred to as an “unstable region”, and the threshold voltage is defined as “stable operation”. This is called “threshold”. Further, a period in which the second amplifier AMP2 operates in an unstable region immediately after startup is referred to as a “transition period”.

  On the other hand, when the first power supply voltage VCC1 is low, the first amplifier AMP1 operates in an unstable region, so the output of the first amplifier AMP1 becomes high impedance, and the output voltage Va becomes indefinite. As shown in FIG. 2, when the second amplifier AMP2 operates in an unstable region, if the input voltage Va is indefinite, the output voltage Vb rapidly increases toward the power supply voltage VCC2, and then A transition is made by sticking to the power supply voltage VCC2.

  Thereafter, when the first power supply voltage VCC1 for the first amplifier AMP1 increases, the first amplifier AMP1 operates normally and the level of the output voltage of the first amplifier AMP1 is determined. As a result, the output voltage Vb of the second amplifier AMP2 changes steeply toward a level corresponding to the output voltage of the first amplifier AMP1.

  When a voltage change that occurs at the output of the second amplifier AMP2 in this way is input to the speaker SPK, noise (shock sound) is output. When the voltage change width is small, it can be removed by the mute transistor Tr1, but when the change width becomes 1V or more, it becomes difficult to remove by the mute transistor Tr1.

When different power supply voltages are supplied to the amplifiers in this way, the output voltage of the audio signal processing circuit is affected by the startup sequence of the power supply circuit that generates each power supply voltage.
Although it is possible to suppress noise by optimizing the startup sequence of the two power supply voltages VCC1 and VCC2 so that noise does not occur, this method complicates system design.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and one of exemplary purposes of an embodiment thereof is to provide an audio signal processing circuit that suppresses noise.

  One embodiment of the present invention relates to an audio signal processing circuit. The audio signal processing circuit includes a first buffer, a second buffer, a non-inverting amplifier, a starting voltage source, a switch, and a control circuit. The first buffer includes a first operational amplifier having a power supply terminal receiving a first power supply voltage from a first power supply, a non-inverting input terminal receiving an audio signal, and an inverting input terminal connected to the output terminal. . The second buffer includes a second operational amplifier that receives a predetermined bias voltage at its non-inverting input terminal and whose inverting input terminal is connected to its output terminal. The non-inverting amplifier receives a second power supply voltage from a second power supply different from the first power supply at its power supply terminal, and a third operational amplifier in which the output voltage of the first operational amplifier is input to its non-inverting input terminal; A first voltage dividing circuit that divides the output voltage of the second operational amplifier and the output voltage of the third operational amplifier and applies the divided voltage to the inverting input terminal of the third operational amplifier. The startup voltage source receives the second power supply voltage at its power supply terminal and generates a startup voltage. The switch is provided between the output terminal of the starting voltage source and the non-inverting input terminal of the third operational amplifier. The control circuit turns on when the second power supply voltage is lower than a predetermined threshold voltage, and turns off the switch when the second power supply voltage is higher than the threshold voltage.

  When the first power supply voltage is started later than the second power supply voltage, the output of the first buffer is in a high impedance state. On the other hand, since the starting voltage source operates by receiving the second power supply voltage, the starting voltage is determined at an earlier time than the first buffer. When the switch is turned on during the transition period of the second amplifier, the start-up voltage from the start-up voltage source is input to the non-inverting amplifier. As a result, the output voltage of the non-inverting amplifier during the transition period does not stick to the second power supply voltage but takes a value corresponding to the start-up voltage, so that the voltage change occurring in the output voltage of the second amplifier can be suppressed, and the noise Can be reduced.

The start-up voltage source receives a second power supply voltage, generates a bias voltage, receives the second power supply voltage at its power supply terminal, receives the bias voltage from the voltage source at its non-inverting input terminal, and inverts it And a fourth buffer that includes a fourth operational amplifier connected to the output terminal of the input terminal and that generates a starting voltage.
The voltage source may include a second voltage dividing circuit that divides the second power supply voltage.

  An audio signal processing circuit according to an aspect may include a plurality of channels including a first operational amplifier, a second operational amplifier, a third operational amplifier, a starting voltage source, and a set of switches. A single starting voltage source and a single control circuit may be shared by multiple channels.

  Another embodiment of the present invention relates to an electronic device. The electronic apparatus is driven by the audio signal processing circuit according to any one of the above-described aspects, a power amplifier that receives the output signal of the non-inverting amplifier of the audio signal processing circuit through the DC prevention capacitor, and amplifies it. An electroacoustic transducer.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  The audio signal processing circuit according to the present invention can suppress noise.

It is a block diagram which shows the structure of the audio signal processing circuit containing the amplifier of 2 steps | paragraphs which this inventor examined. It is a wave form diagram which shows operation | movement of the audio signal processing circuit of FIG. It is a circuit diagram which shows the structure of an electronic device provided with the audio signal processing circuit which concerns on embodiment. FIG. 4 is a circuit diagram illustrating a configuration example of a control circuit in FIG. 3. FIG. 5 is a waveform diagram showing an operation of the control circuit of FIG. 4. FIG. 4 is a simulation waveform diagram showing an operation of the audio signal processing circuit of FIG. 3.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A and the member B are connected” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected to each other. It includes a case where the connection state is not indirectly affected, or the connection and the connection are indirectly made through other members that do not impair the functions and effects achieved by the connection. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as their electric It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.

  FIG. 3 is a circuit diagram illustrating a configuration of the electronic apparatus 1 including the audio signal processing circuit 100 according to the embodiment. The electronic device 1 reproduces a multi-channel audio signal. The electronic device 1 includes an audio signal processing circuit 100, a power amplifier PA provided for each channel, and an electroacoustic conversion element (hereinafter collectively referred to as a speaker) SPK such as a speaker or a headphone provided for each channel. Prepare.

  Each channel of the audio signal processing circuit 100 is similarly configured. For the i-th channel (i is a natural number), the audio signal processing circuit 100 includes a first buffer 10_i, a second buffer 12_i, a non-inverting amplifier 14_i, a switch SW1_i, a starting voltage source 16, and a control circuit 20, and includes one semiconductor. It is integrated on the substrate. “Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate. The starting voltage source 16 and the control circuit 20 are shared by a plurality of channels.

  The audio signal processing circuit 100 receives a first power supply voltage VCC1 from a first power supply (not shown), and receives a second power supply voltage VCC2 from a second power supply (not shown).

  The first buffer 10_i includes a first operational amplifier OA1. The first power supply voltage VCC1 from the first power supply is supplied to the power supply terminal of the first operational amplifier OA1. The audio signal S1_i of the corresponding channel is input to the non-inverting input terminal (+) of the first operational amplifier OA1, and the inverting input terminal (−) is connected to the output terminal. The first buffer 10 — i is a voltage follower having a gain of 1 (0 dB).

  The second buffer 12_i includes a second operational amplifier OA2. The first power supply voltage VCC1 from the first power supply is supplied to the power supply terminal of the second operational amplifier OA2. A predetermined bias voltage VBIAS3 is input to the non-inverting input terminal (+) of the second operational amplifier OA2, and its inverting input terminal (−) is connected to its output terminal. The bias voltage VBIAS3 is desirably determined so that the DC level VBIAS2 of the output voltage Vb of the non-inverting amplifier 14_1 is VCC2 / 2.

  By supplying the first power supply voltage VCC1 to the second operational amplifier OA2, the second operational amplifier OA2 can be configured with a low withstand voltage element as compared with the case where the second power supply voltage VCC2 is supplied, so that the circuit area can be reduced.

  If the circuit area does not matter, it is preferable to supply the second power supply voltage VCC2 to the second operational amplifier OA2. As a result, when the second power supply voltage VCC2 rises, the output VSTART of the starting voltage source 16 and the output voltage VBIAS of the second buffer 12 can be raised in agreement.

  The non-inverting amplifier 14_i includes a third operational amplifier OA3 and first voltage dividing circuits R1 and R2. The second power supply voltage VCC2 from the second power supply is supplied to the power supply terminal of the third operational amplifier OA3. The output voltage of the first operational amplifier OA1 is input to the non-inverting input terminal (+) of the third operational amplifier OA3. The voltage dividing circuits R1 and R2 divide the output voltage of the second operational amplifier OA2 and the output voltage of the third operational amplifier OA3 and apply them to the inverting input terminal (−) of the third operational amplifier OA3. The non-inverting amplifier 14_i has a gain g2 given by (1 + R1 / R2).

The power supply terminal of the starting voltage source 16 is supplied with the second power supply voltage VCC2. The start-up voltage source 16 generates the start-up voltage VSTART when the second power supply voltage VCC2 is supplied. For example, the starting voltage source 16 may include second voltage dividing circuits R3 and R4 and a fourth operational amplifier OA4. The second voltage dividing circuits R3 and R4 divide the second power supply voltage VCC2 by 1/2 to generate a bias voltage VBIAS = VCC2 / 2. The second power supply voltage VCC2 is supplied to the power supply terminal of the fourth operational amplifier OA4. The output voltage VBIAS of the second voltage dividing circuits R3 and R4 is input to the non-inverting input terminal (+) of the fourth operational amplifier OA4, and the inverting input terminal (−) is connected to the output terminal. The starting voltage VSTART is output from the fourth operational amplifier OA4.
The starting voltage source 16 only needs to be able to generate the starting voltage VSTART based on the second power supply voltage VCC2, and its configuration is not particularly limited. For example, the bias voltage VBIAS may be generated by a voltage source of a different type from the resistors R3 and R4.

  The switch SW1_i is provided between the output terminal of the activation voltage source 16 and the non-inverting input terminal (+) of the third operational amplifier OA3 of the corresponding non-inverting amplifier 14_i. For example, the switch SW1_i is composed of an N-channel MOSFET, and is turned on when the control signal S2 applied to its gate is a high level voltage and turned off when the control signal S2 is a low level voltage.

  The control circuit 20 receives the second power supply voltage VCC2, and turns on the switch SW1 of each channel when the second power supply voltage VCC2 is lower than a predetermined threshold voltage Vth1, and the second power supply voltage VCC2 is the threshold voltage. When higher than Vth1, the switch SW1 of each channel is turned off.

FIG. 4 is a circuit diagram showing a configuration example of the control circuit 20 of FIG. The control circuit 20 includes a first resistor Ra1 to a third resistor Ra3, a transistor M1, and a capacitor C2. The first resistor Ra1 and the second resistor Ra2 are sequentially provided in series between a power supply line to which the second power supply voltage VCC2 is applied and a ground line to which the ground voltage VSS is supplied. The third resistor Ra3 and the transistor M1 are sequentially provided in series between the power supply line and the ground line. The potential V _N1 of the connection point N1 between the first resistor Ra1 and the second resistor Ra2 given by the equation (4) is applied to the control terminal (gate) of the transistor M1.
V _N1 = VCC2 × Ra2 / (Ra1 + Ra2) (4)
The voltage V _{N2 at} the connection point N2 between the transistor M1 and the third resistor Ra3 is smoothed by the capacitor C2, and the control signal S2 is generated.

The control signal S2 is at a high level when the voltage V _{N1 at the} node N1 is smaller than the threshold voltage V _TH between the gate and source of the transistor M1, and is at a low level when it is larger. The control signal S2 is at a high level (VCC2) when VCC2 <Vth1, and is at a low level (VSS = 0) when VCC2> Vth1. The threshold voltage Vth1 is given by equation (5).
Vth1 = V _TH × (Ra1 + Ra2) / Ra2 (5)

  The control circuit 20 is designed so that the threshold voltage Vth1 matches the threshold voltage at the boundary between the unstable region and the stable region of the non-inverting amplifier 14. FIG. 5 is a waveform diagram showing the operation of the control circuit 20 of FIG. When the second power supply is activated, the second power supply voltage VCC2 increases with time. In the region where the second power supply voltage VCC2 is lower than the threshold voltage Vth1, S2 = VCC2. When the second power supply voltage VCC2 becomes higher than the threshold voltage Vth1, the control signal S2 becomes low level. As described above, the threshold voltage Vth1 is set equal to the stable operation threshold value of the non-inverting amplifier 14, and therefore the control signal S2 takes a high level during the transition period τ and a low level during the subsequent stable operation period.

  The above is the configuration of the audio signal processing circuit 100. Next, the operation will be described. FIG. 6 is a simulation waveform diagram showing the operation of the audio signal processing circuit 100 of FIG. FIG. 6 shows the first power supply voltage VCC1, the second power supply voltage VCC2, the control signal S2, and the output voltage Vb of the non-inverting amplifier 14. In addition, the output voltage Vb ′ generated in FIG. 1 is indicated by a one-dot chain line.

First, in order to clarify the effect of the audio signal processing circuit 100 according to the embodiment, the operation of the audio signal processing circuit 100r in FIG. 1 will be described again.
At startup, the first buffer 10 is set to the mute state, and the audio signal S1 is blocked. Prior to the first power supply voltage VCC1, the second power supply voltage VCC2 starts to rise. Immediately after startup, since the first power supply voltage VCC1 is low, the first buffer 10 does not operate. Therefore, the output of the first buffer 10 becomes high impedance, and the output voltage Va becomes indefinite.

  In the transition period τ immediately after startup, the non-inverting amplifier 14 operates in an unstable region. If the input voltage Va is indefinite at this time, the output voltage Vb rises steeply toward the second power supply voltage VCC2 (time t1). Subsequently, when the first power supply voltage VCC1 rises, the output of the first buffer 10 becomes low impedance, and the input voltage Va of the non-inverting amplifier 14 is determined. Then, the output voltage Vb of the non-inverting amplifier 14 changes sharply to a voltage level corresponding to the input voltage Va (time t2).

  As described above, in the audio signal processing circuit 100r of FIG. 1, when the first power supply voltage VCC1 rises behind the second power supply voltage VCC2, the output voltage of the non-inverting amplifier 14 varies.

Next, the operation of the audio signal processing circuit 100 in FIG. 3 will be described.
The fourth operational amplifier OA4 of the starting voltage source 16 is supplied with the second power supply voltage VCC2 instead of the first power supply voltage VCC1. Therefore, the output of the startup voltage source 16 changes from a high impedance to a low impedance at an earlier time than the first buffer 10, and the startup voltage VSTART is output from the startup voltage source 16.

  When the control signal S2 rises with the rise of the second power supply voltage VCC2 and the switch SW1 is turned on, the starting voltage VSTART is input to the non-inverting amplifier 14 (time t3). As a result, the output voltage Vb of the non-inverting amplifier 14 transitions to a level corresponding to the starting voltage VSTART, but the amount of change at this time is sufficiently smaller than the amount of change of the output voltage Vb ′ at time t1.

  As described above, according to the audio signal processing circuit 100 of FIG. 3, it is possible to suppress the fluctuation of the output voltage Vb in the transition period τ, compared to the audio signal processing circuit 100 r of FIG. 1. If the change amount of the output voltage Vb is small, it can be removed by the mute transistor, or the mute transistor itself may be omitted.

  Further, since the activation voltage source 16 and the control circuit 20 are shared by a plurality of channels, the power consumption and the circuit area are not so large compared to the audio signal processing circuit 100r of FIG. In the case where an increase in power consumption and circuit area is allowed, the activation voltage source 16 and the control circuit 20 may be provided for each channel.

  Although the multi-channel audio signal processing circuit 100 has been described in the embodiment, the present invention is also effective for a single channel.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 ... Electronic device, 100 ... Audio signal processing circuit, 10 ... 1st buffer, 12 ... 2nd buffer, 14 ... Non-inverting amplifier, 16 ... Start-up voltage source, SW1 ... Switch, 20 ... Control circuit, OA1 ... 1st calculation Amplifier, OA2 ... second operational amplifier, OA3 ... third operational amplifier, OA4 ... fourth operational amplifier, VCC1 ... first power supply voltage, VCC2 ... second power supply voltage.

Claims (7)

A first buffer that includes a first operational amplifier that receives a first power supply voltage from a first power supply at its power supply terminal, an audio signal at its non-inverting input terminal, and an inverting input terminal connected to its output terminal;
A second buffer including a second operational amplifier that receives a predetermined bias voltage at its non-inverting input terminal, and whose inverting input terminal is connected to the output terminal;
A third operational amplifier in which a second power supply voltage from a second power supply different from the first power supply is received at the power supply terminal, and an output voltage of the first operational amplifier is input to the non-inverting input terminal; And a first voltage dividing circuit that divides the output voltage of the third operational amplifier and applies it to the inverting input terminal of the third operational amplifier, and a non-inverting amplifier,
A starting voltage source that receives the second power supply voltage at its power supply terminal and generates a starting voltage;
A switch provided between an output terminal of the starting voltage source and a non-inverting input terminal of the third operational amplifier;
A control circuit that turns on the switch when the second power supply voltage is lower than a predetermined threshold voltage, and turns off the switch when the second power supply voltage is higher than the threshold voltage;
An audio signal processing circuit comprising: The starting voltage source is
A voltage source that receives the second power supply voltage and generates a bias voltage;
A fourth operational amplifier having the power supply terminal receiving the second power supply voltage, the non-inverting input terminal receiving the bias voltage from the voltage source, and the inverting input terminal connected to the output terminal; A fourth buffer for generating
The audio signal processing circuit according to claim 1, further comprising:   3. The audio signal processing circuit according to claim 2, wherein the voltage source includes a second voltage dividing circuit that divides the second power supply voltage. The control circuit includes:
A first resistor and a second resistor provided in series between a power supply line to which the second power supply voltage is applied and a ground line;
A third resistor and a transistor provided in series between the power line and the ground line in order,
Including
A potential at a connection point between the first resistor and the second resistor is applied to a control terminal of the transistor, and a voltage at a connection point between the transistor and the third resistor is output as a control signal for the switch. The audio signal processing circuit according to claim 1, wherein the audio signal processing circuit is according to claim 1. A plurality of channels including the first operational amplifier, the second operational amplifier, the third operational amplifier, the starting voltage source, and the switch set;
5. The audio signal processing circuit according to claim 1, wherein the single start-up voltage source and the single control circuit are shared by a plurality of channels.   6. The audio signal processing circuit according to claim 1, wherein the audio signal processing circuit is monolithically integrated on one semiconductor substrate. The audio signal processing circuit according to any one of claims 1 to 6,
A power supply for supplying a first power supply voltage and a second power supply voltage to the audio signal processing circuit;
A power amplifier for receiving the output signal of the non-inverting amplifier of the audio signal processing circuit via a DC prevention capacitor and amplifying it;
An electroacoustic transducer driven by the power amplifier;
An electronic device comprising:

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