JP4160790B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP4160790B2
JP4160790B2 JP2002189513A JP2002189513A JP4160790B2 JP 4160790 B2 JP4160790 B2 JP 4160790B2 JP 2002189513 A JP2002189513 A JP 2002189513A JP 2002189513 A JP2002189513 A JP 2002189513A JP 4160790 B2 JP4160790 B2 JP 4160790B2
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JP
Japan
Prior art keywords
memory
address
cache memory
cache
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002189513A
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English (en)
Japanese (ja)
Other versions
JP2004030517A (ja
JP2004030517A5 (enExample
Inventor
誓士 三浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2002189513A priority Critical patent/JP4160790B2/ja
Priority to US10/457,609 priority patent/US6928003B2/en
Publication of JP2004030517A publication Critical patent/JP2004030517A/ja
Priority to US11/155,504 priority patent/US7328311B2/en
Publication of JP2004030517A5 publication Critical patent/JP2004030517A5/ja
Application granted granted Critical
Publication of JP4160790B2 publication Critical patent/JP4160790B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30—Providing cache or TLB in specific location of a processing system
    • G06F2212/304—In main memory subsystem
    • G06F2212/3042—In main memory subsystem being part of a memory device, e.g. cache DRAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2245—Memory devices with an internal cache buffer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Dram (AREA)
  • Memory System (AREA)
JP2002189513A 2002-06-28 2002-06-28 半導体装置 Expired - Fee Related JP4160790B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2002189513A JP4160790B2 (ja) 2002-06-28 2002-06-28 半導体装置
US10/457,609 US6928003B2 (en) 2002-06-28 2003-06-10 Memory controller controlling cached DRAM
US11/155,504 US7328311B2 (en) 2002-06-28 2005-06-20 Memory controller controlling cashed DRAM

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002189513A JP4160790B2 (ja) 2002-06-28 2002-06-28 半導体装置

Publications (3)

Publication Number Publication Date
JP2004030517A JP2004030517A (ja) 2004-01-29
JP2004030517A5 JP2004030517A5 (enExample) 2005-10-20
JP4160790B2 true JP4160790B2 (ja) 2008-10-08

Family

ID=29774301

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002189513A Expired - Fee Related JP4160790B2 (ja) 2002-06-28 2002-06-28 半導体装置

Country Status (2)

Country Link
US (2) US6928003B2 (enExample)
JP (1) JP4160790B2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005085289A (ja) * 2003-09-04 2005-03-31 Elpida Memory Inc 半導体記憶装置
US20070005902A1 (en) * 2004-12-07 2007-01-04 Ocz Technology Group, Inc. Integrated sram cache for a memory module and method therefor
US7983091B2 (en) * 2007-11-06 2011-07-19 Intel Corporation Divided bitline flash memory array with local sense and signal transmission
KR101132797B1 (ko) * 2010-03-30 2012-04-02 주식회사 하이닉스반도체 모듈제어회로를 포함하는 반도체모듈 및 반도체모듈의 제어방법
KR102094902B1 (ko) * 2013-07-08 2020-03-30 삼성전자주식회사 액티브 상태에서 인터페이스 모드를 전환하는 스토리지 시스템 및 ufs 시스템
US9779025B2 (en) 2014-06-02 2017-10-03 Micron Technology, Inc. Cache architecture for comparing data
US9805802B2 (en) 2015-09-14 2017-10-31 Samsung Electronics Co., Ltd. Memory device, memory module, and memory system

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04255989A (ja) * 1991-02-07 1992-09-10 Mitsubishi Electric Corp 半導体記憶装置および内部電圧発生方法
US5771367A (en) * 1992-12-17 1998-06-23 International Business Machines Corporation Storage controller and method for improved failure recovery using cross-coupled cache memories and nonvolatile stores
US5822772A (en) * 1996-03-22 1998-10-13 Industrial Technology Research Institute Memory controller and method of memory access sequence recordering that eliminates page miss and row miss penalties
US5983313A (en) * 1996-04-10 1999-11-09 Ramtron International Corporation EDRAM having a dynamically-sized cache memory and associated method
US5848428A (en) * 1996-12-19 1998-12-08 Compaq Computer Corporation Sense amplifier decoding in a memory device to reduce power consumption
JP3161384B2 (ja) * 1997-09-16 2001-04-25 日本電気株式会社 半導体記憶装置とそのアクセス方法
US5983325A (en) * 1997-12-09 1999-11-09 Advanced Micro Devices, Inc. Dataless touch to open a memory page
JP3786521B2 (ja) * 1998-07-01 2006-06-14 株式会社日立製作所 半導体集積回路及びデータ処理システム
JP3178423B2 (ja) * 1998-07-03 2001-06-18 日本電気株式会社 バーチャルチャネルｓｄｒａｍ
US6415353B1 (en) * 1998-10-01 2002-07-02 Monolithic System Technology, Inc. Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same
US6629207B1 (en) * 1999-10-01 2003-09-30 Hitachi, Ltd. Method for loading instructions or data into a locked way of a cache memory
JP2002063069A (ja) * 2000-08-21 2002-02-28 Hitachi Ltd メモリ制御装置、データ処理システム及び半導体装置

Also Published As

Publication number Publication date
US20050232060A1 (en) 2005-10-20
US7328311B2 (en) 2008-02-05
US6928003B2 (en) 2005-08-09
JP2004030517A (ja) 2004-01-29
US20040001362A1 (en) 2004-01-01

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